JP3281833B2 - PLL circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL circuit having a variable frequency dividing device capable of dividing a frequency dividing ratio by a fraction or 1/2.

[0002]

2. Description of the Related Art In a conventional radio receiver, SW / MW switching of a PLL circuit used for a radio is shown in FIG.
It will be described based on. The inter-station frequency of SW is 5 kHz, and the inter-station frequency of MW is 9 kHz (Japan or Europe) or 10 kHz (US). Therefore, VC for SW
The tuning frequency of O must be in units of 5 kHz, and the tuning frequency of the VCO for MW is 9 kHz or 10 kHz.
It must be in kHz. For this reason, the frequency of the reference signal output from the reference oscillator is 5 kHz when in the SW mode.
z and 9 kHz or 10 kHz at MW.

[0003]

However, the output of the LPF (low-frequency filter) changes according to the cutoff frequency based on the time constant constituting the LPF.

For this purpose, as shown in FIG. 5, a resistor (R1) and a capacitor (C1) set to a time constant for SW are used.
And a circuit of a resistor (R2) and a capacitor (C2) set to a time constant for MW are provided and switched.

As described above, conventionally, it is necessary to provide a plurality of time constants in the LPF and switch between them.

[0006]

[0007]

In order to solve the above problems, the present invention provides a radio band SW voltage controlled oscillator, a MW voltage controlled oscillator, the SW voltage controlled oscillator and the MW voltage controlled oscillator. And a variable frequency dividing device capable of variably dividing the output of the SW voltage controlled oscillator or the MW voltage controlled oscillator by a dividing ratio of 1/2 unit, a SW reference signal or the SW reference. A reference oscillator for selectively outputting a MW reference signal having the same or similar frequency as a signal, a phase comparator for comparing a reference signal of the reference oscillator with an output of the variable frequency divider, and an output of the phase comparator Is converted into a control voltage with a time constant shared by the SW reference signal and the MW reference signal, and is output to the voltage controlled oscillator, and the MW reference signal is output from the reference signal oscillator. Both Step 1 the variable frequency divider device
Control means having a MW mode for dividing the frequency by the dividing ratio of and a SW mode for outputting the SW reference signal from the reference oscillator and dividing the variable frequency dividing device by a dividing ratio of ス テ ッ プ step. .

[0008]

Embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a main part of an embodiment of the present invention. (1) is a VCO (Voltage Controlled Oscillator) for SW, which inputs a local oscillation frequency to a mixing unit (not shown) of the SW radio unit (R1). (2) is a VCO for MW, which inputs a local oscillation frequency to a mixing unit (not shown) of a radio unit (R2) of MW. (3) is a switch,
The connection of the VCO (1) for SW and the VCO (2) for MW to the variable frequency divider (4) described later is switched.

[0009] (4) is a variable frequency dividing device, and V for SW
Output of CO (1) or VCO (2) for MW (f
i) is variably frequency-divided at a pitch of 1/2 the frequency division ratio.

As an example of this apparatus, FIG. 2 shows a configuration described in Japanese Patent Application No. 8-257164, which is the same applicant as the present invention. Detailed description is omitted, and will be briefly described.
In this configuration, when J0 is "H", the first means for alternately outputting a signal of frequency division by N and the signal of frequency division by N + 1, and a second means for outputting a signal delayed by a half cycle from the first means. Means, and third means for alternately outputting the first means and the second means,
As shown in FIG. 3, N + ／ frequency division is performed. When J0 is "L", the frequency is divided by N as shown in FIG. Therefore, the variable frequency dividing device shown in FIG. 2 can perform frequency division at a division ratio of 1/2 pitch.

A variable frequency dividing device capable of dividing the frequency at a frequency dividing ratio of 1/2 pitch is disclosed in Japanese Patent Application No. Hei.
No. 5,769 (pulse deletion method) and Japanese Patent Application No. Hei 8-4215 (adder method). The description of these configurations and operations will be omitted.

Reference numeral (5) denotes a reference oscillator which outputs a 10 kHz reference signal for SW and a 9 kHz frequency for MW in Japan and Europe and a 10 kHz reference signal in the United States for MW. That is, in the United States, it is a common SW / MW reference signal.

A phase comparator (6) compares the phase of the reference signal (fr) output from the reference oscillator (5) with the phase of the signal (fv) output from the variable frequency divider (4).

(7) is an LPF (low frequency filter),
The output of the phase comparator (6) is converted into a control voltage with a predetermined time constant and output to the VCO (1) for SW and the VCO (2) for MW. The time constant is set by the value of the resistance (R) and the value of the capacitor (C) of the time constant circuit (71). Conventionally, there are two types of time constants for SW and MW,
The LPF (7) of the present invention is one time constant shared by SW and MW. The value of this shared time constant is set to be optimal at 10 kHz for US specifications, and is set to be optimal at 9.5 kHz between SW and MW for Japan and Europe. .

A control circuit (8) controls the switch (3), the variable frequency divider (4) and the reference oscillator (5) based on a band changeover switch (not shown).

The operation of the control circuit (8) will be described. In the case of Japanese specifications, when the band changeover switch is switched to MW, the switch (3) is switched to the VCO (2) for MW, a 9 kHz signal is output from the reference oscillator, and the frequency dividing ratio of the variable frequency dividing device is changed. Divide by one pitch. Thereby, the local oscillation frequency to the radio unit (R2) of the MW VCO (2) is 9 kHz (reference signal) × 1 (pitch) = 9 k
Hz.

When the band switch is switched to SW, the switch (3) is switched to the VCO (1) for SW.
And a 10 kHz signal is output from the reference oscillator, and the frequency dividing ratio of the variable frequency dividing device is divided by 1/2 pitch. Thereby, the radio section (R) of the SW VCO (1)
The local oscillation frequency to 1) is 10 kHz (reference signal) x 1
/ 2 (pitch) = 5 kHz.

At this time, the time constant of the LPF (7) is 9.5.
Although set to kHz, the difference between SW and MW is as small as 0.5 kHz, and the lock-up time and overshoot are practically allowable.

In the case of US specification, the reference frequency is SW, M
In order for W to be the same, the control circuit (8) does not need to control the reference oscillator. In addition, the time constant of the LPF (7) at this time is an optimum value for both SW and MW.

Although the pitch of the variable frequency division ratio in the above-described embodiment is 1/2, by changing this to 1 / A (A is a positive integer), the time constant of the LPF (7) is changed. It is possible to output a local oscillation frequency having a frequency ratio such as 1: A or 2: A without performing.

As an example of a variable frequency dividing device (4) for performing variable frequency division at a pitch of a frequency dividing ratio of 1/2, Japanese Patent Application No. Hei 8-1 of the same applicant
No. 644. In this method, B / C (B and C are positive integers) frequency division is performed using a variable frequency divider having a frequency division ratio of N + 1/2, and a detailed description thereof will be omitted.

[0022]

According to the above configuration, the time constant of the LPF can be shared with the frequency output from the PLL circuit.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a main part of an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a main part of the variable frequency dividing device of FIG. 1;

FIG. 3 is an explanatory diagram of an operation of N + 1/2 frequency division of the variable frequency divider of FIG. 2;

FIG. 4 is an explanatory diagram of an operation of dividing the frequency of N by the variable frequency dividing device of FIG. 2;

FIG. 5 is a block diagram showing a main part of a conventional PLL circuit.

[Explanation of symbols]

 Reference Signs List 1 voltage controlled oscillator for SW (VCO for SW) 2 voltage controlled oscillator for MW (VCO for MW) 3 switch 4 variable frequency divider 5 reference oscillator 6 phase comparator 7 low frequency filter (LPF) 71 time constant circuit 8 control circuit

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H03L ⁷ /06-7/23 H04B 1/26

Claims (1)

(57) [Claims] 1. A voltage-controlled oscillator for radio-band SW and a voltage-controlled oscillator for MW, a switch for selecting the voltage-controlled oscillator for SW and the voltage-controlled oscillator for MW, and a voltage-controlled oscillator for SW or for the MW A variable frequency dividing device capable of variably dividing the output of the voltage controlled oscillator by a dividing ratio of 1/2, and selectively selecting a SW reference signal or a MW reference signal having the same or similar frequency as the SW reference signal; A reference oscillator to be output; a phase comparator for comparing a reference signal of the reference oscillator with an output of the variable frequency divider; and an output of the phase comparator with a time constant shared by the SW reference signal and the MW reference signal. A low-frequency filter that converts the voltage into a control voltage and outputs the voltage to the voltage-controlled oscillator; and a MW reference signal output from the reference signal oscillator, and the variable frequency divider divides the frequency by the frequency division ratio of step 1. A PLL circuit comprising: a control unit having an MW mode and a SW mode for outputting a SW reference signal from the reference oscillator and dividing the variable frequency dividing device at a dividing ratio of 1/2 step.