JPS6327475Y2 - - Google Patents

Description

[Detailed description of the invention] The present invention relates to a semiconductor device, and particularly to a circuit that is asynchronous with respect to the reference frequency (r) of a phase detector of a phase lock loop circuit (hereinafter referred to as a PLL circuit). This invention relates to integrated circuits constructed on the same silicon substrate.

Conventionally, when a circuit asynchronous to the reference frequency r of a phase detector, which is one of the PLL circuit components, is realized as an integrated circuit on the same silicon substrate,
The signal-to-noise ratio (C/N ratio) of a voltage-controlled oscillator (hereinafter abbreviated as VCO) with a PLL circuit configuration had become extremely poor. First, I will explain the mechanism.
When considering the C/N ratio of the VCO in the PLL circuit configuration,
It is necessary to view PLL circuits in an analog sense. In this case, C of the C/N ratio is the center frequency component of the VCO, and N is the noise component included in this center frequency. This noise consists of the reference frequency component fr of the phase detector and its harmonic components, as well as low frequency beat components and low frequency components coming from other sources. The low frequency beat component is a difference component between the reference frequency component fr and a frequency asynchronous to this reference frequency from another circuit close to this reference frequency r. Here, the reference frequency component and its harmonic components can be removed by a low-pass filter circuit, so there is no particular problem. The problem here is the low frequency beat component and the low frequency components that independently come from other circuits. These two components come from other circuits,
This has been passed around to this PLL circuit.

By preventing this component from entering the PLL circuit, a VCO with a good C/N ratio can be realized. Now, it has been found that the main route to the PLL circuit is the power supply wiring (voltage application wiring and ground wiring). Figure 1 shows an equivalent circuit of the basic configuration of a PLL circuit in which wraparound occurs.

This circuit includes a programmable divider circuit 3, a phase detector 4 to which a reference frequency r is input, further a charge pump circuit 5, a low-pass filter circuit 6, and a voltage controlled oscillator 7. Here, there is a voltage application wiring 1 made of aluminum and a ground wiring 2 made of aluminum. The aluminum wiring 1 and 2 for normal voltage application and grounding are 15μ wide.
Use one with a thickness of 1μ and specific resistance ρ = 2.69μΩ・cm. When the length of the wiring 2 is 5 mm, its resistance value R is approximately 9Ω. In the case where the ground wiring 2 of the asynchronous frequency circuit (not shown) is not separated but is the same wiring, when the asynchronous frequency current component (IN) 8 flows at 10 mA, this ground wiring 2
A voltage with an asynchronous frequency component of 90 mV is generated. When the voltage flows around from the voltage application wiring 1 and ground wiring 2 of the low-pass filter circuit 6 of the PLL circuit, the low-pass filter output voltage 6' changes. This output voltage 6' causes the VCO 7 to undergo frequency modulation.

Figure 2 shows the spectrum analyzer observed waveform of the VCO output in this case. In this case, the frequency of the asynchronous frequency component applied from the outside to the inverter circuit, which is on the same silicon substrate as this PLL circuit, is 125 Hz. This figure shows that components (sidebands) that are integral multiples of the modulation frequency of 125 Hz are generated on both sides of the modulated frequency (o). This spectrum analyzer waveform is
7 is subjected to frequency modulation.

FIG. 3 shows spectrum analyzer observed waveforms when the reference frequency 4 of the phase detector is 10 kHz and the externally applied asynchronous frequency is 10.040 kHz in the same manner as above. In this figure, a beat frequency component (40Hz) of the difference between the reference frequency r and the non-periodic frequency is generated,
This component indicates that frequency modulation is applied to the VCO 7.

FIG. 4 shows waveforms observed by a spectrum analyzer in the same integrated circuit as in FIGS. 2 and 3, but without applying an external asynchronous frequency component. This figure shows that the C/N ratio in this case is good.
Here, we have explained the case where the signal comes from the ground wiring of the low-pass filter circuit 6, but the PLL
In the same way, it is also possible to run around from the ground wiring of the individual circuits forming the circuit. In FIG. 1, in addition to the low-pass filter circuit, the programmable divider circuit 3, the phase detector 4, the VCO 7 from the ground wiring 2, etc. can also be considered.

An object of the present invention is to eliminate the causes of C/N deterioration as described above, and to provide a semiconductor device having a PLL structure with a good C/N ratio.

The present invention is characterized in that the power supply wiring of the phase lock loop circuit and the power supply wiring of other circuits that are not synchronized with the reference frequency of the circuit are connected via pads on the semiconductor substrate. It is a semiconductor device. In particular, it is desirable for the power supply wiring to have a structure in which both the voltage application wiring and the ground wiring are connected via pads.

Next, an embodiment of the present invention will be described in detail with reference to FIG. Particularly different from the conventional one is that the power supply wiring for the circuit 12 that is not synchronized with the reference frequency and the power supply wiring for the circuits that constitute the phase lock loop circuit, that is, the programmable divider circuit 3, the phase detector 4, etc., are different from the pad 10, 11. In this embodiment, the asynchronous frequency current component generated in the asynchronous circuit 12 does not pass through the voltage application wiring 1 and the grounding wiring 2, so the signal from this asynchronous circuit 12 does not go around directly, and therefore the above-mentioned Even if a 90 mV asynchronous frequency component voltage occurs in the asynchronous circuit 12, the PLL
Since it is independent from the circuit, this asynchronous frequency component does not affect the PLL circuit. In addition,
This asynchronous frequency current component is once applied to the pads 10 and 11 on the semiconductor substrate, but since the potential here is kept substantially constant, the voltage has no influence via these pads 10 and 11. There's nothing to give. By providing these pads 10 and 11, voltage application wiring 1 and grounding wiring 2
Furthermore, there is no need to worry about the signal from the asynchronous circuit 12 going around. As mentioned above, the problem with the deterioration of the C/N ratio is that
The asynchronous component with the reference frequency r of the phase detector 4 is
The problem is that the voltage goes around the PLL circuit that makes up the local oscillator through the voltage application wiring and ground wiring.

In this invention, in particular, the power supply wiring 2 of the PLL circuit configured on the same silicon substrate and the power supply wiring of the reference frequency r of the phase detector 4 and the asynchronous circuit are separated, thereby achieving a good C/N ratio. This makes it possible to create a local oscillator.

In the description of the above embodiments, the ground wiring is provided as a separate wiring, but it is even more effective to take similar consideration to the voltage application wiring.

[Brief explanation of the drawing]

FIG. 1 is an equivalent circuit block diagram for explaining the path through which frequency components asynchronous with the reference frequency of the phase detector enter the PLL circuit. Second
The figure shows the conventional case when the reference frequency of the phase detector and the asynchronous component frequency of 125 Hz are applied externally.
FIG. 2 is a frequency spectrum diagram showing a spectrum analyzer observed waveform of a VCO. Figure 3 shows the reference frequency of the phase detector.
Assuming that the externally applied asynchronous frequency is 10kHz,
It is a frequency spectrum diagram showing the spectrum analyzer observed waveform of a conventional VCO when the frequency is 10.040kHz. Fourth
This figure is a frequency spectrum diagram showing a conventional VCO observed waveform when no external asynchronous frequency component is applied in the same integrated circuit as in FIGS. 2 and 3. Figure 5 shows the phases of the embodiment of the present invention.
1 is a circuit block diagram showing a lock loop circuit, etc.; FIG. In the figure, 1...voltage application wiring, 2...
Ground wiring, 3... Programmable divider circuit, 4... Phase detector, 5... Charge pump circuit, 6... Low pass filter circuit, 6'... Low pass filter output voltage, 7... Voltage controlled oscillator, 8 ...Asynchronous current component, 10...Power supply part (VDD) of the pad (PAD) of the integrated circuit (IC) board, 11...Ground part (GND) of the pad of the IC board, 12...Synchronized with the reference frequency No circuit.

Claims (1)

[Scope of utility model registration request] In a semiconductor device in which a phase-lock loop circuit and an asynchronous circuit that is not synchronized with the reference frequency of a phase detector of the circuit are incorporated on the same semiconductor substrate, the power supply wiring of the asynchronous circuit and the phase-lock loop circuit are connected to each other. A semiconductor device characterized in that it is connected to a power supply wiring via a pad on the semiconductor substrate.