JPS6239819B2 - - Google Patents
Info
- Publication number
- JPS6239819B2 JPS6239819B2 JP55173590A JP17359080A JPS6239819B2 JP S6239819 B2 JPS6239819 B2 JP S6239819B2 JP 55173590 A JP55173590 A JP 55173590A JP 17359080 A JP17359080 A JP 17359080A JP S6239819 B2 JPS6239819 B2 JP S6239819B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- sio
- poly
- photoresist
- present
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 14
- 239000000758 substrate Substances 0.000 claims description 10
- 238000000034 method Methods 0.000 claims description 8
- 238000000151 deposition Methods 0.000 claims description 3
- 238000004380 ashing Methods 0.000 claims description 2
- 239000000463 material Substances 0.000 claims description 2
- 229920000642 polymer Polymers 0.000 claims description 2
- 238000007740 vapor deposition Methods 0.000 claims description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 30
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 24
- 229920002120 photoresistant polymer Polymers 0.000 description 18
- 230000015654 memory Effects 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 229910052681 coesite Inorganic materials 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000002861 polymer material Substances 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000000927 vapour-phase epitaxy Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
Description
【発明の詳細な説明】
本発明は半導体層の側面に選択的に絶縁体層を
被着形成する方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for selectively depositing an insulating layer on the side surfaces of a semiconductor layer.
はじめに本発明が半導体装置の製造に於て効果
を有する所以を実際のデバイスに即して説明す
る。 First, the reason why the present invention is effective in manufacturing semiconductor devices will be explained based on an actual device.
第１図は集積型の１トランジスタMOSメモリ
であるが、蓄積電極１０１とゲート電極１０２が
共に多結晶シリコン（以下ポリSiと略記）で形成
されるところから、通常「２層ポリSi型」と呼ば
れているものである。 Figure 1 shows an integrated one-transistor MOS memory, but since both the storage electrode 101 and the gate electrode 102 are made of polycrystalline silicon (hereinafter abbreviated as poly-Si), it is usually called a "two-layer poly-Si type". It is what is called.
此のMOSメモリの製造に於ては、まずポリSi
層１０１が形成された後、ゲート絶縁膜が熱酸化
によつて形成され、次いでポリSi層１０２が形成
されるのであるが、熱酸化の際ポリSi層１０１の
表面も酸化されてSiO2層１０３が形成される。
このSiO2層１０３がポリSi層１０１とポリSi層１
０２の間の絶縁膜となるのであるが、上述のよう
にゲート絶縁膜１０４（通常400nm程度の厚さ）
と同時に形成されるので、ポリSi層の酸化速度は
単結晶Siのそれより大ではあるが、その厚さは
600nm程度に限られる。なお、図に於て１０５は
キヤパシタの誘電層であるSiO2，１０６はフイ
ールド酸化膜、１０７はｐ型シリコン（Si）基板
である。 In manufacturing this MOS memory, we first use poly-Si.
After the layer 101 is formed, a gate insulating film is formed by thermal oxidation, and then a poly-Si layer 102 is formed. During the thermal oxidation, the surface of the poly-Si layer 101 is also oxidized and an SiO 2 layer is formed. 103 is formed.
This SiO 2 layer 103 is a poly-Si layer 101 and a poly-Si layer 1
02, and as mentioned above, the gate insulating film 104 (usually about 400 nm thick)
Although the oxidation rate of the poly-Si layer is higher than that of single-crystal Si because it is formed at the same time, its thickness is
Limited to around 600nm. In the figure, 105 is a SiO 2 dielectric layer of the capacitor, 106 is a field oxide film, and 107 is a p-type silicon (Si) substrate.
絶縁膜がこの程度の厚さであると、図のＡの部
分のように形状が急に変化している部分では絶縁
不良が生じやすい。ポリSi層１０１の上面のSiO2
層１０３を厚くすることは、予めSiO2層を形成
しておく等の方法によつて容易に実現し得るが、
側面部は、ポリSi層１０１のパターニングによつ
て始めて露出されるので、ゲート酸化膜形成前に
（或は形成後に）その部分にのみ絶縁膜を形成す
ることは困難であつた。 When the insulating film has such a thickness, insulation failure is likely to occur in a portion where the shape changes suddenly, such as the portion A in the figure. SiO 2 on the top surface of poly-Si layer 101
Increasing the thickness of the layer 103 can be easily achieved by forming a SiO 2 layer in advance, etc.
Since the side surface portion is exposed only by patterning the poly-Si layer 101, it is difficult to form an insulating film only on that portion before (or after) forming the gate oxide film.
本発明はこのような場合にも半導体層の側面の
みに選択的に且容易に絶縁皮膜を形成する方法を
提供するものであつて、側面の露出した半導体領
域を表面に有する半導体基板に、その平面部分に
は比較的厚く、側面部分には比較的薄く高分子材
料を塗布した後、該高分子層の一部を灰化処理し
て前記半導体領域側面を再び露出し、プラズマ気
相成長法によつて該半導体領域側面に絶縁体層を
被着することを特徴としている。 The present invention provides a method for selectively and easily forming an insulating film only on the side surfaces of a semiconductor layer in such a case, and the present invention provides a method for forming an insulating film selectively and easily only on the side surfaces of a semiconductor layer. After applying a polymer material relatively thickly to the plane portion and relatively thinly to the side portions, a portion of the polymer layer is ashed to expose the side surfaces of the semiconductor region again, and then plasma vapor phase epitaxy is performed. The method is characterized in that an insulating layer is deposited on the side surface of the semiconductor region.
第２図は本発明の一実施例を順次説明するもの
である。同図ａに於て、Si基板１上にSiO2層２を
介してポリSi層３が存在し、その側面３′には
SiO2層は被着していない。これはポリSi層３をパ
ターニングした結果生ずる状態に対応するもので
ある。なお、SiO2層２或は２′の存在の有無は本
発明の実施に直接関係するものではなく、単に第
１図に対応させる為に、それが存在する場合を示
しているだけである。 FIG. 2 sequentially explains one embodiment of the present invention. In figure a, a poly-Si layer 3 exists on a Si substrate 1 with a SiO 2 layer 2 interposed therebetween, and its side surface 3' is
No SiO2 layer is deposited. This corresponds to the state that occurs as a result of patterning the poly-Si layer 3. The presence or absence of the SiO 2 layer 2 or 2' is not directly related to the implementation of the present invention, and is merely shown to correspond to FIG. 1.
この状態の基板上に粘性を通常より高く調整し
たフオトレジストをスピンコートで約500nmの厚
さに塗布する。ポリSi層３による段差は650nm程
度なのでフオトレジスト層４は、段差部では薄い
層でつながるようになる。フオトレジストの粘性
が低いと、この部分も厚くつながるので本発明の
実施に不都合である。フオトレジストは粘性が高
いほど薄く塗布するのが困難になるが、本発明を
実施する為には段差よりも薄く塗布できる範囲内
で、できるだけ高粘性に調整すべきである。 On the substrate in this state, a photoresist whose viscosity has been adjusted to be higher than usual is applied by spin coating to a thickness of approximately 500 nm. Since the step difference due to the poly-Si layer 3 is about 650 nm, the photoresist layer 4 becomes connected with a thin layer at the step portion. If the viscosity of the photoresist is low, this portion will also be thick and connected, which is inconvenient for implementing the present invention. The higher the viscosity of a photoresist, the more difficult it is to apply it thinly, but in order to carry out the present invention, the viscosity should be adjusted to be as high as possible within a range that allows the photoresist to be applied thinner than the difference in level.
次にこのレジスト層４の表面をプラズマアツシ
ヤーで灰化すると、この灰化処理はほぼ等方的に
進行するので第２図ｂに示す如く、ポリSi層３の
側面部分のフオトレジストは除去されて空隙５が
生ずる一方、平坦部に塗布されたフオトレジスト
はその厚みを減ずるのみで、なお基板表面を覆つ
ている。 Next, the surface of this resist layer 4 is ashed using a plasma assher. Since this ashing process proceeds almost isotropically, the photoresist on the side surfaces of the poly-Si layer 3 is removed, as shown in FIG. On the other hand, the photoresist applied to the flat area only reduces its thickness and still covers the substrate surface.
このフオトレジストを残した状態のまま次にプ
ラズマ気相成長法（以下プラズマCVD法と記
す）によつてSiO2層を被着すると第２図ｃのよ
うにポリSi層端面にSiO2層が被着形成される。フ
オトレジスト上にもSiO2層は堆積するがこれは
後にフオトレジストと共に除去されるものであ
り、図面には描かれていない。 Next, with this photoresist left in place, a SiO 2 layer is deposited by plasma vapor deposition (hereinafter referred to as plasma CVD), and as shown in Figure 2c, a SiO 2 layer is formed on the end face of the poly-Si layer. Adhesion is formed. A SiO 2 layer is also deposited on the photoresist, but this is later removed together with the photoresist and is not depicted in the drawing.
プラズマCVD法によるSiO2の堆積は、原料ガ
スとして通常SiH4＋N2Oが用いられ、減圧状態で
プラズマ化されて100℃程度の低温で反応が進行
するのでフオトレジストの分解は起らない。また
SiO2層の厚みを任意に制御することができる。 In the deposition of SiO 2 by the plasma CVD method, SiH 4 +N 2 O is usually used as a raw material gas, which is turned into plasma under reduced pressure and the reaction proceeds at a low temperature of about 100° C., so that the photoresist does not decompose. Also
The thickness of the SiO2 layer can be controlled arbitrarily.
最後にフオトレジストを、その上に堆積した
SiO2と共に除去し、600〜800℃、30〜40min程度
の熱処理によつて堆積したSiO2層を緻密なもの
に変えればポリSi層３の側面に絶縁性の良好な
SiO2層が形成されたことになる。 Finally, photoresist was deposited on top of it.
If the deposited SiO 2 layer is removed together with SiO 2 and heat treated at 600 to 800°C for 30 to 40 minutes, the deposited SiO 2 layer can be made dense, creating a layer with good insulation on the sides of the poly-Si layer 3.
This means that two SiO layers have been formed.
以上はポリSi層の側面にSiO2層を形成する場合
であるが、単結晶Siに対しても同様にその側面に
絶縁皮膜を形成することができる。次にそのよう
な処理の必要な場合の一例をあげる。 The above is a case where an SiO 2 layer is formed on the side surface of a poly-Si layer, but an insulating film can be similarly formed on the side surface of single-crystal Si. Next, we will give an example of a case where such processing is necessary.
第３図ａは先に本発明者の一人によつて発明さ
れ、本出願人によつて出願された１トランジスタ
型MOSメモリの構造を示すものである。該先願
発明（特願昭54−109640）の特徴や動作は本発明
に直接関係するものではないが、図中の各部位の
名称或いは機能を簡単に述べると、300はp-型Si
基板、３０１，３０１′はフイールド酸化膜であ
り、また３０２及び３０３はn+型ポリSiで夫々
MOSトランジスタのソース及びドレイン領域を
構成する。３０４はｐ型エピタキシヤル成長領域
でMOSトランジスタのバツクゲート領域、３０
５はMOSトランジスタのゲート絶縁膜である。
また３０６はMOSトランジスタのゲート電極で
ワード線を兼ねる導体層、３０７はMOSトラン
ジスタのドレインに接続されるビツト線、３０８
はp+領域で、薄い酸化膜３０９をはさんでポリ
Si層３０２′と共に電荷を蓄積する領域を構成す
る。３１１はp+チヤネルストツパであり、３１
２はPSG層である。 FIG. 3a shows the structure of a one-transistor type MOS memory previously invented by one of the inventors of the present invention and filed by the applicant of the present invention. Although the features and operations of the prior invention (Japanese Patent Application No. 109640/1984) are not directly related to the present invention, to briefly describe the names or functions of each part in the figure, 300 is a p - type Si
The substrates 301 and 301' are field oxide films, and 302 and 303 are n + type poly-Si, respectively.
Configures the source and drain regions of the MOS transistor. 304 is a p-type epitaxial growth region, which is a back gate region of a MOS transistor;
5 is a gate insulating film of a MOS transistor.
Further, 306 is a conductor layer which is the gate electrode of the MOS transistor and also serves as a word line, 307 is a bit line connected to the drain of the MOS transistor, and 308 is a conductor layer which also serves as a word line.
is the p + region, with a thin oxide film 309 in between.
Together with the Si layer 302', it constitutes a region for accumulating charges. 311 is p + channel stopper and 31
2 is the PSG layer.
図中の厚いSiO2層３０１′は、n+型のソース領
域３０２と、p+領域３０８とが直接突合されて
低耐圧のＰ／Ｎ接合を形成するのを避ける為分離
領域として設けられているものであつて、高集積
化の為にはこれを無くす事が望まれる。 The thick SiO 2 layer 301' in the figure is provided as a separation region to prevent the n + type source region 302 and the p + region 308 from directly butting together and forming a low breakdown voltage P/N junction. However, it is desirable to eliminate this in order to achieve higher integration.
そこで第３図ｂのような構成にすることが考え
られるが、従来は図のＢの部分の構造を、即ち
p+領域３０８の側面をSiO2層３１０で覆つてn+
ポリSi層３０２と直接接することのないようにし
た構造を、十分な耐圧を持たせて実現することが
難かしかつた。此の図面の装置はＢの部分以外は
ａ図のものと構成、機能は全く同じなので煩雑さ
を避ける為各部の説明は省略するが、Ｂの部分は
薄い酸化膜３０９に連続してSi基板３００の表面
に形成されたステツプ部の側面にやや厚い酸化膜
３１０が、薄い酸化膜３０９に連続して形成され
ているものである。 Therefore, it is conceivable to create a structure as shown in Figure 3b, but conventionally the structure of part B in the figure is changed to
The sides of the p + region 308 are covered with a SiO 2 layer 310 to form an n +
It has been difficult to realize a structure that does not come into direct contact with the poly-Si layer 302 and has sufficient breakdown voltage. The device in this drawing has exactly the same structure and function as the one in FIG. A slightly thick oxide film 310 is formed on the side surface of the step portion formed on the surface of the oxide film 300, which is continuous with a thin oxide film 309.
本発明によればこのような位置、即ち単結晶半
導体表面に存在するステツプ部の側面に選択的に
十分な絶縁耐圧を有する絶縁皮膜を形成すること
ができ、従つて第３図ｂのような構造のメモリ素
子を形成することが可能となる。 According to the present invention, it is possible to selectively form an insulating film having a sufficient dielectric strength voltage on such a position, that is, on the side surface of the step portion existing on the surface of the single crystal semiconductor, and therefore, as shown in FIG. It becomes possible to form a memory element with a structure.
第４図ａ〜ｄにこのような場合の本発明の実施
例が示されているが、本質的には第２図における
工程と同じなので簡単に説明する。 An embodiment of the present invention in such a case is shown in FIGS. 4a to 4d, and since the steps are essentially the same as those shown in FIG. 2, a brief explanation will be provided.
まず、第４図ａに示されているように、ステツ
プ部のある半導体基板１の表面に、フオトレジス
ト層４を塗布形成する。この場合、第２図に於け
ると同様、高粘性のフオトレジストが使用され
る。第３図ｂに対応させて見た場合、このステツ
プは基板をエツチングして形成したものでＢの部
分のステツプに対応し、SiO2層２は電荷蓄積用
キヤパシタの誘電体膜３０７に相当することにな
る。 First, as shown in FIG. 4a, a photoresist layer 4 is coated on the surface of the semiconductor substrate 1 where the step portion is located. In this case, as in FIG. 2, a highly viscous photoresist is used. When viewed in conjunction with FIG. 3b, this step is formed by etching the substrate and corresponds to the step in part B, and the SiO 2 layer 2 corresponds to the dielectric film 307 of the charge storage capacitor. It turns out.
次いでフオトレジスト層を軽く灰化処理して不
連続部５を生ぜしめ（第４図ｂ）、プラズマCVD
法によつてSiO2６を形成する（第４図ｃ）。フオ
トレジスト層と共にその上に堆積したSiO2（図
示せず）を除去し、熱処理によつてSiO2６を緻
密化すれば第４図ｄに示すようにステツプ側面に
厚いSiO2膜６′を持つ構造が実現する。 Next, the photoresist layer is lightly ashed to produce discontinuous portions 5 (Fig. 4b), and then subjected to plasma CVD.
SiO 2 6 is formed by a method (FIG. 4c). If the SiO 2 (not shown) deposited on the photoresist layer is removed and the SiO 2 6 is densified by heat treatment, a thick SiO 2 film 6' can be formed on the side surface of the step as shown in FIG. 4d. The structure you have is realized.
以上の説明はシリコン層の側面にSiO2膜を形
成する場合を例にあげて行なつたが、被覆される
ものがシリコンに限るものでないこと及び被覆す
る絶縁材料がSiO2に限るものでないことはもち
ろんである。 The above explanation has been given using the case where a SiO 2 film is formed on the side surface of a silicon layer as an example, but it should be noted that the material to be coated is not limited to silicon, and the insulating material to be coated is not limited to SiO 2 . Of course.
以上述べたように、本発明は本質的には半導体
層の側面と絶縁皮膜を形成する方法であるが、半
導体装置の製造、特に１トランジスタ型MOSメ
モリの製造に有用なものである。 As described above, the present invention is essentially a method for forming an insulating film on the side surface of a semiconductor layer, but it is useful for manufacturing semiconductor devices, particularly for manufacturing one-transistor type MOS memories.
第１図及び第３図は本発明が利用されるデバイ
スの構造を示す図、第２図及び第４図は本発明の
実施例を説明する図であつて１はSi基板、２，
２′はSiO2、３はポリSi層、３′はポリSi層の端
面、４はフオトレジスト、５はフオトレジストの
不連続部、６，６′はプラズマCVD法で形成した
SiO2、１０１，１０２はポリSi層、１０３，１０
４，１０５はSiO2皮膜、１０６はフイールド
SiO2層、３００はSi基板、３０１，３０１′は厚
いSiO2層、３０２，３０２′，３０３はn+ポリSi
層、３０４はｐ型エピタキシヤル層、３０５はゲ
ート酸化膜、３０６はゲート電極兼ワード線、３
０７はビツト線、３０８はp+領域、３０９，３
１０はSiO2層、３１１はチヤネルストツパ、３
１２はPSG層である。
1 and 3 are diagrams showing the structure of a device to which the present invention is applied, and FIGS. 2 and 4 are diagrams illustrating an embodiment of the present invention, in which 1 is a Si substrate, 2 is a
2' is SiO 2 , 3 is a poly-Si layer, 3' is the end face of the poly-Si layer, 4 is a photoresist, 5 is a discontinuous part of the photoresist, 6 and 6' are formed by plasma CVD method
SiO 2 , 101, 102 are poly-Si layers, 103, 10
4,105 is SiO 2 film, 106 is field
SiO 2 layer, 300 is Si substrate, 301, 301' is thick SiO 2 layer, 302, 302', 303 is n + poly-Si
304 is a p-type epitaxial layer, 305 is a gate oxide film, 306 is a gate electrode/word line, 3
07 is the bit line, 308 is the p + region, 309,3
10 is a SiO 2 layer, 311 is a channel stopper, 3
12 is a PSG layer.
Claims (1)
導体基板に、その平面部分には比較的厚く、側面
部分には比較的薄く高分子材料を塗布した後、該
高分子層の一部を灰化処理して前記半導体領域側
面を再び露出し、プラズマ気相成長法によつて該
半導体領域側面に絶縁体層を被着することを特長
とする絶縁皮膜の形成法。1. After applying a polymeric material relatively thickly on the flat surface and relatively thinly on the side surface of a semiconductor substrate having a semiconductor region with exposed side surfaces on the surface, a part of the polymer layer is subjected to ashing treatment. A method for forming an insulating film, comprising: exposing the side surface of the semiconductor region again, and depositing an insulating layer on the side surface of the semiconductor region by plasma vapor deposition.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55173590A JPS5796537A (en) | 1980-12-09 | 1980-12-09 | Forming method for insulating film |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55173590A JPS5796537A (en) | 1980-12-09 | 1980-12-09 | Forming method for insulating film |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5796537A JPS5796537A (en) | 1982-06-15 |
| JPS6239819B2 true JPS6239819B2 (en) | 1987-08-25 |
Family
ID=15963401
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP55173590A Granted JPS5796537A (en) | 1980-12-09 | 1980-12-09 | Forming method for insulating film |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5796537A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR870000750A (en) * | 1985-06-14 | 1987-02-20 | 이마드 마하윌리 | How to chemically vapor coat a silicon dioxide film |
-
1980
- 1980-12-09 JP JP55173590A patent/JPS5796537A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5796537A (en) | 1982-06-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP3415496B2 (en) | Semiconductor device and manufacturing method thereof | |
| JP3565993B2 (en) | Method for manufacturing semiconductor device | |
| JP2623659B2 (en) | Method for manufacturing MIS transistor | |
| JPS6239819B2 (en) | ||
| JPH11186525A (en) | Semiconductor device including capacitor and its manufacture | |
| US5723371A (en) | Method for fabricating a thin film transistor having a taper-etched semiconductor film | |
| JP2503621B2 (en) | Method for manufacturing semiconductor device | |
| JPS5816341B2 (en) | Manufacturing method of semiconductor device | |
| JPH07109858B2 (en) | Method for manufacturing semiconductor device | |
| JPH07122737A (en) | Semiconductor device and its manufacture | |
| JPS62172732A (en) | Manufacture of semiconductor device | |
| KR0154765B1 (en) | Thin film transistor | |
| JPS5984570A (en) | Manufacture of capacitor for semiconductor device | |
| KR950007958B1 (en) | Fabricating method of semiconductor device | |
| JPH09213942A (en) | Semiconductor device and manufacture thereof | |
| KR100486610B1 (en) | Method for manufacturing capacitor of semiconductor device | |
| JP3264402B2 (en) | Semiconductor device | |
| JPH0419707B2 (en) | ||
| JPH11145425A (en) | Manufacture of semiconductor element and semiconductor device | |
| JP2945023B2 (en) | Method for manufacturing thin film transistor | |
| JPH03233938A (en) | Manufacture of thin-film transistor | |
| JPH04318938A (en) | Manufacture of semiconductor device | |
| JPH05198744A (en) | Manufacture of semiconductor device | |
| JPS5994437A (en) | Semiconductor device | |
| JPH0578193B2 (en) |