KR0154765B1 - Thin film transistor - Google Patents
Thin film transistorInfo
- Publication number
- KR0154765B1 KR0154765B1 KR1019940035626A KR19940035626A KR0154765B1 KR 0154765 B1 KR0154765 B1 KR 0154765B1 KR 1019940035626 A KR1019940035626 A KR 1019940035626A KR 19940035626 A KR19940035626 A KR 19940035626A KR 0154765 B1 KR0154765 B1 KR 0154765B1
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- Prior art keywords
- oxide film
- gate insulating
- chemical vapor
- thermal oxide
- vapor deposition
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- 239000010409 thin film Substances 0.000 title description 3
- 238000000034 method Methods 0.000 claims abstract description 29
- 238000005229 chemical vapour deposition Methods 0.000 claims abstract description 26
- 238000000151 deposition Methods 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims description 11
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 10
- 239000010453 quartz Substances 0.000 claims description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 7
- 238000010438 heat treatment Methods 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 abstract description 10
- 238000007254 oxidation reaction Methods 0.000 abstract description 10
- 230000008021 deposition Effects 0.000 abstract description 6
- 238000000280 densification Methods 0.000 abstract description 4
- 230000000694 effects Effects 0.000 abstract description 4
- 238000006356 dehydrogenation reaction Methods 0.000 abstract description 3
- 230000001590 oxidative effect Effects 0.000 abstract description 3
- 239000000126 substance Substances 0.000 abstract 1
- 239000012808 vapor phase Substances 0.000 abstract 1
- 239000010408 film Substances 0.000 description 80
- 230000015572 biosynthetic process Effects 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 5
- 239000004973 liquid crystal related substance Substances 0.000 description 4
- 238000002474 experimental method Methods 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000006911 nucleation Effects 0.000 description 2
- 238000010899 nucleation Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 235000014653 Carica parviflora Nutrition 0.000 description 1
- 241000243321 Cnidaria Species 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 239000012861 aquazol Substances 0.000 description 1
- 229920006187 aquazol Polymers 0.000 description 1
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000007429 general method Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000005527 interface trap Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02269—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by thermal evaporation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78672—Polycrystalline or microcrystalline silicon transistor
- H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Crystallography & Structural Chemistry (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Formation Of Insulating Films (AREA)
- Thin Film Transistor (AREA)
Abstract
이 발명은 에지 시닝 형상을 없앤 이중게이트 절연막 및 그 형성방법에 관한 것으로, 저온 화학기상증착 산화막을 증착후 열산화함으로써, 에지 시닝 현상을 완전히 해결하고, 홈을 줄이며, 후기열산화 공정시 화학기상증착 산화막 덴시피케이션(Densification) 및 디하이드로제네이션(Dehydrogenation) 효과가 있어 전기적 특성 및 절연 특성에서도 열산화막도 동일한 결과를 얻을 수 있는 에지 시닝 형상을 없앤 이중게이트 절연막 및 그 형성방법에 관한 것이다.The present invention relates to a double gate insulating film and a method of forming the same without the edge thinning shape, by thermally oxidizing the low temperature chemical vapor deposition oxide film after deposition, to completely solve the edge thinning phenomenon, reduce the grooves, the chemical vapor phase during the post-thermal oxidation process The present invention relates to a double-gate insulating film having an edge thinning shape that has a deposition oxide film densification and dehydrogenation effect, and thus thermal oxide film can have the same result in electrical and insulating properties, and a method of forming the same.
Description
제1도는 종래는 게이트 절연막의 단면도.1 is a cross-sectional view of a conventional gate insulating film.
제2도는 종래의 열산화후 화학 기상증착법으로 산화막을 증착하는 방법으로 형성된 게이트 절연막의 단면도.2 is a cross-sectional view of a gate insulating film formed by a method of depositing an oxide film by a conventional chemical vapor deposition method after thermal oxidation.
제3도는 종래의 게이트 절연막의 형성과정중에 홈이 생기는 과정을 도시한 단면도.3 is a cross-sectional view showing a process of forming a groove during a process of forming a conventional gate insulating film.
제4도는 이 발명의 실시예에 따른 에지 시닝 형상을 없앤 이중게이트 절연막의 형성전에 저온 산화막을 증착시킨 단면도.4 is a cross-sectional view of depositing a low temperature oxide film before formation of the double gate insulating film without the edge thinning shape according to the embodiment of the present invention.
제5도는 이 발명의 실시예에 따른 에지 시닝 형상을 없앤 이중게이트 절연막의 단면도.5 is a cross-sectional view of the double gate insulating film without the edge thinning shape according to the embodiment of the present invention.
제6도는 이 발명의 실시예에 따른 에지 시닝 형상을 없앤 이중게이트 절연막의 형성과정중에 홈이 줄어드는 과정을 도시한 단면도.6 is a cross-sectional view illustrating a process of reducing grooves during formation of a double gate insulating film without edge thinning according to an embodiment of the present invention.
제7도는 이 발명의 실시예에 따른 에지 시닝 형상을 없앤 이중게이트 절연막을 일정조건으로 실험한 결과표.FIG. 7 is a table showing results of experimenting with a double gate insulating film without edge edge thinning according to an embodiment of the present invention.
제8도는 이 발명의 실시예를 따른 에지 시닝 형상을 없앤 이중게이트 절연막의 실험을 위한 회로도.8 is a circuit diagram for an experiment of a double gate insulating film without the edge thinning shape according to the embodiment of the present invention.
제9도는 제8도의 회로에 대하여 일정조건으로 실험한 결과표이다.9 is a result table of the circuit of FIG. 8 under certain conditions.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 기판 2 : 액티브 패턴1 substrate 2 active pattern
3 : 화학기상증착 산화막 4 : 열산화막3: chemical vapor deposition oxide film 4: thermal oxide film
이 발명은 에지 시닝 형상을 없앤 이중게이트 절연막 및 그 형성방법에 관한 것으로 더욱 상세하게 말하자면, 박막트랜지스터(TFT) 제조과정에서 게이트 절연막을 형성할 때 저온 화학적 기상증착법(CVD)으로 산화막을 증착한 후 열산화함으로써 게이트 절연막의 가장자리에서 그 두께가 얇아지는 에지 시닝(Edge-Thinning)현상을 없앤 이중게이트 절연막 및 그 형성방법에 관한 것이다.The present invention relates to a double-gate insulating film having an edge thinning shape and a method of forming the same. More specifically, the oxide film is deposited by low temperature chemical vapor deposition (CVD) when the gate insulating film is formed in the TFT manufacturing process. The present invention relates to a double-gate insulating film and a method of forming the same, which eliminate edge edge-thinning that is thinned at the edge of the gate insulating film by thermal oxidation.
화상정보시대에 있어서, 정보전달의 최대 담당자인 표시장치에 많은 기대가 모아지고 있으며 이로 인해 지금까지의 음극선관(CRT)을 대신한 각종 평면표시장치가 개발되어 급속히 보급되기 시작하고 있다.In the image information age, much expectation is gathered in the display device which is a person in charge of information transmission. As a result, various flat display devices in place of the cathode ray tube (CRT) have been developed and are rapidly spreading.
그중에서도 액정표시장치(LCD)는 극도로 경량으로 박형, 저가 저소비 전력구동으로 집적회로와의 정합성이 좋은 점등의 특징을 가져 랩 톱 컴퓨터나 포켓 컴퓨터의 표시에 차량적재용, 칼라 텔레비젼 화상용으로 그 용도를 확대하고 있다.Among them, liquid crystal display (LCD) is extremely lightweight, thin, low-cost, low-power operation, and has good lighting characteristics, which is compatible with integrated circuits. It is expanding its use.
상기한 액정표시장치를 액티브 매트릭스 방식으로 구동하기 위해서 티에프티 액정표시장치가 사용된다.In order to drive the liquid crystal display device in an active matrix manner, a TFT liquid crystal display device is used.
고온 티에프티 액정표시장치 제조공정에서는 게이트 절연막 액티브(Active) 층 패턴 형성이후 열산화하여 형성하는 것이 일반적인 방법이다.In the manufacturing process of the high temperature TFT liquid crystal display device, it is a general method to thermally oxidize the gate insulating layer after forming the active layer pattern.
이하, 첨부된 도면을 참조로 하여 종래의 기술을 설명하기로 한다.Hereinafter, a conventional technology will be described with reference to the accompanying drawings.
제1도는 종래의 게이트 절연막의 단면도이고, 제2도는 종래의 열산화후 화학기상증착법으로 산화막을 증착하는 방법으로 형성된 게이트 절연막의 단면도이고, 제3도는 종래의 게이트 절연막의 형성과정중에 홈이 생기는 과정을 도시한 단면도이다.1 is a cross-sectional view of a conventional gate insulating film, FIG. 2 is a cross-sectional view of a gate insulating film formed by a method of depositing an oxide film by a conventional chemical vapor deposition method after thermal oxidation, and FIG. It is a section showing the process.
제1도에 도시되어 있듯이, 종래에는 기판(1)위에 비정질 실리콘을 증착한후 액티브 패턴(2)을 형성하고, 그 위에 열산화하는 방법으로 게이트 절연막(5)을 형성하였다.As shown in FIG. 1, conventionally, after forming amorphous silicon on the substrate 1, the active pattern 2 is formed, and then the gate insulating film 5 is formed by thermal oxidation.
그러나 제1도에 도시된 바와 같이 종래의 게이트 절연막은 이후 공정에서 에지 시닝(9)과 같은 문제점이 발생하여, 티에프티 액정표시장치 패널을 신뢰성 있게 만들어야 하는 제조공정에 있어서 치명적으로 신뢰성에 문제를 야기시키는 단점이 있다.However, as shown in FIG. 1, the conventional gate insulating film has a problem such as edge thinning 9 in a subsequent process, thereby causing a critical reliability problem in a manufacturing process in which a TFT LCD panel must be made reliably. There is a disadvantage that causes.
이러한 문제 해결을 위해 제2도에 도시된 바와 같은 구조로 열산화후에 화학기상증착법으로 산화막을 증착하는 방법이 제시된 바 있으나 , 화학기상증착법으로 성장된 산화막의 경우 그 절연내압 및 누설전류 면에서 열산화막보다 훨씬 못 미치는 특성을 나타내고, 화학기상증착법으로 성장된 산화막(6)과 열산화막(4)의 계면트랩(Trap)의 발생으로 실제 소자 제작시 특성에 나쁜 효과를 미친다.In order to solve this problem, a method of depositing an oxide film by chemical vapor deposition after thermal oxidation with a structure as shown in FIG. 2 has been proposed. However, in the case of an oxide film grown by chemical vapor deposition, heat is reduced in terms of insulation breakdown voltage and leakage current. It exhibits properties far less than the oxide film, and has an adverse effect on the characteristics of the actual device fabrication due to the generation of an interface trap between the oxide film 6 and the thermal oxide film 4 grown by chemical vapor deposition.
또한 초기 열산화시 이미 네거티브 프로화일(Negative Profile)이 형성되고 화학기상증착법으로 성장된 산화막(6)이 그 에지를 파고 들어가므로 에지 시닝 현상에는 도움이 안된다.In addition, since the negative profile is already formed during the initial thermal oxidation, and the oxide film 6 grown by chemical vapor deposition penetrates the edge, it does not help the edge thinning phenomenon.
또한, 제3도에 도시되어 있듯이, 종래에는 아몰포스 실리콘(또는 폴리 실리콘) 위에 고온열산화막을 형성하면, 아몰포스 실리콘이 순식간에 폴리 실리콘이 되어버리고, 이때 생긴 폴리 실리콘의 결정입계(Grain Boundary)를 따라 열산화막이 빠르게 형성되어 홈(Grooving)이 깊게 생기는 단점이 있다.In addition, as shown in FIG. 3, when a high temperature thermal oxide film is conventionally formed on amorphous silicon (or polysilicon), amorphous silicon becomes instantaneously polysilicon, and the grain boundary of the polysilicon produced at this time is generated. According to the thermal oxide film is formed quickly there is a disadvantage that deep grooves (Grooving) occurs.
그러므로 본 발명의 목적은 종래의 단점을 해결하기 위한 것으로 저온 화학기상증착 산화막을 증착후 열산화함으로써, 에지 시닝 현상을 완전히 해결하고, 홈을 줄이며, 후기열산화 공정시 화학기상증착 산화막 덴시피케이션(Densification), 디하이드로제네이션(Dehydrogenation) 효과가 있어 전기적 특성 및 절연 특성에서도 열산화막과 동일한 결과를 얻을 수 있는 에지 시닝 형상을 없앤 이중게이트 절연막 및 그 형성방법을 제공하고자 하는데 있다.Therefore, an object of the present invention is to solve the drawbacks of the prior art by thermally oxidizing the low temperature chemical vapor deposition oxide film after deposition, to completely solve the edge thinning phenomenon, reduce the grooves, chemical vapor deposition oxide densification during the late thermal oxidation process It is intended to provide a double gate insulating film and a method of forming the same, which have an edge thinning shape that can achieve the same result as a thermal oxide film due to effects of densification and dehydrogenation.
상기 목적을 달성하고자하는 이 발명의 구성은,The configuration of the present invention to achieve the above object,
석영기판과;A quartz substrate;
상기 석영기판위에 최종 형성되어 있는 액티브 다결정 실리콘과;Active polycrystalline silicon finally formed on the quartz substrate;
상기 액티브 다결정 실리콘의 위에 형성되어 있는 열산화막과;A thermal oxide film formed on the active polycrystalline silicon;
열처리 공정 이전에 증착된 화학기상증착 산화막으로 이루어진다.It consists of a chemical vapor deposition oxide film deposited prior to the heat treatment process.
상기 목적을 달성하고자하는 이 발명의 다른 구성은,Another configuration of the present invention to achieve the above object,
석영기판 위에 비정질 실리콘을 증착후 액티브 패턴을 형성하는 단계와;Depositing amorphous silicon on the quartz substrate to form an active pattern;
상기의 패턴 형성 후에 저온 화학기상증착 산화막을 증착하는 단계와;Depositing a low temperature chemical vapor deposition oxide film after forming the pattern;
상기의 저온 화학기상증착 산화막 형성 후에 열산화막을 형성하는 단계로 이루어진다.After forming the low temperature chemical vapor deposition oxide film is formed of a thermal oxide film.
상기 구성에 의하여 이 발명을 용이하게 실시할 수 있는 가장 바람직한 실시예를 첨부된 도면을 참조로 하여 설명하면 다음과 같다.When described with reference to the accompanying drawings the most preferred embodiment which can easily implement this invention by the above configuration as follows.
제4도는 이 발명의 실시예에 따른 에지 시닝 형상을 없앤 이중게이트 절연막의 형성전에 저온 산화막을 증착시킨 단면도이고,4 is a cross-sectional view of depositing a low temperature oxide film before the formation of the double gate insulating film without the edge thinning shape according to the embodiment of the present invention,
제5도는 이 발명의 실시예에 따른 에지 시닝 형상을 없앤 이중게이트 절연막의 단면도이고,5 is a cross-sectional view of the double gate insulating film without the edge thinning shape according to the embodiment of the present invention,
제6도는 이 발명의 실시예에 따른 에지 시닝 형상을 없앤 이중게이트 절연막의 형성과정중에 홈이 줄어드는 과정을 도시한 단면도이고,6 is a cross-sectional view illustrating a process of reducing grooves during formation of a double gate insulating film without edge thinning according to an embodiment of the present invention.
제7도는 이 발명의 실시예에 따른 에지 시닝 형상을 없앤 이중게이트 절연막을 일정조건으로 실험한 결과표이고,FIG. 7 is a table showing results of experimenting with a double gate insulating film without edge edge thinning according to an embodiment of the present invention under predetermined conditions.
제8도는 이 발명의 실시예에 따른 에지 시닝 형상을 없앤 이중게이트 절연막의 실험을 위한 회로도이고,8 is a circuit diagram for an experiment of a double gate insulating film without the edge thinning shape according to the embodiment of the present invention,
제9도는 제8도의 회로에 대하여 일정조건으로 실험한 결과표이다.9 is a result table of the circuit of FIG. 8 under certain conditions.
제5도에 도시되어 있듯이, 이 발명의 실시예에 따른 에지 시닝 형상을 없앤 이중게이트 절연막의 구성은,As shown in FIG. 5, the structure of the double gate insulating film without the edge thinning shape according to the embodiment of the present invention is
석영기판(1)위에 상기 기판위에 최종 형성되어 있는 액티브 다결정 실리콘(2)이 덮여 있고, 그 위에 열산화막(4)이 덮여 있고, 그 위에 열처리 공정 이전에 증착된 화학기상증착 산화막(3)이 덮여 있는 구조로 이루어진다.The active polycrystalline silicon 2 finally formed on the substrate is covered on the quartz substrate 1, the thermal oxide film 4 is covered thereon, and the chemical vapor deposition oxide film 3 deposited before the heat treatment process is deposited thereon. It consists of a covered structure.
상기 구성에 의한 에지 시닝 형상을 없앤 이중게이트 절연막의 제조방법은 다음과 같다.The manufacturing method of the double gate insulating film which removed the edge thinning shape by the said structure is as follows.
제4도에 도시되어 있듯이, 먼저 기판(1)위에 비정질 실리콘을 증착후 액티브 패턴(2)을 형성한다.As shown in FIG. 4, first, amorphous silicon is deposited on the substrate 1 to form an active pattern 2.
상기 액티브 패턴(2) 위에 저온 화학기상증착(APCVD, PECVD, LTO, ECR-CVD) 산화막(3)을 500Å 증착한다.500 Å of low temperature chemical vapor deposition (APCVD, PECVD, LTO, ECR-CVD) oxide film 3 is deposited on the active pattern 2.
상기한 저온 산화막(3) 증착은 산화막 증착시 액티브 패턴(2)의 뉴클리에이션(Neucleation)을 방지하기 위함이다.The low temperature oxide film 3 is deposited to prevent nucleation of the active pattern 2 when the oxide film is deposited.
고온산화막(HTO)을 증착하게 되면 뉴클리에이션이 일어나 이후 열산화 공정에서 그레인 성장(Grain-Growth)을 방해하는 요인으로 작용하게 된다.The deposition of high temperature oxide (HTO) causes nucleation, which acts as a factor that prevents grain-growth in the thermal oxidation process.
제3도와 같이 형성된 이후 열산화막(4)을 200Å 내지 600Å 바람직하게는 500Å 형성시킨다.After the thermal oxide film 4 is formed as shown in FIG. 3, the thermal oxide film 4 is formed at 200 kPa to 600 kPa, preferably 500 kPa.
상기한 저온 산화막(3)과 열산화막(4)의 두께는 수십 내지 디바이스의 최고 요구 절연내압을 견디는 두께로 제조하는 것을 특징으로 한다.The thickness of the low temperature oxide film 3 and the thermal oxide film 4 is characterized in that it is manufactured to a thickness that withstands the highest required dielectric breakdown voltage of the device.
상기한 저온 산화막(3)과 열산화막(4)의 두께는 1000Å 내지 1200Å이 되는 것이 바람직하다.It is preferable that the thickness of the low temperature oxide film 3 and the thermal oxide film 4 be 1000 kPa to 1200 kPa.
열산화막(4)의 형성시 액티브 패턴(2)은 비정질 실리콘 상태에서 다결정 실리콘으로 되며 열산화막(4)이 액티브 패턴(2)과 저온 산화막(3)의 계면에서부터 형성되므로 열산화막 만으로만 게이트 산화막을 형성한 제1도에 도시된 종래의 게이트 절연막과 같은 특성을 얻을 수 있다.When the thermal oxide film 4 is formed, the active pattern 2 is made of polycrystalline silicon in an amorphous silicon state, and since the thermal oxide film 4 is formed from the interface between the active pattern 2 and the low temperature oxide film 3, the gate oxide film is formed only by the thermal oxide film. The same characteristics as the conventional gate insulating film shown in FIG.
또한 열산화막(4)의 형성시 저온 산화막(3) 자체의 덴시피케이션 및 디하이드로제네이션이 일어나므로 화학기상증착 산화막의 특성이 열산화막과 동일해진다.In addition, when the thermal oxide film 4 is formed, densification and dehydrogenation of the low temperature oxide film 3 itself occur, so that the characteristics of the chemical vapor deposition oxide film are the same as the thermal oxide film.
또한 열산화막(4) 형성과정이 화학기상증착 산화막과 열산화막 계면이 트랩을 치유해 주고 박막과 박막의 스트레스(STRESS)를 릴리스(Realease)해주는 역할을 하므로 막 자체의 안전성을 확보할 수 있다. 무엇보다도 이러한 공정을 사용하게 되면 에지 시닝 현상을 완벽히 해결할 수 있어 이후 게이트 형성(증착 및 패턴 형성)시에 게이트 물질이 에지에 잔류하는 문제 발생을 방지할 수 있게 되었다.In addition, the formation process of the thermal oxide film 4 serves to secure the safety of the film itself because the chemical vapor deposition oxide film and the thermal oxide film interface heal the trap and release the stress of the thin film and the thin film. Best of all, this process completely eliminates edge thinning, preventing gate material from remaining at the edges during gate formation (deposition and pattern formation).
상기한 열산화막(4)을 100Å 내지 500Å 정도만 형성하면 제6도와 같은 홈이 감소한 이중게이트 절연막을 얻을 수 있다.If the thermal oxide film 4 is formed at only about 100 kPa to about 500 kPa, a double gate insulating film having reduced grooves as shown in FIG. 6 can be obtained.
참고로 다음과 같은 조건으로 완성된 이중게이트 절연막을 실험한 결과를 제7도의 표에 도시하였다.For reference, the test results of the double gate insulating film completed under the following conditions are shown in the table of FIG. 7.
조건: 비정질 실리콘을 560℃의 온도와 SiH4+H2혼합 기체 분위기에서 600Å의 두께로 증착하고 패터닝하여 액티브 패턴을 형성하고, 400℃의 온도와 각각 25sccm와 1100sccm의 유량을 갖는 SiH4+n2O 혼합 기체 분위기에서 플라즈마 인헨스드(plasma enhanced) 화학기상증착법으로 600Å 두께의 산화막(PEOX)을 증착하고, 다시 1,050℃의 온도에서 산호(O2) 기체를 공급하여 열산화막을 500Å 성장시킨다. 이때 비정실 실리콘의 결정화가 동시에 일어난다.Conditions: Amorphous silicon was deposited and patterned to 600 두께 in a 560 ° C. and SiH 4 + H 2 mixed gas atmosphere to form an active pattern, SiH 4 + n with a temperature of 400 ° C. and a flow rate of 25 sccm and 1100 sccm, respectively. A 600 O thick oxide film (PEOX) is deposited by plasma enhanced chemical vapor deposition in a 2 O mixed gas atmosphere, and then, a 500 Å thermal oxide film is grown by supplying coral (O 2 ) gas at a temperature of 1,050 ° C. At this time, crystallization of amorphous silicon occurs simultaneously.
또한, 제8도에 도시된 조건으로 실험한 결과를 제9도의 표에 도시하였다.In addition, the results of the experiment shown in FIG. 8 are shown in the table of FIG. 9.
이상에서와 같이 이 발명의 실시예에서 저온 화학기상증착 산화막을 증착후 열산화함으로써, 에지 시닝 현상을 완전히 해결하고, 홈을 줄이며, 후기 열산화 공정시 화학기상증착 산화막 덴시피케이션, 디하이드로제네이션 효과가 있어 전기적 특성 및 절연 특성에서도 열산화막과 동일한 결과를 얻을 수 있는 잇점이 있는 에지 시닝 형상을 없앤 이중게이트 절연막 및 그 형성방법을 제공할 수 있다.As described above, by depositing and thermally oxidizing the low temperature chemical vapor deposition oxide film in the embodiment of the present invention, the edge thinning phenomenon is completely solved, the grooves are reduced, and the chemical vapor deposition oxide film deposition and dehydroze during the late thermal oxidation process. It is possible to provide a double-gate insulating film and a method of forming the same, which have an edge effect and eliminate the edge thinning shape, which has the advantage of achieving the same result as the thermal oxide film in electrical and insulating properties.
Claims (7)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019940035626A KR0154765B1 (en) | 1994-12-21 | 1994-12-21 | Thin film transistor |
| JP7333625A JPH08236778A (en) | 1994-12-21 | 1995-12-21 | Duplex gate insulation film and its forming method |
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| KR1019940035626A KR0154765B1 (en) | 1994-12-21 | 1994-12-21 | Thin film transistor |
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| KR960026975A KR960026975A (en) | 1996-07-22 |
| KR0154765B1 true KR0154765B1 (en) | 1998-10-15 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7052940B2 (en) | 2002-09-04 | 2006-05-30 | Lg.Philips Lcd Co., Ltd. | Method of fabricating top gate type thin film transistor having low temperature polysilicon |
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| TW334581B (en) | 1996-06-04 | 1998-06-21 | Handotai Energy Kenkyusho Kk | Semiconductor integrated circuit and fabrication method thereof |
| KR19980055948A (en) * | 1996-12-28 | 1998-09-25 | 김영환 | Gate oxide film formation method of a semiconductor device |
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1994
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US7052940B2 (en) | 2002-09-04 | 2006-05-30 | Lg.Philips Lcd Co., Ltd. | Method of fabricating top gate type thin film transistor having low temperature polysilicon |
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| KR960026975A (en) | 1996-07-22 |
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