JPH05198744A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH05198744A JPH05198744A JP763892A JP763892A JPH05198744A JP H05198744 A JPH05198744 A JP H05198744A JP 763892 A JP763892 A JP 763892A JP 763892 A JP763892 A JP 763892A JP H05198744 A JPH05198744 A JP H05198744A
- Authority
- JP
- Japan
- Prior art keywords
- film
- forming
- semiconductor device
- lower electrode
- silicon nitride
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は半導体装置の製造方法に
関し、特に容量部の形成方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming a capacitor portion.
【0002】[0002]
【従来の技術】従来の半導体装置における容量部の形成
方法を図3を用いて説明する。2. Description of the Related Art A conventional method of forming a capacitor portion in a semiconductor device will be described with reference to FIG.
【0003】まず、図3(a)に示すように減圧気相成
長法により多結晶シリコン膜を堆積後フォトリソグラフ
ィー技術とエッチング技術により下部電極3を形成す
る。First, as shown in FIG. 3A, a lower electrode 3 is formed by a photolithography technique and an etching technique after depositing a polycrystalline silicon film by a low pressure vapor deposition method.
【0004】次に、図3(b)に示すように急速熱窒化
を行うことにより、下部電極3の表面に薄いシリコン窒
化膜5を形成した後、図3(c)に示すように減圧気相
成長法により所望の膜厚のシリコン窒化膜7を堆積させ
る。Next, as shown in FIG. 3 (b), rapid thermal nitriding is performed to form a thin silicon nitride film 5 on the surface of the lower electrode 3, and then a reduced pressure gas is formed as shown in FIG. 3 (c). A silicon nitride film 7 having a desired film thickness is deposited by a phase growth method.
【0005】次に、容量絶縁膜としてのシリコン窒化膜
5, 7を通してリーク電流が流れるのを防ぐために酸化
を行い、図3(d)に示すようにシリコン酸化膜8を形
成する。その後、減圧気相成長法により多結晶シリコン
膜を堆積させた後、フォトリソグラフィー技術とエッチ
ング技術を用いて、図3(e)に示すように上部電極6
を形成し、容量部を完成させる。Next, oxidation is performed in order to prevent a leak current from flowing through the silicon nitride films 5 and 7 as the capacitive insulating film, and a silicon oxide film 8 is formed as shown in FIG. 3 (d). After that, a polycrystalline silicon film is deposited by the low pressure vapor deposition method, and then the upper electrode 6 is formed by using the photolithography technique and the etching technique as shown in FIG.
Are formed to complete the capacitance section.
【0006】[0006]
【発明が解決しようとする課題】ところで、半導体装置
の微細化が進むにつれて、容量部の占有面積が小さくな
り、容量値の確保が次第に困難となってきている。この
ため容量値を確保するための手段として容量部電極の表
面積の増大や容量絶縁膜の薄膜化などが検討されてい
る。By the way, as the miniaturization of the semiconductor device progresses, the occupied area of the capacitor portion becomes smaller, and it becomes increasingly difficult to secure the capacitance value. For this reason, increasing the surface area of the capacitor electrode and thinning the capacitor insulating film have been studied as means for securing the capacitance value.
【0007】現在においては容量絶縁膜の薄膜化は5n
mにまで及んでいるが、減圧気相成長法により堆積した
容量絶縁膜としてのシリコン窒化膜が疎な膜であるため
に、これ以上の薄膜化を行うと容量絶縁膜を通して流れ
るリーク電流が急激に増大し、容量部としての役割を果
たさなくなるという問題点があった。At present, the thinning of the capacitance insulating film is 5n.
However, since the silicon nitride film as the capacitive insulating film deposited by the low pressure vapor deposition method is a sparse film, the leakage current flowing through the capacitive insulating film becomes abrupt when the thickness is further reduced. However, there is a problem in that it does not play the role of the capacitance section.
【0008】また、さらに薄膜化を行うと、減圧気相成
長法によるシリコン窒化膜堆積後の酸化工程により、シ
リコン窒化膜の耐酸化性がやぶれ、酸化膜が厚く形成さ
れてしまうために、半導体装置に必要な容量値が得られ
なくなるという問題点があった。Further, if the thickness is further reduced, the oxidation resistance of the silicon nitride film is deteriorated due to the oxidation process after the deposition of the silicon nitride film by the low pressure vapor phase epitaxy method, and the oxide film is formed thick. There is a problem that the capacity value required for the device cannot be obtained.
【0009】本発明は、このような従来技術の課題に鑑
みて提案されたもので、下部電極と容量絶縁膜と上部電
極を有する半導体装置において、容量絶縁膜を密な膜に
することによりリーク電流を増加させることなく薄膜化
を行ない従来のものに比し容量値の大きい容量部を形成
することのできる半導体装置の製造方法を提供すること
を目的とする。The present invention has been proposed in view of the above problems of the prior art, and in a semiconductor device having a lower electrode, a capacitive insulating film, and an upper electrode, by making the capacitive insulating film a dense film, leakage occurs. It is an object of the present invention to provide a method for manufacturing a semiconductor device, which is capable of forming a thin film without increasing the current and forming a capacitor portion having a larger capacitance value than a conventional one.
【0010】[0010]
【課題を解決するための手段】本発明の半導体装置の製
造方法は、下部電極形成後、シリコン膜を形成する工程
と前記シリコン膜を熱窒化する工程を複数回繰り返すこ
とにより容量絶縁膜を形成することを特徴とする。According to the method of manufacturing a semiconductor device of the present invention, a capacitor insulating film is formed by repeating a step of forming a silicon film and a step of thermally nitriding the silicon film after forming a lower electrode. It is characterized by doing.
【0011】本発明によればまた、半導体基板に所定寸
法の溝部を形成し、該溝を覆う様に下部電極を形成し、
該下部電極形成後にシリコン膜を形成する工程と前記シ
リコン膜を熱窒化する工程を少なくとも2回以上繰り返
すことにより容量絶縁膜を形成し、かつ、該容量絶縁膜
形成溝を埋めるようにして上部電極を形成することを特
徴とする半導体装置の製造方法が得られる。According to the present invention, a groove portion having a predetermined size is formed on the semiconductor substrate, and a lower electrode is formed so as to cover the groove,
The step of forming a silicon film after the formation of the lower electrode and the step of thermally nitriding the silicon film are repeated at least twice to form a capacitive insulating film and to fill the groove for forming the capacitive insulating film. A method for manufacturing a semiconductor device is obtained which is characterized in that
【0012】[0012]
【実施例】次に本発明について図面を参照して説明す
る。The present invention will be described below with reference to the drawings.
【0013】図1は本発明の第1実施例を示す半導体装
置の容量部形成プロセスフロー図である。FIG. 1 is a process flow diagram for forming a capacitor portion of a semiconductor device showing a first embodiment of the present invention.
【0014】まず、シリコン酸化膜2に開孔部を形成し
た状態の半導体基板1に減圧気相成長法により多結晶シ
リコン膜を堆積させる。この後、フォトリソグラフィー
技術とエッチング技術により下部電極3を形成する(図
1(a))。この下部電極3までを形成する方法は従来
と同様である。First, a polycrystalline silicon film is deposited on the semiconductor substrate 1 in which the openings are formed in the silicon oxide film 2 by the low pressure vapor deposition method. After that, the lower electrode 3 is formed by the photolithography technique and the etching technique (FIG. 1A). The method of forming the lower electrode 3 is the same as the conventional method.
【0015】次にSiH4 ガスを用いた温度600℃で
の減圧気相成長法により多結晶シリコン膜4を1nmの
膜厚で堆積させた後(図1(b))、ランプアニール装
置を用いて850℃、60秒間NH3 雰囲気中でアニー
ルすることにより、多結晶シリコン膜4を窒化し、1.
5nmのシリコン窒化膜5を形成する(図1(c))。Next, after depositing a polycrystalline silicon film 4 to a thickness of 1 nm by a reduced pressure vapor deposition method using SiH4 gas at a temperature of 600 ° C. (FIG. 1 (b)), a lamp annealing apparatus is used. The polycrystalline silicon film 4 is nitrided by annealing in a NH 3 atmosphere at 850 ° C. for 60 seconds to
A 5 nm silicon nitride film 5 is formed (FIG. 1C).
【0016】次に、1層目の多結晶シリコン膜4を堆積
した場合と同条件の減圧気相成長法により2層目の多結
晶シリコン膜4を堆積させた後(図1(d))、ランプ
アニール装置で1層目のシリコン窒化膜5を形成した場
合と同条件により、2層目のシリコン窒化膜5を形成す
る(図1(e))。この状態で計3nmのシリコン窒化
膜が形成される。Next, after the second-layer polycrystalline silicon film 4 is deposited by the low pressure vapor deposition method under the same conditions as the case of depositing the first-layer polycrystalline silicon film 4 (FIG. 1 (d)). The second-layer silicon nitride film 5 is formed under the same conditions as when the first-layer silicon nitride film 5 was formed by the lamp annealing apparatus (FIG. 1E). In this state, a silicon nitride film with a total thickness of 3 nm is formed.
【0017】次に減圧気相成長法により所望の膜厚の多
結晶シリコン膜を堆積させた後、フォトリソグラフィー
技術とエッチング技術により上部電極6を形成し、容量
部を完成させる(図1(f))。Next, after depositing a polycrystalline silicon film having a desired film thickness by the low pressure vapor deposition method, the upper electrode 6 is formed by the photolithography technique and the etching technique to complete the capacitor portion (FIG. 1 (f). )).
【0018】この方法により形成したシリコン窒化膜5
は、従来の減圧気相成長法により形成したシリコン窒化
膜よりも密であり、ピンホールが存在しないため、従来
シリコン窒化膜のピンホールを無くすために行っていた
酸化の工程を不要とすることができる。Silicon nitride film 5 formed by this method
Is denser than the silicon nitride film formed by the conventional low pressure vapor phase epitaxy method and does not have pinholes. Therefore, it is possible to eliminate the oxidation step which was conventionally performed to eliminate the pinholes in the silicon nitride film. You can
【0019】また、この発明の方法によれば、酸化の工
程を行わずに済むために、シリコン窒化膜を薄くしても
耐酸化性のやぶれにより厚くシリコン酸化膜が形成され
半導体装置に必要な容量値が得られなくなるという従来
の問題は生じなくなる。Further, according to the method of the present invention, since the oxidation step is not necessary, a thick silicon oxide film is formed due to the oxidation resistance blur even if the silicon nitride film is thin, which is necessary for a semiconductor device. The conventional problem that the capacitance value cannot be obtained does not occur.
【0020】また従来の方法により形成したシリコン窒
化膜が容量絶縁膜としての役割を果たすことができる下
限界膜厚はリーク電流の問題で5nm前後であったが、
本発明によりシリコン窒化膜が密な膜となったため、膜
厚を3nm前後にまで薄くしてもリーク電流が増加する
という問題は生じない。The lower limit film thickness at which the silicon nitride film formed by the conventional method can function as a capacitive insulating film is about 5 nm due to the problem of leak current.
Since the silicon nitride film is a dense film according to the present invention, there is no problem that the leak current increases even if the film thickness is reduced to about 3 nm.
【0021】そのためシリコン窒化膜の膜厚を従来の下
限界膜厚の5分の3にまで薄膜化することにより、容量
値を従来の3分の5倍にすることができる。Therefore, by reducing the film thickness of the silicon nitride film to three-fifths of the conventional lower limit film thickness, the capacitance value can be increased to three-fifths of the conventional value.
【0022】図2は本発明の第2実施例を示す半導体装
置の容量部形成プロセスフロー図である。FIG. 2 is a process flow chart for forming a capacitor portion of a semiconductor device showing a second embodiment of the present invention.
【0023】まず図2(a)に示すように、フォトリソ
グラフィー技術とエッチング技術により溝を形成した
後、不純物を注入して下部電極3を形成する。次に第1
の実施例と同様に、減圧気相成長法による多結晶シリコ
ン膜の堆積と、その膜をランプアニール装置により急速
熱窒化する工程を繰り返して3nmの膜厚のシリコン窒
化膜5を形成する(図2(b))。First, as shown in FIG. 2A, after forming a groove by a photolithography technique and an etching technique, impurities are implanted to form a lower electrode 3. Then the first
In the same manner as in Example 1, the step of depositing a polycrystalline silicon film by the low pressure vapor phase epitaxy method and the step of rapid thermal nitriding the film by a lamp annealing device are repeated to form a silicon nitride film 5 having a thickness of 3 nm (FIG. 2 (b)).
【0024】次に減圧気相成長法により所望の膜厚の多
結晶シリコン膜を堆積させた後、フォトリソグラフィー
技術とエッチング技術により上部電極6を形成して容量
部を完成させる(第2図(c))。第2実施例において
もシリコン窒化膜は密に形成され、従来の下限界膜厚よ
りも薄くすることが可能となる。このため、第2実施例
も第1実施例と同等の効果を有し、さらに本第2実施例
を用いることにより素子の平坦化が容易となる。Next, a polycrystalline silicon film having a desired film thickness is deposited by the reduced pressure vapor deposition method, and then the upper electrode 6 is formed by the photolithography technique and the etching technique to complete the capacitor portion (see FIG. 2 ( c)). Also in the second embodiment, the silicon nitride film is densely formed and can be made thinner than the conventional lower limit film thickness. Therefore, the second embodiment has the same effect as that of the first embodiment, and by using the second embodiment, it becomes easy to flatten the element.
【0025】[0025]
【発明の効果】以上説明したように本発明は、下部電極
形成後、シリコン膜を形成する工程と、前記シリコン膜
を熱窒化する工程を繰り返すことにより、減圧気相成長
法により堆積したシリコン窒化膜よりも密な膜を形成で
きるため、シリコン窒化膜形成後の酸化工程が不要とな
る。またリーク電流を増大させることなく、容量絶縁膜
を薄膜化して容量値を従来の3分の5倍にまで増大させ
ることができるという効果を有する。As described above, according to the present invention, by repeating the step of forming a silicon film after forming the lower electrode and the step of thermally nitriding the silicon film, the silicon nitride deposited by the low pressure vapor phase epitaxy method is repeated. Since a film denser than the film can be formed, the oxidation step after forming the silicon nitride film is unnecessary. In addition, there is an effect that the capacitance insulating film can be thinned and the capacitance value can be increased to 5 times the conventional value without increasing the leak current.
【0026】また、これにより第4図に示す通り、従来
3〜20%程度であったホールド不良率を5%以下に低
減できるという効果を有する。As a result, as shown in FIG. 4, there is an effect that the hold failure rate, which was about 3 to 20% in the past, can be reduced to 5% or less.
【図1】本発明の第1実施例を示す半導体装置の容量部
形成プロセスフロー図。FIG. 1 is a process flow diagram of forming a capacitor portion of a semiconductor device showing a first embodiment of the present invention.
【図2】本発明の第2実施例を示す半導体装置の容量部
形成プロセスフロー図。FIG. 2 is a process flow chart of forming a capacitor portion of a semiconductor device showing a second embodiment of the present invention.
【図3】従来の半導体装置の容量部プロセスフロー図。FIG. 3 is a process flow diagram of a conventional semiconductor device capacitor section.
【図4】製法とホールド不良率との相関関係。FIG. 4 is a correlation between a manufacturing method and a hold failure rate.
1…半導体基板 2…シリコン酸化膜 3…下部電極 4…多結晶シリコン膜 5…シリコン窒化膜 6…上部電極 7…シリコン窒化膜 8…シリコン酸化膜 DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate 2 ... Silicon oxide film 3 ... Lower electrode 4 ... Polycrystalline silicon film 5 ... Silicon nitride film 6 ... Upper electrode 7 ... Silicon nitride film 8 ... Silicon oxide film
Claims (2)
する半導体装置において、前記下部電極形成後にシリコ
ン膜を形成する工程と前記シリコン膜を熱窒化する工程
を少なくとも2回以上繰り返すことにより前記容量絶縁
膜を形成することを特徴とする半導体装置の製造方法。1. A semiconductor device having a lower electrode, a capacitive insulating film and an upper electrode, wherein the step of forming a silicon film after the formation of the lower electrode and the step of thermally nitriding the silicon film are repeated at least twice. A method of manufacturing a semiconductor device, comprising forming a capacitive insulating film.
該溝を覆う様に下部電極を形成し、該下部電極形成後に
シリコン膜を形成する工程と前記シリコン膜を熱窒化す
る工程を少なくとも2回以上繰り返すことにより容量絶
縁膜を形成し、かつ、該容量絶縁膜形成溝を埋めるよう
にして上部電極を形成することを特徴とする半導体装置
の製造方法。2. A groove portion having a predetermined size is formed on a semiconductor substrate,
A lower electrode is formed so as to cover the groove, and a step of forming a silicon film after forming the lower electrode and a step of thermally nitriding the silicon film are repeated at least twice to form a capacitor insulating film, and A method of manufacturing a semiconductor device, comprising forming an upper electrode so as to fill a groove for forming a capacitance insulating film.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4007638A JP3006809B2 (en) | 1992-01-20 | 1992-01-20 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4007638A JP3006809B2 (en) | 1992-01-20 | 1992-01-20 | Method for manufacturing semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH05198744A true JPH05198744A (en) | 1993-08-06 |
JP3006809B2 JP3006809B2 (en) | 2000-02-07 |
Family
ID=11671376
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4007638A Expired - Lifetime JP3006809B2 (en) | 1992-01-20 | 1992-01-20 | Method for manufacturing semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP3006809B2 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6194775B1 (en) | 1997-01-16 | 2001-02-27 | Nec Corporation | Semiconductor element with thermally nitrided film on high resistance film and method of manufacturing the same |
KR100707517B1 (en) * | 1999-12-13 | 2007-04-13 | 발레오 에끼쁘망 엘렉뜨리끄 모뙤르 | Method and device for controlling an electric machine rotor field coil power such as a vehicle alternator-starter |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0293071A (en) * | 1988-09-29 | 1990-04-03 | Toshiba Corp | Thin film formation |
-
1992
- 1992-01-20 JP JP4007638A patent/JP3006809B2/en not_active Expired - Lifetime
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0293071A (en) * | 1988-09-29 | 1990-04-03 | Toshiba Corp | Thin film formation |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6194775B1 (en) | 1997-01-16 | 2001-02-27 | Nec Corporation | Semiconductor element with thermally nitrided film on high resistance film and method of manufacturing the same |
US6358808B1 (en) | 1997-01-16 | 2002-03-19 | Nec Corporation | Semiconductor element with thermally nitrided film on high resistance film and method of manufacturing the same |
KR100707517B1 (en) * | 1999-12-13 | 2007-04-13 | 발레오 에끼쁘망 엘렉뜨리끄 모뙤르 | Method and device for controlling an electric machine rotor field coil power such as a vehicle alternator-starter |
Also Published As
Publication number | Publication date |
---|---|
JP3006809B2 (en) | 2000-02-07 |
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