JPS6239788B2 - - Google Patents

Info

Publication number
JPS6239788B2
JPS6239788B2 JP55163796A JP16379680A JPS6239788B2 JP S6239788 B2 JPS6239788 B2 JP S6239788B2 JP 55163796 A JP55163796 A JP 55163796A JP 16379680 A JP16379680 A JP 16379680A JP S6239788 B2 JPS6239788 B2 JP S6239788B2
Authority
JP
Japan
Prior art keywords
data
input
command
output device
channel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP55163796A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5786926A (en
Inventor
Masao Koyabu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55163796A priority Critical patent/JPS5786926A/ja
Publication of JPS5786926A publication Critical patent/JPS5786926A/ja
Publication of JPS6239788B2 publication Critical patent/JPS6239788B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)
JP55163796A 1980-11-19 1980-11-19 Data transfer controlling system of channel device Granted JPS5786926A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55163796A JPS5786926A (en) 1980-11-19 1980-11-19 Data transfer controlling system of channel device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55163796A JPS5786926A (en) 1980-11-19 1980-11-19 Data transfer controlling system of channel device

Publications (2)

Publication Number Publication Date
JPS5786926A JPS5786926A (en) 1982-05-31
JPS6239788B2 true JPS6239788B2 (fr) 1987-08-25

Family

ID=15780860

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55163796A Granted JPS5786926A (en) 1980-11-19 1980-11-19 Data transfer controlling system of channel device

Country Status (1)

Country Link
JP (1) JPS5786926A (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6222167A (ja) * 1985-07-22 1987-01-30 Nec Corp タイムアウト検出回路

Also Published As

Publication number Publication date
JPS5786926A (en) 1982-05-31

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