JPS6239534B2 - - Google Patents

Info

Publication number
JPS6239534B2
JPS6239534B2 JP54158933A JP15893379A JPS6239534B2 JP S6239534 B2 JPS6239534 B2 JP S6239534B2 JP 54158933 A JP54158933 A JP 54158933A JP 15893379 A JP15893379 A JP 15893379A JP S6239534 B2 JPS6239534 B2 JP S6239534B2
Authority
JP
Japan
Prior art keywords
thin film
substrate
gas
substrates
raw material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP54158933A
Other languages
Japanese (ja)
Other versions
JPS5681923A (en
Inventor
Hajime Ichanagi
Nobuhiko Fujita
Hiroshi Kawai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Industries Ltd
Original Assignee
Sumitomo Electric Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Electric Industries Ltd filed Critical Sumitomo Electric Industries Ltd
Priority to JP15893379A priority Critical patent/JPS5681923A/en
Publication of JPS5681923A publication Critical patent/JPS5681923A/en
Publication of JPS6239534B2 publication Critical patent/JPS6239534B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02524Group 14 semiconducting materials
    • H01L21/02532Silicon, silicon germanium, germanium
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/458Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/0262Reduction or decomposition of gaseous compounds, e.g. CVD

Description

【発明の詳細な説明】 本発明は原料ガスを分解することにより薄膜を
得るいわゆるCVD(Chemical Vapor
Deposition)法による薄膜製造法に関する。
Detailed Description of the Invention The present invention is a so-called CVD (Chemical Vapor
Regarding the thin film manufacturing method using the Deposition method.

CVD法には次の3つの方法がある。1つは常
圧下で高温に保たれた反応容器内で原料ガスを熱
分解することにより薄膜を得るいわゆる常圧
CVD法であり、他の1つは気体の平均自由工程
を高め均一な膜厚を得るために減圧下で高温に保
たれた反応容器内で原料ガスを熱分解することに
より薄膜を得るいわゆる減圧CVD法であり、1
つは低温で膜を形成するために原料ガスをグロー
放電分解することにより薄膜を得るいわゆるプラ
ズマCVD法である。
There are three methods of CVD method: One is the so-called normal pressure method in which a thin film is obtained by thermally decomposing raw material gas in a reaction vessel kept at high temperature under normal pressure.
The other method is the so-called reduced pressure method, in which a thin film is obtained by thermally decomposing the raw material gas in a reaction vessel kept at high temperature under reduced pressure in order to increase the mean free path of the gas and obtain a uniform film thickness. CVD method, 1
One is the so-called plasma CVD method, which obtains thin films by glow discharge decomposition of raw material gases to form films at low temperatures.

従来、上記のCVD法は半導体集積回路製作に
おいてシリコン(Si)、金属、窒化物、酸化物な
どのエピタキシヤル成長、あるいはSiO2、Si3N4
などの絶縁保護膜の作製に、また各種工具製作に
おいて、TiC、TiNに代表される炭化物、窒化物
のコーテイングに応用されてきた。またプラズマ
CVD法はシラン(SiH4)ガスをグロー放電分解し
て得られるアモルフアスシリコン膜の形成などに
用いられている。アモルフアスシリコン膜は、置
換型不純物のドーピングにより、価電子制御が可
能であることが実験的に確められ、以来プラズマ
CVD法は、代替エネルギー源開発の要請に応え
る低コストの太陽電池や種々の電子デバイス製造
方法として着目されるようになつた。
Conventionally, the above CVD method has been used for epitaxial growth of silicon (Si), metals, nitrides, oxides, etc., or SiO 2 , Si 3 N 4 in the production of semiconductor integrated circuits.
It has been applied to coatings of carbides and nitrides, such as TiC and TiN, in the production of insulating protective films such as TiC and TiN, and in the production of various tools. Also plasma
The CVD method is used to form amorphous silicon films obtained by glow discharge decomposition of silane (SiH 4 ) gas. It has been experimentally confirmed that valence electrons can be controlled in amorphous silicon films by doping with substitutional impurities, and since then plasma
The CVD method has attracted attention as a method for manufacturing low-cost solar cells and various electronic devices that meet the demands for the development of alternative energy sources.

第1図は従来のCVD装置の概要を示す断面図
であり、1は反応容器、2は原料ガスを供給する
ガス供給口、3は原料ガス、4は排気ガス口、5
は排気ガス、6は基板、7は基板支持台である。
FIG. 1 is a cross-sectional view showing an outline of a conventional CVD apparatus, in which 1 is a reaction vessel, 2 is a gas supply port for supplying raw material gas, 3 is raw material gas, 4 is an exhaust gas port, and 5 is a gas supply port for supplying raw material gas.
6 is an exhaust gas, 6 is a substrate, and 7 is a substrate support stand.

しかしかかる構造のCVD装置は次のような次
点を有していた。基板6は、薄膜を形成するため
に離散して設置されそのために反応容器1の単位
容積あたりの生産性が低い。
However, the CVD apparatus with this structure had the following disadvantages. The substrates 6 are installed discretely to form a thin film, and therefore the productivity per unit volume of the reaction vessel 1 is low.

また、原料ガス3のまわり込みが良いため薄膜
は基板6の両面に形成される。薄膜の両面形成を
目的とする場合は構わないが、薄膜形成後片面の
みを使用する場合は裏面に堆積した薄膜は無駄と
なり、原料ガス3の収率は低下する。また、基板
6は外部ヒータ(図示せず)からの加熱であるた
めに熱効率が悪く、さらに反応容器1の内壁やヒ
ータ部に相当量の原料ガス分解生成物が堆積する
ために、原料ガス3の収率は低下する。また片面
のみに形成したい場合は裏面には薄膜形成を妨げ
るべくマスクが必要である。さらに上記のごとき
欠点は特にアモルフアスシリコン膜太陽電池等大
面積を必要とする薄膜を作製する場合問題とな
る。
Further, since the raw material gas 3 can circulate well, the thin film is formed on both sides of the substrate 6. It does not matter if the purpose is to form a thin film on both sides, but if only one side is used after forming the thin film, the thin film deposited on the back side will be wasted and the yield of the raw material gas 3 will decrease. Further, since the substrate 6 is heated by an external heater (not shown), thermal efficiency is poor, and furthermore, a considerable amount of raw material gas decomposition products accumulates on the inner wall of the reaction vessel 1 and the heater portion, so that the raw material gas 3 yield decreases. Furthermore, if it is desired to form on only one side, a mask is required on the back side to prevent thin film formation. Furthermore, the above-mentioned drawbacks become a problem especially when producing a thin film that requires a large area, such as an amorphous silicon film solar cell.

そこで発明者は上記欠点を解消すべく種々検討
を行なつた結果、2枚の基板の間にヒータを設置
し薄膜を製造するならば上記欠点が解消されると
考えた。
Therefore, the inventor conducted various studies to solve the above-mentioned drawbacks, and as a result, he thought that the above-mentioned drawbacks could be solved by installing a heater between two substrates and manufacturing a thin film.

従つて本発明の一つの目的は、反応容器単位容
積あたりの生産性の高いCVD法による薄膜製造
法を提供することにある。
Accordingly, one object of the present invention is to provide a thin film manufacturing method using the CVD method that has high productivity per unit volume of a reaction vessel.

本発明の他の目的は、原料ガスの収率の高い
CVD法による薄膜製造法を提供することにあ
る。
Another object of the present invention is to obtain a high yield of raw material gas.
The purpose of the present invention is to provide a thin film manufacturing method using the CVD method.

本発明の一つの目的は、ヒータの熱効率の高い
CVD法による薄膜製造法を提供することにあ
る。
One object of the present invention is to improve the thermal efficiency of the heater.
The purpose of the present invention is to provide a thin film manufacturing method using the CVD method.

本発明の他の目的は、基板の片面への薄膜形成
に際し裏面マスクの不要なCVD法による薄膜製
造法を提供することにある。本発明の一つの目的
は、大面積基板を用いたCVD法による薄膜製造
法を提供することにある。
Another object of the present invention is to provide a thin film manufacturing method using a CVD method that does not require a back mask when forming a thin film on one side of a substrate. One object of the present invention is to provide a thin film manufacturing method using a CVD method using a large-area substrate.

本発明は、ヒーターを介して二枚重ねにされた
長手方向に移動可能にされた二枚重ねの帯状の基
板と、ガス供給・排出方向を前記基板短手方向に
略一致させて、前記基板両側の前記基板長手方向
に交互に設けられたガス供給口およびガス排気口
とを有することを特徴とするCVD法による薄膜
製造法にある。
The present invention includes two stacked strip-shaped substrates that are stacked together and made movable in the longitudinal direction via a heater, and gas supply and discharge directions that are substantially aligned with the transverse direction of the substrates, and the substrates on both sides of the substrate. A thin film manufacturing method using a CVD method characterized by having gas supply ports and gas exhaust ports alternately provided in the longitudinal direction.

以下実施例について詳細に説明する。 Examples will be described in detail below.

第2図は本発明の薄膜製造に使用する装置の他
の実施例の概要を示す断面図であり、11は反応
容器、12は原料ガスを供給するガス供給口、1
3は排気ガス口、14はグロー放電用の第1の電
極、15は基板加熱用ヒータ、16はグロー放電
用の第2電極、17は帯状基板、18は電極14
と電極16とに接続されている直流または高周波
電源、19は帯状基板17を送り出すロール、2
0は帯状基板17を巻き取るロール、21は補助
ロールである。
FIG. 2 is a sectional view showing an outline of another embodiment of the apparatus used for thin film production of the present invention, in which 11 is a reaction vessel, 12 is a gas supply port for supplying raw material gas, and 1
3 is an exhaust gas port, 14 is a first electrode for glow discharge, 15 is a heater for heating a substrate, 16 is a second electrode for glow discharge, 17 is a strip-shaped substrate, and 18 is an electrode 14
and a DC or high frequency power source connected to the electrode 16; 19 is a roll for feeding out the strip substrate 17;
0 is a roll for winding up the strip substrate 17, and 21 is an auxiliary roll.

第2図に示す動作は、原料ガスをガス供給口1
2から供給し、排気ガス口13より排気し反応容
器11内の原料ガスの分圧を10-2〜10Torrと
し、電源18を起動させ、帯状基板17をロール
19から送り出すと同時にロール20に所望の膜
を堆積した帯状基板17を巻き取るものである。
The operation shown in Fig. 2 is to supply raw material gas to gas supply port 1.
2 and exhausted from the exhaust gas port 13 to set the partial pressure of the raw material gas in the reaction vessel 11 to 10 -2 to 10 Torr, start the power supply 18, and feed the strip substrate 17 from the roll 19 at the same time as the desired amount to the roll 20. The belt-shaped substrate 17 on which the film is deposited is wound up.

第2図に示す装置で原料ガスとしてシラン
(SiH4)ガスを使用し、基板は厚さ0.05mm、巾5
cm、長さ20mの帯状のステンレス鋼を使用し、基
板温度は250℃とし、高周波電源の出力は300Wの
条件で厚さ約1μmのアモルフアスシリコン膜を
作製した結果を、第2図に示す装置で帯状基板を
一枚のみとし、他の条件は上記と同じとしてアモ
ルフアスシリコン膜を作製した結果を比較すると
本発明法の方がはるかに優れていた。
Silane (SiH 4 ) gas is used as the source gas in the apparatus shown in Figure 2, and the substrate is 0.05 mm thick and 5 mm wide.
Figure 2 shows the results of fabricating an amorphous silicon film with a thickness of approximately 1 μm using a stainless steel strip with a length of 20 m and a substrate temperature of 250°C and a high frequency power supply output of 300 W. Comparing the results of producing an amorphous silicon film using only one strip-shaped substrate in the apparatus and keeping the other conditions the same as above, the method of the present invention was far superior.

以上の説明はシラン(SiH4)を原料ガスとして
アモルフアスシリコン膜を得る場合について述べ
たが、他のガスを使用し他の膜を得る場合も同様
の効果が得られることは明らかである。
Although the above description has been made regarding the case where an amorphous silicon film is obtained using silane (SiH 4 ) as a source gas, it is clear that similar effects can be obtained when other films are obtained using other gases.

また、上記説明は、ステンレス鋼の基板の場合
について述べたが、他の如何なる導電性基板ある
いは絶縁性基板であつても同様の効果が得られる
ことは明らかである。
Furthermore, although the above description has been made regarding the case of a stainless steel substrate, it is clear that similar effects can be obtained with any other conductive or insulating substrate.

以上詳細に説明したごとく、本発明の製造法に
よれば、反応容器単位容積あたりの生産性の高い
CVD法による薄膜が得られる。また本発明の製
造法によれば、ヒータの熱効率の高いCVD法に
よる薄膜が得られる。また本発明の製造法によれ
ば、基板の片面への薄膜形成に際し裏面マスクの
不要なCVD法による薄膜が得られる。また本発
明の製造法によれば、大面積基板を用いたCVD
法による大面積の薄膜が得られる。
As explained in detail above, according to the production method of the present invention, high productivity per unit volume of the reaction vessel can be achieved.
A thin film can be obtained using the CVD method. Further, according to the manufacturing method of the present invention, a thin film can be obtained by the CVD method with high heater thermal efficiency. Further, according to the manufacturing method of the present invention, a thin film can be obtained by the CVD method that does not require a back mask when forming a thin film on one side of a substrate. Furthermore, according to the manufacturing method of the present invention, CVD using a large-area substrate
A large area thin film can be obtained by this method.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来のCVD装置の概要を示す断面図
であり、第2図は本発明の薄膜製造に使用する装
置の一実施例の概要を示す断面図である。
FIG. 1 is a cross-sectional view showing an outline of a conventional CVD apparatus, and FIG. 2 is a cross-sectional view showing an outline of an embodiment of the apparatus used for manufacturing a thin film according to the present invention.

Claims (1)

【特許請求の範囲】[Claims] 1 ヒーターを介して二枚重ねにされた長手方向
に移動可能な帯状の基板と、ガスの供給・排出方
向を前記基板短手方向に略一致させて、前記基板
両側の前記基板長手方向に交互に設けられたガス
供給口およびガス排気口とを有することを特徴と
するCVD法による薄膜製造法。
1 Two strip-shaped substrates stacked together via a heater and movable in the longitudinal direction, and gas supply and discharge directions substantially aligned with the lateral direction of the substrates, and provided alternately in the longitudinal direction of the substrates on both sides of the substrates. 1. A thin film manufacturing method using a CVD method, characterized by having a gas supply port and a gas exhaust port.
JP15893379A 1979-12-06 1979-12-06 Manufacture of thin film Granted JPS5681923A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15893379A JPS5681923A (en) 1979-12-06 1979-12-06 Manufacture of thin film

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15893379A JPS5681923A (en) 1979-12-06 1979-12-06 Manufacture of thin film

Publications (2)

Publication Number Publication Date
JPS5681923A JPS5681923A (en) 1981-07-04
JPS6239534B2 true JPS6239534B2 (en) 1987-08-24

Family

ID=15682505

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15893379A Granted JPS5681923A (en) 1979-12-06 1979-12-06 Manufacture of thin film

Country Status (1)

Country Link
JP (1) JPS5681923A (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5873167A (en) * 1981-10-27 1983-05-02 Konishiroku Photo Ind Co Ltd Thin film solar cell
JPS59167012A (en) * 1983-03-12 1984-09-20 Agency Of Ind Science & Technol Plasma cvd equipment
JPS59167013A (en) * 1983-03-12 1984-09-20 Agency Of Ind Science & Technol Plasma cvd equipment
JPS59219927A (en) * 1983-05-27 1984-12-11 Fuji Electric Corp Res & Dev Ltd Plasma cvd device
JPS60157217A (en) * 1983-07-28 1985-08-17 Fuji Electric Corp Res & Dev Ltd Plasma cvd apparatus
JPH0351971Y2 (en) * 1988-05-12 1991-11-08
US6720576B1 (en) 1992-09-11 2004-04-13 Semiconductor Energy Laboratory Co., Ltd. Plasma processing method and photoelectric conversion device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4935152U (en) * 1972-06-24 1974-03-28
JPS531465A (en) * 1976-06-25 1978-01-09 Matsushita Electric Ind Co Ltd Manufacturer for semiconductor mono crystal thin film and its manufacturing unit

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4942857U (en) * 1972-07-19 1974-04-15

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4935152U (en) * 1972-06-24 1974-03-28
JPS531465A (en) * 1976-06-25 1978-01-09 Matsushita Electric Ind Co Ltd Manufacturer for semiconductor mono crystal thin film and its manufacturing unit

Also Published As

Publication number Publication date
JPS5681923A (en) 1981-07-04

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