JP2562686B2 - Plasma processing device - Google Patents

Plasma processing device

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Publication number
JP2562686B2
JP2562686B2 JP1066525A JP6652589A JP2562686B2 JP 2562686 B2 JP2562686 B2 JP 2562686B2 JP 1066525 A JP1066525 A JP 1066525A JP 6652589 A JP6652589 A JP 6652589A JP 2562686 B2 JP2562686 B2 JP 2562686B2
Authority
JP
Japan
Prior art keywords
substrate
substrates
electrode
plasma
susceptor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP1066525A
Other languages
Japanese (ja)
Other versions
JPH02246111A (en
Inventor
光範 坂間
武 深田
直樹 広瀬
喬 犬島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Energy Laboratory Co Ltd
Original Assignee
Semiconductor Energy Laboratory Co Ltd
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Filing date
Publication date
Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Priority to JP1066525A priority Critical patent/JP2562686B2/en
Publication of JPH02246111A publication Critical patent/JPH02246111A/en
Application granted granted Critical
Publication of JP2562686B2 publication Critical patent/JP2562686B2/en
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Classifications

    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00Energy generation through renewable energy sources
    • Y02E10/50Photovoltaic [PV] energy

Description

【発明の詳細な説明】 (イ)発明の利用分野 本発明は珪素を主成分としたアモルファス及び多結晶
の非単結晶半導体からなる光電変換装置または珪素を主
成分とする非単結晶半導体からなる薄膜電界効果トラン
ジスタ等大型基板上の素子形成に応用することができる
プラズマ処理装置に関するものである。
DETAILED DESCRIPTION OF THE INVENTION (a) Field of Use of the Invention The present invention comprises a photoelectric conversion device composed of amorphous and polycrystalline non-single-crystal semiconductors containing silicon as a main component or a non-single-crystal semiconductor containing silicon as a main component. The present invention relates to a plasma processing apparatus that can be applied to the formation of elements such as thin film field effect transistors on a large substrate.

(ロ)従来の技術 プラズマ化学気相堆積法(以下プラズマCVD法とい
う)により形成される珪素を主成分とした非単結晶半導
体薄膜や酸化珪素、窒化シリコン等の絶縁体薄膜は、太
陽電池、イメージセンサ等の光電変換装置、液晶表示装
置等に使用する薄膜電界効果トランジスタなどの材料と
して巾広く応用されている。これらの電子装置は性質の
異なる複数の薄膜を積層したものから構成され、これら
の装置の大型化および低価格化に伴い、これら積層膜を
工業的に大面積にかつ大量に作製する目的で行われてい
た従来のプラズマ処理装置を以下に示す。
(B) Conventional technology Non-single-crystal semiconductor thin films containing silicon as a main component and insulator thin films such as silicon oxide and silicon nitride formed by plasma enhanced chemical vapor deposition (hereinafter referred to as plasma CVD) are used for solar cells, It is widely applied as a material for photoelectric conversion devices such as image sensors and thin film field effect transistors used for liquid crystal display devices. These electronic devices are composed of a stack of multiple thin films with different properties, and with the increasing size and cost of these devices, these electronic devices are manufactured for the purpose of industrially producing a large area and mass. The conventional plasma processing apparatus that has been known is shown below.

第2図に最も一般的な平行平板電極を用いたプラズマ
CVD装置の概略断面図を示す。
Figure 2 shows the most common plasma using parallel plate electrodes.
The schematic sectional drawing of a CVD apparatus is shown.

この場合、1つの真空予備室(26)と1つの反応室
(23)が示されている。基板(1)は基板支持体(21)
上に設置され、支持体(21)と一緒に仕切り弁(22)を
通じて反応室(23)へ搬送される。該反応室(23)にて
基板(1)はヒーター(24)により加熱され、所定の温
度に達した後、放電電極(25)により反応性気体を分
解、活性化させて基板上に薄膜を形成するものである。
In this case, one vacuum reserve chamber (26) and one reaction chamber (23) are shown. Substrate (1) is substrate support (21)
It is installed above and is conveyed to the reaction chamber (23) together with the support (21) through the sluice valve (22). The substrate (1) is heated by the heater (24) in the reaction chamber (23), and after reaching a predetermined temperature, the reactive gas is decomposed and activated by the discharge electrode (25) to form a thin film on the substrate. To form.

この方式は図より明らかな如く、基板と電極とが平行
であるので、大面積基板上に薄膜を形成する際には電極
面積を大きくする必要があった。
In this method, as is clear from the figure, the substrate and the electrode are parallel to each other, and therefore, it was necessary to increase the electrode area when forming a thin film on a large-area substrate.

さらに一回の薄膜形成工程にて電極面積にほぼ等しい
だけの面積にしか形成できないため、基板の大量処理に
は不十分であった。
Furthermore, since it can be formed only in an area almost equal to the electrode area in one thin film forming step, it is insufficient for large-scale processing of substrates.

これらを解決する1つの方法として、本出願人らによ
るプラズマ気相反応装置(特願昭59−79623)がある。
この装置反応室の概略断面図を第3図に示す。
As one method for solving these problems, there is a plasma vapor phase reactor (Japanese Patent Application No. 59-79623) by the present applicants.
A schematic sectional view of the reaction chamber of this apparatus is shown in FIG.

図面のように、平行平板電極(31)間に被膜形成用基
板(1)複数枚を電極に対し垂直となるように配設し、
一度の処理にて従来の10倍以上の基板処理枚数を達成
し、同時に装置の床面積は従来の装置とほぼ同等であっ
た。上下の放電電極(31)間隔を広げていくに従い、よ
り大きい基板上に被膜を作製することが可能となるが、
実際は上下の電極間隔が広くなるに従い、プラズマ放電
が不安定となるので、通常は電極の一辺の二倍以内にそ
の電極間隔をとっている。このような大面積、大量基板
処理のプラズマ気相反応法にもいくつかの欠点が存在す
る。
As shown in the drawing, a plurality of film-forming substrates (1) are arranged between the parallel plate electrodes (31) so as to be perpendicular to the electrodes,
We achieved more than 10 times the number of substrates to be processed in a single treatment, and at the same time, the floor area of the equipment was almost the same as the conventional equipment. As the distance between the upper and lower discharge electrodes (31) increases, it becomes possible to form a coating on a larger substrate.
Actually, the plasma discharge becomes unstable as the upper and lower electrode intervals become wider, and therefore the electrode interval is usually set within twice the one side of the electrode. There are some drawbacks in the plasma vapor phase reaction method for processing such a large area and a large amount of substrates.

即ち、電極間の距離が相当長いため、基板上に形成さ
れた被膜は特定の製膜条件の場合以外は電極間方向に膜
厚分布を持ってしまう。その様子を第4図(A),
(B),(C),(D)に示す。これは第3図のプラズ
マ気相反応装置にて非単結晶珪素半導体を硝子基板上に
作製した場合の被膜の付き方の概略図を示す。第4図
(A)のIの領域で示すように、反応圧力が高めで高周
波電力の投入電力が低い場合は、第4図(B)に示すよ
うに基板の電極方向の上部及び下部に形成される被膜が
多くなり、このような膜厚分布を有する。この被膜を作
製中、プラズマ反応を行っている反応室内のプラズマ発
光領域は、上下の電極近傍に集まっているのが観察され
た。次に反応圧力が低く、高周波電力の投入電力が高い
場合は、第4図(A)のIIIの領域、第4図(D)のよ
うに基板の電極方向に対し中央部付近に形成される被膜
が多く、このような膜厚分布を有する。
That is, since the distance between the electrodes is considerably long, the coating film formed on the substrate has a film thickness distribution in the direction between the electrodes except under a specific film forming condition. This is shown in Fig. 4 (A),
Shown in (B), (C) and (D). This shows a schematic diagram of how to attach a film when a non-single crystal silicon semiconductor is produced on a glass substrate by the plasma vapor phase reaction apparatus of FIG. As shown in the region I of FIG. 4 (A), when the reaction pressure is high and the input power of the high frequency power is low, it is formed on the upper and lower parts of the substrate in the electrode direction as shown in FIG. 4 (B). The number of coatings formed increases, and the film has such a film thickness distribution. During the production of this film, it was observed that the plasma emission regions in the reaction chamber where the plasma reaction was performed were gathered near the upper and lower electrodes. Next, when the reaction pressure is low and the input power of high-frequency power is high, it is formed in the area III in FIG. 4 (A), near the central portion in the electrode direction of the substrate as shown in FIG. 4 (D). It has many coatings and has such a film thickness distribution.

また狭い範囲ではあるが、第4図(A)の領域IIでは
第4図(C)に示すようなほぼ均一な膜厚分布を得るこ
とが可能であった。
Although it is a narrow range, it was possible to obtain a substantially uniform film thickness distribution as shown in FIG. 4 (C) in the region II of FIG. 4 (A).

このように大面積基板上において不均一な膜厚分布を
有すると同一基板上に構成される各半導体素子の特性、
特に物理的及び電気的特性にひどいばらつきを生じ、大
面積基板上にTFTや光電変換装置を作製しても工業的な
価値はなかった。
In this way, the characteristics of each semiconductor element formed on the same substrate with a non-uniform film thickness distribution on a large-area substrate,
In particular, the physical and electrical characteristics were greatly varied, and there was no industrial value even if a TFT or a photoelectric conversion device was manufactured on a large area substrate.

(ハ)発明の目的 本発明は、前記の従来法の欠点を補うものであり、大
量の大面積基板上に均一な膜厚分布を有する被膜を幅広
い条件下で作製する装置に関する。
(C) Object of the invention The present invention is to supplement the above-mentioned drawbacks of the conventional method, and relates to an apparatus for producing a coating having a uniform film thickness distribution on a large amount of large-area substrates under a wide range of conditions.

(ニ)発明の構成 本発明は前述の問題を解決するプラズマ処理装置に関
するものであり、反応室内壁と放電用電極(3)の間に
一対の電極シールド(4)を設け、前記電極シールド
(4)は、放電用電極(3)間にこの電極とは非平行な
状態で複数の基板(1)を配置するための基板サセプタ
ー(5)とで閉空間を形成し、この基板サセプターは一
方向に可動でき、反応室内の所定の位置に設置された際
に前述の電極シールドと閉空間を形成するものでありま
す。
(D) Configuration of the invention The present invention relates to a plasma processing apparatus which solves the above-mentioned problems, and a pair of electrode shields (4) are provided between the inner wall of the reaction chamber and the discharge electrode (3), and the electrode shield ( 4) forms a closed space between the discharge electrodes (3) and a substrate susceptor (5) for disposing a plurality of substrates (1) in a state not parallel to the electrodes, and the substrate susceptor is It can move in any direction and forms a closed space with the above-mentioned electrode shield when it is installed at a predetermined position in the reaction chamber.

このような構成によって、一対の放電電極及び複数の
基板は、すべて電極シールドと基板サセプターによって
取り囲まれており、プラズマ放電もこれら取り囲まれた
空間より外部にもれず各基板間にも、ほぼ等しい密度の
プラズマ雰囲気が形成され、大面積基板においても均一
性のよい被膜成形が可能となるものである。
With such a configuration, the pair of discharge electrodes and the plurality of substrates are all surrounded by the electrode shield and the substrate susceptor, and the plasma discharge is not leaked to the outside from the enclosed space and the density is almost equal between the substrates. The plasma atmosphere described above is formed, and it becomes possible to form a film with good uniformity even on a large-area substrate.

また、基板サセプターは、一方向に可動可能で、かつ
所定の位置では、電極シールドと閉空間を形成する。こ
のため複数の基板が保持されたサセプターをプラズマ処
理の前後で移動させることで、プラズマ処理を連続的に
行なえるという特徴を持つ。
In addition, the substrate susceptor is movable in one direction and forms a closed space with the electrode shield at a predetermined position. Therefore, by moving the susceptor holding a plurality of substrates before and after the plasma processing, the plasma processing can be continuously performed.

この電極シールドと基板サセプターの構造の一例を第
1図示す。
An example of the structure of the electrode shield and the substrate susceptor is shown in FIG.

第1図(A)においては基板サセプター(5)は図面
の右方向に可動でき、電極シールド(4)とで閉空間を
構成する。
In FIG. 1 (A), the substrate susceptor (5) can be moved to the right in the drawing and forms a closed space together with the electrode shield (4).

この基板サセプター(5)と、電極シールド(4)と
の重なり部分は同図(B)にその拡大概略図が示してあ
り、このような構造をとって基板サセプターは可動し、
電極シールドと閉空間を構成する。
An enlarged schematic view of the overlapping portion of the substrate susceptor (5) and the electrode shield (4) is shown in FIG. 7B, and the substrate susceptor is movable with such a structure,
It forms an electrode shield and a closed space.

また、第5図にその他の電極シールドと基板サセプタ
ーとの組み合わせ例を示す。
Further, FIG. 5 shows an example of a combination of another electrode shield and a substrate susceptor.

本発明においては特にこれらに示した構造のみに限定
されることなく、その他の構造でも本発明の思想を反映
させることが可能である。
The present invention is not particularly limited to the structures shown in these and other structures can also reflect the idea of the present invention.

以下に実施例を示し本発明を説明する。 The present invention will be described below with reference to examples.

『実施例』 本実施例においては、第6図に示すプラズマ気相反応
装置を使用し、硝子基板上に非単結晶半導体被膜を形成
した。同図において、300mm×400mmの大きさのガラス基
板(1)を電極に対して垂直に配置するように基板サセ
プター(5)にセッティングする。本実施例の場合、同
サセプター(5)に硝子基板(1)を10枚装着してある
が、硝子基板(1)の向かい合う間隔が20mm以上であれ
ば放電が再現性よく発生し、より多くの基板上に被膜形
成は可能であるが、基板上の膜厚の均一性を考えるなら
ば、本実施例の場合、10〜15枚程度が良い。尚この基板
間隔は、被膜作製時の圧力等他の要素によって変化する
ので、一に固定することは適当ではない。
Example In this example, the plasma vapor phase reaction apparatus shown in FIG. 6 was used to form a non-single crystal semiconductor film on a glass substrate. In the figure, a glass substrate (1) having a size of 300 mm × 400 mm is set on the substrate susceptor (5) so as to be arranged perpendicularly to the electrodes. In the case of the present embodiment, ten glass substrates (1) are attached to the same susceptor (5), but if the distance between the glass substrates (1) facing each other is 20 mm or more, the discharge occurs reproducibly, and more Although it is possible to form a film on the substrate of No. 3, if the thickness of the film on the substrate is considered to be uniform, about 10 to 15 sheets are preferable in the case of this embodiment. Since this substrate interval changes depending on other factors such as the pressure at the time of forming the coating, it is not appropriate to fix it to one.

また、電極シールド(4)と基板サセプター(5)
は、第1図に示す構造を有しており、これら電極シール
ド,基板サセプターは金属材料であるニッケル,ステン
レス,アルミニュームやセラミックス等の表面に導電材
料を形成した物が使用可能である。本実施例ではこれら
を10mmφのパンチング穴加工がなされたアルミニューム
材で構成した。このパンチングによる穴は反応性気体の
流れをよくする為と初期排気の時間短縮の為に設けたも
のであるがこのパンチングの穴よりプラズマが漏れるこ
とは無かった。
Also, the electrode shield (4) and the substrate susceptor (5)
Has the structure shown in FIG. 1, and these electrode shields and substrate susceptors can be made of metal such as nickel, stainless steel, aluminum, or ceramics having a conductive material formed on the surface thereof. In this embodiment, these are made of an aluminum material having a punching hole of 10 mmφ. This punching hole was provided to improve the flow of the reactive gas and to shorten the initial exhaust time, but the plasma did not leak from the punching hole.

さらに本実施例では、電極シールドと基板サセプター
を接地し、より均一なプラズマが放電電極間のみに発生
するようにした。これにより各基板は、より均一なプラ
ズマ雰囲気下に置かれることになった。
Further, in this embodiment, the electrode shield and the substrate susceptor are grounded so that more uniform plasma is generated only between the discharge electrodes. As a result, each substrate was placed in a more uniform plasma atmosphere.

この硝子基板がセットされたサセプター(5)を予備
室(62)よりプラズマ反応室に入れ、真空排気を行った
後、ゲイト弁(63)を開き、搬送機構(図示せず)によ
り第1の反応室(64)へ移動した後、図では描けないの
で省略してあるが、第6図の紙面と平行で手前側と奥側
にある基板加熱用ヒーターにより被膜形成温度である20
0〜300℃程度にまで加熱できる。
The susceptor (5) on which the glass substrate is set is put into the plasma reaction chamber from the preliminary chamber (62), and after vacuum evacuation, the gate valve (63) is opened and the first transfer mechanism (not shown) is used. After moving to the reaction chamber (64), it is omitted because it cannot be drawn in the figure, but the film forming temperature is set by the substrate heating heaters on the front side and the back side which are parallel to the paper surface of FIG.
It can be heated up to about 0-300 ℃.

この状態で反応室(64)内にシランガスを50SCCMの流
量で導入し排気系のコンダクタンスを制御した反応室内
圧力を0.01〜0.1torrに保持できる。
In this state, silane gas was introduced into the reaction chamber (64) at a flow rate of 50 SCCM, and the pressure in the reaction chamber in which the conductance of the exhaust system was controlled can be maintained at 0.01 to 0.1 torr.

次に、上下の平行平板電極(61)間に13.56MHzの高周
波電力を印加し、プラズマ放電は上下の電極シールド
(4)及び基板支持サセプター(5)の側面にて構成さ
れる空間中に閉じ込められ、反応室(64)の内壁まで到
達はしていない。よって形成される被膜も、前記の空間
内部にしか形成されず、反応室内壁をクリーニングする
必要がないか、またはクリーニングの回数を非常に少な
くすることが可能となっている。
Next, high-frequency power of 13.56MHz is applied between the upper and lower parallel plate electrodes (61), and the plasma discharge is confined in the space defined by the side surfaces of the upper and lower electrode shields (4) and substrate support susceptor (5). Therefore, it has not reached the inner wall of the reaction chamber (64). Therefore, the coating film formed is formed only in the space described above, and it is not necessary to clean the inner wall of the reaction chamber, or the number of times of cleaning can be extremely reduced.

本発明の装置を用いて、300mm×400mmの基板上にP,I,
N構造を有する太陽電池(素子面積1.05cm2)を500個作
製した。その特性を以下の表1に示す。
Using the device of the present invention, P, I, on a 300 mm × 400 mm substrate
500 solar cells having an N structure (device area 1.05 cm 2 ) were prepared. The characteristics are shown in Table 1 below.

このように、光電変換効率のばらつきが非常に小さく
なっている。これは特にPIN型太陽電池のI型半導体層
の膜厚のばらつきが非常に少ないことと深い関係がある
ためである。
Thus, the variation in photoelectric conversion efficiency is extremely small. This is because it is closely related to the fact that the variation in the film thickness of the I-type semiconductor layer of the PIN solar cell is very small.

(ホ)効果 本発明の構成によりプラズマ発生空間を基板が置かれ
た電極間のみに限定でき、より均一なプラズマを発生で
きた。
(E) Effect With the configuration of the present invention, the plasma generation space can be limited to only between the electrodes on which the substrate is placed, and more uniform plasma can be generated.

また、このようなプラズマ発生空間を限定でる基板サ
セプターは移動可能であるため、大量の基板を連続的に
処理できた。
Further, since the substrate susceptor that limits the plasma generation space is movable, a large amount of substrates can be continuously processed.

また、本発明の装置を用いて被膜を作製すると、大面
積基板上に非常に均一な被膜を形成することが可能とな
る。これにより大面積基板よりとり出せる素子数が増加
し、さらにその特性も均一なものが得られるようにな
る。
Moreover, when a film is produced using the apparatus of the present invention, it becomes possible to form a very uniform film on a large area substrate. As a result, the number of elements that can be taken out from the large-area substrate is increased, and the characteristics can be made uniform.

また大面積の素子、例えば太陽電池等は、基板上の膜
質が均一となるので、全体として特性の向上が得られ
る。
Further, in a large-area element such as a solar cell, the quality of the film on the substrate is uniform, so that the characteristics can be improved as a whole.

【図面の簡単な説明】[Brief description of drawings]

第1図及び第5図は本発明の電極シールドと基板サセプ
ターの組み合わせの様子を示す。 第2図は従来のプラズマCVD装置を示す。 第3図は本発明で用いたプラズマCVD装置を示す。 第4図は従来法により形成された結果を示す。 第6図は本発明のプラズマ処理装置。 1……基板 3……電極 4……電極シールド 5……基板サセプター
1 and 5 show the combination of the electrode shield and the substrate susceptor of the present invention. FIG. 2 shows a conventional plasma CVD apparatus. FIG. 3 shows the plasma CVD apparatus used in the present invention. FIG. 4 shows the result formed by the conventional method. FIG. 6 shows the plasma processing apparatus of the present invention. 1 ... Substrate 3 ... Electrode 4 ... Electrode shield 5 ... Substrate susceptor

───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 昭60−111415(JP,A) 特開 昭60−213020(JP,A) 特開 昭63−237409(JP,A) ─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-60-111415 (JP, A) JP-A-60-213020 (JP, A) JP-A-63-237409 (JP, A)

Claims (3)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】減圧状態に保持可能な反応室内の一対の平
行平板電極間に複数の基板の表面を前記電極とは平行で
ない位置に配置し、前記複数の基板上にプラズマ処理を
行うプラズマ処理装置であって、前記反応室の内壁と前
記電極との間に設けられた一対の電極シールドと、前記
複数の基板を保持するサセプターとを重ね合わせること
により、閉空間を構成し、前記閉空間内には前記電極と
前記複数の基板が設けられており、前記電極によって発
生されるプラズマは前記閉空間内のみに存在し、前記サ
セプターは一方向に引き出し可能なことを特徴とするプ
ラズマ処理装置。
1. A plasma treatment in which the surfaces of a plurality of substrates are arranged in a position not parallel to the electrodes between a pair of parallel plate electrodes in a reaction chamber that can be maintained under reduced pressure, and plasma treatment is performed on the plurality of substrates. An apparatus, wherein a pair of electrode shields provided between the inner wall of the reaction chamber and the electrode and a susceptor holding the plurality of substrates are superposed to form a closed space, and the closed space is formed. The plasma processing apparatus is characterized in that the electrode and the plurality of substrates are provided inside, the plasma generated by the electrode exists only in the closed space, and the susceptor can be drawn out in one direction. .
【請求項2】減圧状態に保持可能な反応室内の一対の平
行平板電極間に複数の基板の表面を前記電極とは平行で
ない位置に配置し、前記複数の基板上にプラズマ処理を
行なうプラズマ処理装置であって、前記複数の基板を保
持するサセプターを所定の方向より移動させて所定の位
置に配置することにより、前記反応室の内壁と前記電極
の間に設けられた一対の電極シールドと、前記サセプタ
ーとを重ね合わせることによって、プラズマを閉じ込め
る空間を構成するプラズマ処理装置。
2. A plasma treatment in which the surfaces of a plurality of substrates are arranged in a position not parallel to the electrodes between a pair of parallel plate electrodes in a reaction chamber that can be kept under a reduced pressure, and plasma treatment is performed on the plurality of substrates. A device, wherein a pair of electrode shields provided between the inner wall of the reaction chamber and the electrodes by arranging the susceptor holding the plurality of substrates in a predetermined position by moving the susceptor from a predetermined direction, A plasma processing apparatus in which a space for confining plasma is formed by overlapping the susceptor.
【請求項3】特許請求の範囲第1項および第2項におい
て、前記電極シールドと前記サセプターは導電性表面を
有する材料よりなり、それぞれは反応室と同様に接地さ
れていることを特徴とするプラズマ処理装置。
3. The electrode shield and the susceptor according to claims 1 and 2 are made of a material having a conductive surface, and each is grounded like the reaction chamber. Plasma processing equipment.
JP1066525A 1989-03-18 1989-03-18 Plasma processing device Expired - Fee Related JP2562686B2 (en)

Priority Applications (1)

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JP1066525A JP2562686B2 (en) 1989-03-18 1989-03-18 Plasma processing device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1066525A JP2562686B2 (en) 1989-03-18 1989-03-18 Plasma processing device

Publications (2)

Publication Number Publication Date
JPH02246111A JPH02246111A (en) 1990-10-01
JP2562686B2 true JP2562686B2 (en) 1996-12-11

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Country Link
JP (1) JP2562686B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2652292B2 (en) * 1991-11-22 1997-09-10 株式会社半導体エネルギー研究所 Plasma processing equipment
JPH07122502A (en) * 1993-10-21 1995-05-12 Nec Corp Plasma machining device

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60111415A (en) * 1983-11-22 1985-06-17 Semiconductor Energy Lab Co Ltd Plasmic vapor-phase reaction equipment
JPS60213020A (en) * 1984-04-07 1985-10-25 Konishiroku Photo Ind Co Ltd Glow discharge decomposition device
JPS63237409A (en) * 1987-03-25 1988-10-03 Shimadzu Corp Plasma cvd system

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JPH02246111A (en) 1990-10-01

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