JPS6238744B2 - - Google Patents
Info
- Publication number
- JPS6238744B2 JPS6238744B2 JP57160122A JP16012282A JPS6238744B2 JP S6238744 B2 JPS6238744 B2 JP S6238744B2 JP 57160122 A JP57160122 A JP 57160122A JP 16012282 A JP16012282 A JP 16012282A JP S6238744 B2 JPS6238744 B2 JP S6238744B2
- Authority
- JP
- Japan
- Prior art keywords
- tlb
- error
- parity
- protection key
- parity check
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000000034 method Methods 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000010365 information processing Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1076—Parity data used in redundant arrays of independent storages, e.g. in RAID systems
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は情報処理システムにおけるTLB（テ
ーブル・ルツクアサイド・バツフア）中に、主記
憶の保護を行なうための保護キーを登録して使用
する場合の、該保護キーのパリテイチエツクに関
する。[Detailed Description of the Invention] [Technical Field of the Invention] The present invention provides a method for registering and using a protection key for protecting main memory in a TLB (table lookaside buffer) in an information processing system. Regarding the parity check of the protection key.
保護キーは、TLBに登録しても使用されない
（又は使用しない）場合があるため、従来よりパ
リテイチエツクはTLBに登録する前には行われ
ず、TLBから読出したときに行なつている。そ
のため、主記憶（MS）から送られて来たときに
エラーがあつたのか、TLBに登録した後でエラ
ーが発生したのかを区別することができない。し
かし、主記憶から送られて来た時のエラーは、
MSキーエラーとして、またTLB内でのエラーは
TLBエラーとして別々の処理をしなくてはいけ
ない。
Even if a protection key is registered in the TLB, it may not be used (or may not be used), so conventionally parity checks have not been performed before being registered in the TLB, but have been performed when reading from the TLB. Therefore, it is not possible to distinguish whether an error occurred when the data was sent from main memory (MS) or after it was registered in the TLB. However, the error when sent from main memory is
As an MS key error and within the TLB, the error is
It must be handled separately as a TLB error.
本発明はチエツクのための時間遅れを伴なわ
ず、かつMSエラーとTLBエラーとを区別するこ
とを目的とする。
The purpose of the present invention is to distinguish between MS errors and TLB errors without any time delay for checking.
図は本発明の一実施例回路ブロツク図であり、
１はキー部用のMS読出しレジスタ、１′はキー部
に対するパリテイＰ用のMS読出しレジスタ、２
はレジスタ１，１′の内容全体に対するパリテイ
を発生する回路、３，３′，４はTLBへの書込み
レジスタ、５はTLB、６，６′，７はTLB読出し
レジスタ、８はレジスタ６，６′に対するパリテ
イチエツク回路、９はレジスタ６，６′及び７の
全体に対するパリテイチエツク回路、１０は否定
回路、１１はAND回路である。
The figure is a circuit block diagram of an embodiment of the present invention.
1 is the MS read register for the key part, 1' is the MS read register for parity P for the key part, 2
is a circuit that generates parity for the entire contents of registers 1 and 1', 3, 3', and 4 are registers for writing to TLB, 5 is TLB, 6, 6', and 7 are TLB read registers, and 8 is registers 6 and 6. 9 is a parity check circuit for all registers 6, 6' and 7, 10 is a NOT circuit, and 11 is an AND circuit.
パリテイチエツク回路８でエラーが検出された
だけでは、そのエラーがTLBへの書込みの前に
生じたか、後に生じたかは判らない。そのときも
しも、パリテイチエツク回路９でエラーが検出さ
れなければ、前記エラーはTLBへの書込み前に
MSでエラーを生じていたものと見做される。ま
たパリテイチエツク回路９でもエラーが検出され
れば、前記エラーはTLB登録後に生じたものと
見做される。 If an error is detected by the parity check circuit 8, it cannot be determined whether the error occurred before or after writing to the TLB. At that time, if no error is detected by the parity check circuit 9, the error will be detected before writing to the TLB.
It is assumed that an error occurred in MS. If an error is also detected by the parity check circuit 9, it is assumed that the error occurred after TLB registration.
本発明によれば、TLB読出し時に２種のチエ
ツクをすることにより、MSエラーとTLBエラー
の区別が可能となり、適切なエラー処理を行なう
ことが可能となる。
According to the present invention, by performing two types of checks when reading the TLB, it is possible to distinguish between MS errors and TLB errors, and it is possible to perform appropriate error processing.
図は本発明の一実施例回路ブロツク図であり、
２はパリテイ発生回路、８，９はプリテイチエツ
ク回路、５はTLBである。
The figure is a circuit block diagram of an embodiment of the present invention.
2 is a parity generation circuit, 8 and 9 are parity check circuits, and 5 is a TLB.
Claims (1)
用する方式において、 TLBに保護キーを登録するときに、保護キー
とそのパリテイを含んだ全ビツトに対してパリテ
イジエネレートした新しいパリテイを付加して
TLBに登録し、 TLBから保護キーを読出すときに保護キーと
そのパリテイとにもとづく第１のパリテイチエツ
クと、上記全ビツトとその新しいパリテイとにも
とづく第２のパリテイチエツクとを併行して行な
い、上記第２のパリテイチエツクによりエラーが
検出されたときTLBエラーとして出力し、上記
第２のパリテイチエツクではエラーが検出されず
上記第１のパリテイチエツクでのみエラーが検出
されたとき主記憶エラーとして出力するよう構成
したことを特徴とするTLBにおける保護キーの
チエツク方式。[Claims] 1. In a method in which a protection key stored in the main memory is registered in the TLB and used, when the protection key is registered in the TLB, a parity generator is applied to all bits including the protection key and its parity. Add a new rated parity
When registering in the TLB and reading the protection key from the TLB, a first parity check based on the protection key and its parity is performed in parallel with a second parity check based on all the above bits and the new parity. If an error is detected by the second parity check, it is output as a TLB error, and if no error is detected by the second parity check, but an error is detected only by the first parity check. A method for checking a protection key in a TLB, characterized in that it is configured to output a main memory error when a main memory error occurs.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57160122A JPS5968898A (en) | 1982-09-14 | 1982-09-14 | Check system of protection key in tlb |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57160122A JPS5968898A (en) | 1982-09-14 | 1982-09-14 | Check system of protection key in tlb |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5968898A JPS5968898A (en) | 1984-04-18 |
| JPS6238744B2 true JPS6238744B2 (en) | 1987-08-19 |
Family
ID=15708338
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57160122A Granted JPS5968898A (en) | 1982-09-14 | 1982-09-14 | Check system of protection key in tlb |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5968898A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2559398B2 (en) * | 1987-03-18 | 1996-12-04 | 株式会社日立製作所 | Virtual computer system |
| JPH04184649A (en) * | 1990-11-20 | 1992-07-01 | Fujitsu Ltd | Information processor |
| JP2007032811A (en) * | 2005-07-29 | 2007-02-08 | Fujinon Corp | Camera platform system |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5175355A (en) * | 1974-12-25 | 1976-06-29 | Fujitsu Ltd | |
| JPS55135396A (en) * | 1979-04-05 | 1980-10-22 | Mitsubishi Electric Corp | Error correction/detection system of memory unit |
-
1982
- 1982-09-14 JP JP57160122A patent/JPS5968898A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5175355A (en) * | 1974-12-25 | 1976-06-29 | Fujitsu Ltd | |
| JPS55135396A (en) * | 1979-04-05 | 1980-10-22 | Mitsubishi Electric Corp | Error correction/detection system of memory unit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5968898A (en) | 1984-04-18 |
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