JPH04184649A - Information processor - Google Patents

Abstract

PURPOSE:To judge an error occurrence place by checking data from a buffer memory by an error detecting means in a cache controller while checking the data by a read buffer in a processor. CONSTITUTION:The cache controller 3 decides whether or not data in the address of an incorporated read bit decision mechanism 32 is inputted to the buffer memory by the read bit decision mechanism 32 and sets the data from the memory 4 in a read buffer 51 incorporated in the processor 5 in the case of read bits to make a parity check. If a parity error is caused, the parity status is set in a read buffer parity status register 53. When a register 53 is set here and a buffer memory parity error status register 35 in the controller 3 is also set, it is judged that the error is caused by the accident of a cache device, but when only the register 35 is set, it is judged that the accident occurs to a storage 1.

Description

[Detailed description of the invention] [Table of contents] Overview Industrial field of application Prior art (Figure 8) Problems to be solved by the invention Means for solving the problems (Figure 1) Working examples (Figure 2) ) Effects of the Invention [Summary] The present invention relates to an information processing device, and when a processor detects an abnormality in read data, whether it is based on an abnormality in the cache or a cache device having a system storage, a cache controller, and a buffer memory. and an information processing device comprising a processor equipped with a means for checking input data, in which a check means for checking data output from a buffer memory is provided in the cache controller, and a check means for checking data output from the buffer memory of the cache device is provided. The data is checked by the processor's check means and the cache controller's check means, and if there is an error in both, it is determined that there is an error in the data from the buffer memory of the cache device, and the data is read from the system storage. The system is configured such that the processor checks the data by a checking means of the processor, and when an error is detected, it is determined that there is an error in the data from the system storage.

[Industrial Field of Application] The present invention relates to an information processing apparatus using a cache device, and more particularly to an information processing apparatus having means for accurately locating the location where an error occurs when an error occurs within the information processing apparatus.

[Prior Art] In recent years, cache devices have been used to speed up data processing. Providing such a cache device increases the overall amount of hardware, so if an error occurs within the device, the error location must be quickly and accurately corrected for system reliability, maintainability, and availability. It is necessary to separate it.

An information processing apparatus having a conventional error occurrence point detection means will be explained with reference to FIG.

In FIG. 8, 11 is a system storage (main memory,
SS), 12 is an interface, 13 is a cache controller, and 14 is a buffer memory (BM), and the cache controller 13 and buffer memory 14 constitute a cache device. The cache controller 13 is
A read miss control mechanism 81' is provided for reading data from the system storage 11 when data to be read is not input to the buffer memory 14, that is, when a read miss occurs.

15 is a processor, which includes a read buffer 51 for setting data read from each memory, a parity check (PC) section 52 for checking the data set by the read buffer 51, and a parity check (PC) section 52 for checking whether or not there is a parity error. The RBPE status register (Read Buffer) is a register that indicates the status.
Parity Error 5tatus Regi
ster) 53.

Conventionally, in the information processing apparatus configured as described above, the processor 15 searches the Bacher memory 14 via the cache controller 18 in order to obtain desired data.

When data to be read is input to the buffer memory 14, that is, when a read hit occurs, the processor 15 reads the data from the buffer memory 14, receives it in the read buffer 51, and checks it in the parity check section 52.

If there is a parity error, a flag is set in the RBPE status register 53 to indicate that this data is in error.

Further, when the data to be read is not input to the buffer memory 4, that is, when a read miss occurs, the corresponding data is read from the system storage 11 by a mishit control mechanism 31' provided in the cache controller 18, and the read miss control mechanism 3
1' to the read buffer 51.

Data from the system storage 11 set in the read buffer 51 in the processor 15 undergoes a parity check in the parity check section 52.

If there is a parity error, a flag is set in the RBPE status register 58 to indicate that this data is in error.

[Problems to be Solved by the Invention] However, in the conventional method, both the data output from the buffer memory 4 and the data output from the system storage 11 are stored in the read buffer 5 provided in the processor 15.
1 and undergoes a parity check only here, so even if an error is detected in the read buffer 51, the processor 15 will check whether the data read from the buffer memory 14 is an error or whether the data transferred from the system storage 11 itself is an error. It was not possible to determine exactly where the error occurred.

Therefore, an object of the present invention is to provide an information processing apparatus that uses a cache device and has means for accurately determining whether an error occurs in data read by a processor, in the cache device or in the system storage. It is something.

[Means for Solving the Problems] In order to achieve the above object, the present invention provides error detection means for the data in the buffer memory in the cache controller, and transfers the data from the buffer memory into the processor.
The location where the error has occurred is determined by checking the error detection means in the cache controller at the same time as checking the error detection means in the cache controller.

FIG. 1 is a diagram illustrating the inventive principle of the present invention.

1st rl! In J, 1 is the system storage (SS
), 2 is an interface, 3 is a cache controller, 4 is a buffer memory (BM), and 5 is a processor. In the present invention, the cache controller 3 is equipped with a BM buffer 33.

51 is a read buffer (RB
).

In the present invention, when the processor 5 reads desired data, it first searches the buffer memory 4 via the cache controller 8.

When desired data is input to the buffer memory 4,
That is, when a read hit occurs, this data is read, and the data from the buffer memory 4 is set in the read buffer 51 in the processor 5, and at the same time, it is also set in the BM buffer 33 in the cache controller s. Therefore, when an error is detected in the read buffer 51 in the processor 5, the error in the read buffer 51 in the cache controller s is detected simultaneously.
When an error is also detected from the M buffer 38, it is determined that there is an error in the data from the cache device.

On the other hand, when desired data is not input to the buffer memory 4, that is, when a read miss occurs, the cache controller 8 reads data from the system storage 1. In this case, the cache controller 3 stores this data in the 8M buffer 31. Check by setting it only in the read buffer 51 in the processor 5 instead of setting it in the read buffer 51 in the processor 5. As a result, if there is an error in data from the system storage 1, the error is detected only within the processor 5.

[Operation] By configuring as in the present invention, in an information processing device using a cache device, when there is an error in the data read by the processor, when the error is detected from both the processor and the cache device, the error is detected from the cache device. It can be determined that an error has occurred in the data, and when an error is detected only from the processor, it can be determined that an error has occurred in the data from the system storage.

[Example] An embodiment of the present invention will be explained with reference to FIG.

FIG. 2 is an explanatory diagram of the configuration of an embodiment of the present invention.

In Fig. 2, the same symbols as in Fig. 1 indicate the same parts, and 1
2 is a system storage (main memory, SS), 2 is an interface, 8 is a cache controller, 4 is a buffer memory (BM), and 5 is a processor, and the cache controller 8 and buffer memory 4 constitute a cache device.

In addition to a read miss control mechanism 81 for reading data from the system storage l in the case of a read miss, the cache controller 8 includes:
Read hit determination mechanism 82, BM buffer 38, parity check unit S4.8 MPE status register (Bu
The memory parity error status register) 35 is provided.

The read hit determination mechanism 82 determines, based on the read address output from the processor 5, whether data at the address has been input to the buffer memory 4. If there is a hit, the read hit determination mechanism 82 sends a hit signal to the processor 5. If there is a mishit, a read mishit signal is output to the processor 5 and sent to the read mishit control mechanism 31.

The BM buffer 38 inputs read data from the buffer memory 4 and performs a parity check in the parity check unit 84.The BMPE status register 35 sets a 1-bit flag when an error is found as a result of the check in the parity check unit 34. It is used to display errors. In addition, in FIG. 2, 86.38 is a receiver, and 87 is a driver.

On the other hand, the processor 5 has a read buffer 51 in which read data is set as in the conventional example, and a parity check section 52 performs a parity check, and an RBPE status register 53 that displays an error when an error is detected as a result of the parity check. Be equipped.

In one embodiment of the present invention, when processor 5 requires data, processor 5 outputs a read address to cache controller 8.

In the cache controller 8, the read hit determination mechanism 3
2 determines that data at this address is input to the buffer memory 4. If it is determined that there is a read hit, the corresponding data from the buffer memory 4 is set in the read buffer 51 of the processor 5, a parity check is performed, and if the result is an error, it is set in the RBPE status register 53.

Further, in this case, the corresponding data from the buffer memory 4 is also set in the 8M buffer 33 in the cache controller 3 at the same time, and a parity check is performed by the parity check section 84. If an error is detected as a result, the BM
It is set in the PE status register 85.

Therefore, if the RBPE status register 53 is set and the BMPE status register 85 is also set, that is, if flags are set in both status registers, it can be determined that there is an error in the data from the cache device. I can do it.

On the other hand, when the data at the address read accessed by the processor 5 has not been input to the buffer memory 4, that is, when the read hit determination mechanism 32 determines that there is a read miss, the read hit determination mechanism 82 sends a read miss signal to the read mishit control mechanism 31. input.

As a result, the cache controller 3 reads the data at the corresponding address from the system storage 1 and sets it in the read buffer 51 of the processor 5 via the read miss control mechanism 81. read buffer 5
The data set to 1 is subjected to a parity check in the parity check section 52, and if an error is detected as a result of the check, it is set in the RBPE status register 53 and an error is displayed.

Since the data read from the system storage 1 is not input to the 8M buffer 3S in the cache controller 3, the BMPE status register 35 is not set in this case.

Therefore, when a read miss occurs, when the RBPE status register 53 is set and the BMPE status register 35 is not set, it can be determined that there is an error in the data from the system storage 1.

[Effects of the Invention] According to the present invention, in an information processing device using a cache device, when an error is detected in the data input to the processor, whether the error is an error in the data read from the cache device or from the system storage is detected. It is possible to easily recognize the location of the error, whether it is an error in the read data. Therefore, by accurately determining which device should be replaced at the location where the error has occurred, the reliability and maintainability of the system are increased.

In particular, if the buffer memory is determined to be faulty, it is possible to disconnect only the cache device and continue access using the system storage, which can be expected to have a significant effect of increasing system availability.

[Brief explanation of the drawing]

FIG. 1 is an illustration of the inventive principle of the present invention, FIG. 2 is an explanatory diagram of the configuration of an embodiment of the invention, and FIG. 3 is an explanatory diagram of the configuration of a conventional example. DESCRIPTION OF SYMBOLS 1... Main memory (SS), 2... Interface, 3... Cache controller, 4... Buffer memory (BM), 5... Processor, 31... Read miss control mechanism, 82 ... Read hit determination mechanism, 38... BM buffer, 84... Parity check section, 35... BMPE status register, 51... Read buffer, 52... Parity check section, 58... RBPE status register. Patent Applicant: Fujitsu Ltd. Representative Patent Attorney Akira Yamatani Sakae Invention Stainless Steel Diagram 1

Claims (1)

[Claims] Information comprising a system storage (1), a cache device having a cache controller (3) and a buffer memory (4), and a processor (5) having input data checking means (51). In the processing device, a buffer memory (
A checking means (33) is provided for checking the data output from the cache device (4), and a checking means (33) of the processor (5) is provided for checking the data read from the buffer memory (4) of the cache device.
51) and the checking means (33) of the cache controller (3), and if there is an error in both, it is determined that there is an error in the data from the buffer memory (4) of the cache device, and the system storage (1) The data read from the system storage (1) is checked by the checking means (51) of the processor (5), and when an error is detected, it is determined that there is an error in the data from the system storage (1). Information processing device.