JPH0264836A - Rom parity check method - Google Patents

Abstract

PURPOSE:To accurately execute parity check even if ROM different in capacity is mounted by executing parity check through the sequential use of plural parity check methods. CONSTITUTION:A system main body 1 consists of a processor 1a, RON1b, RON1c and I/O (interface)1d, and the plural parity check methods PCi corresponding to different ROM capacities are prepared in the processor 1a. The processor 1a sequentially executes plural parity check methods PCi at the time of parity-checking data in ROM and judges it to be good when the total sum of bits by either parity check method agrees with a prescribed value, and judges to be no good when they do not agree so as to generate an alarm. Thus, parity check can accurately be executed when ROMs different in capacity are mounted.

Description

[Detailed description of the invention] <Industrial application field> The present invention relates to a ROM parity check method.

In particular, data in ROM is divided into blocks of a predetermined length,
The present invention relates to a ROM parity check method that performs a parity check by adding a parity bit to each block.

Prior Art> Very high reliability is required for data in a ROM in a computer system such as a CNC. Therefore, the system constantly monitors the inside of the ROM, and when the data changes from the original data or a defect in the ROM is discovered,
The alarm lamp is lit and the operation is stopped immediately to prevent dangers such as runaway.

One method of monitoring within such a ROM is a horizontal parity check (sum check). Figure 4 shows the thumb check method for data in the ROM, and .
1”, ○ means “0”, bits arranged vertically
The code is represented by 8 bits from 1 to bit 8 or 0 (1 or O). 12 check is R
The data in the OM is divided horizontally into blocks of a predetermined length according to the ROM capacity, and a parity pick is applied to each block.
-FRB is added, and the total focus of rlJ is set to a predetermined value (for example,
The value of the parity bit is determined to be an even or odd number, and the system performs a parity check to see if the sum of bits in the block including the parity bit matches a predetermined value when the power is turned on. Turn on the alarm lamp and stop the operation.

<Problems to be Solved by the Invention> Incidentally, in order to improve the performance of the CNC, there are cases where it is desired to remove the current ROM and replace it with a ROM with a larger capacity. For example, pudding 1 to plate PNT as shown in FIG.
) The installed ROM12 (not limited to one) is
Installation is compatible with ROMs of different capacities, and the current RO
It is possible to remove M and replace it with another ROM with a larger capacity. A microcomputer system is built on the printed board PNT shown in Figure 5, and the CPU
1.1, ROM12, RAM13. l1014 is implemented. In such cases, conventionally, only a parity check method has been provided for one type of ROM in one system. In other words, because the current system only has a parity check method for a block length that corresponds to the current ROM capacity, it is not possible to correctly perform a parity check for a ROM with a different capacity than the current ROM, and therefore the capacity There was a problem that the ROM could not be replaced with a different ROM.

From the above, it is an object of the present invention to provide a ROM parity check method that can correctly perform a parity check even when ROMs with different capacities are installed.

Means for Solving the Problems> An object of the present invention is to prepare a plurality of parity check methods according to the ROM capacity, and to perform a parity check of the data in the ROM by using the plurality of parity check methods.
This is accomplished by performing a parity check using the following terms:

Function> Use or reduce the number of parity check methods according to the ROM capacity, perform the plurality of parity check methods in sequence when parity checking the data in the ROM, and check the parity of any of the plurality of parity check methods. If the bit sum determined by the checking method matches the predetermined value, it is determined to be good; if it does not match by any of the parity checking methods, it is determined to be defective and an alarm is generated.

<Example> FIG. 1 is a block diagram of an apparatus implementing the invention.

Reference numeral 1 denotes a system body having a microcombicoater configuration, 2 a keyboard, and 3 a display device.

The system main body includes a processor LA and an RO with a predetermined capacity.
M1 b, RAMI c, l10 (interface)]
d, and these are mounted on one pudding board.

Processor 1a will have another RO with a different capacity in the future.
Anticipating that M will be implemented, multiple parity check methods PCi (i=1.21 ・
・n) is available.

FIG. 2 is an explanatory diagram of the parity check method PCi according to ROMs with different capacities, FIG. 2(a) is an explanatory diagram of the parity check method PCI for ROM capacities of IM (megabits), and FIG. 2(b) is an explanatory diagram of a parity check method PC2 with a ROM capacity of 2M, and FIG. 2(C) is an explanatory diagram of a parity check method PCn with a ROM capacity of nM (megabits).

In Fig. 2, a part of the data in the ROM is shown, ・ means "1", 0 means "0", and bits 1- to bj, t8 arranged in the vertical direction are shown.・Or O(
The code is represented by 8 bits (1 or O).

When the ROM capacity is IM, the data in the ROM is horizontally divided into a predetermined block length BLI (
A parity bit PRBI is added to each block, and the total bit sum of "1" in each block including the parity bit PRBI is set to a predetermined value (for example, "
The value of the parity bit is determined so that the sum of 1' is an even number. That is, the first parity check method PCI
performs a parity check for each block length BLI'.

When the ROM capacity is 2M, the data in the 2M ROM is horizontally divided into a predetermined block length B according to the 2M capacity.
L2 (Fig. 2(b)), a parity bit FRB2 is added to each block, and a parity bit PRB2 is added to each block.
The value of the parity bit is determined so that the sum of bits of "1" in block units including "1" is an even number. Therefore, the second
The parity check method PC2 performs a parity check for each block length BL2'.

When the ROM capacity is nM (n=4.8.16...), the data in the nM ROM is horizontally divided into a predetermined block length BLn (Fig. 2 (C)) according to the nM capacity. A parity bit PRBn is added to each block, and "1" is added to each block including the parity bit PRBn.
The value of the parity bit is determined so that the bit sum of `` is an even number. That is, the nth parity check method PC
n is for performing a parity check every block length BLn'.

FIG. 3 is a flowchart of the process of the ROM parity check method of the present invention. The ROM parity check process of the present invention will be explained below along the flowchart of FIG.

When the operator starts up the system through a predetermined operation using the keyboard 2, the processor 1a performs a parity check using the first parity check method PCI among the prepared parity check methods. That is, ROM
The data within is divided horizontally into blocks of 1M block length BLI', a parity check is performed, and it is determined whether the bit sum is an even number (steps 101 and 102). As a result of judgment, if it is an even number, it is good.
Further, the data in the ROM 1b is read while continuing the parity check using the first parity check method PCI.

On the other hand, if the result of the determination in step 102 is an odd number, the processor 1a performs a parity check in the ROM 1b using the second parity check method PC2. That is, R
The data in OM1b is horizontally divided into block length BL of 2M.
A parity check is performed for every 2', and it is determined whether the total bit sum is an even number (step 103).
and step 104). As a result of the judgment, if the number is even, it is acceptable, and the data in the ROM 1b is read while continuing the parity check using the second parity check method PC2.

On the other hand, if the result of the determination in step 104 is an odd number, the processor 1a performs a parity check in the ROM 1b using the nth parity check method PCn. That is, R
The data in OM1b is horizontally divided into block lengths BLn' of nM bits, a parity check is performed, and it is determined whether the bit sum is an even number (steps 105 and 106). As a result of the judgment, if the number is even, it is acceptable, and the data in the ROM 1b is read while continuing the parity check using the n-th parity check method PCn.

On the other hand, if the result of the judgment in step 106 is an odd number, in other words, the prepared parity check method PCi (i
=1.2...n) are all odd numbers, ROM1b
It is assumed that the display device 3 is defective, the alarm lamp of the display device 3 is turned on, the operation is stopped, and the ROM parity check process is ended.

<Effects of the Invention> According to the present invention, a plurality of parity check methods are prepared according to the ROM capacity, and the plurality of parity check methods are sequentially performed when checking the parity of data in the ROM, and the plurality of parity check lag methods are performed in sequence. If the sum of bits by any of the parity check methods matches the predetermined value, it is determined to be good, and if it does not match by any of the parity check methods, it is determined to be defective and an alarm is generated. Even if different ROMs are installed, parity check can be performed correctly.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an apparatus implementing the present invention, FIG. 2 is an explanatory diagram of the parity check method PCi according to the present invention according to ROMs with different capacities, and FIG. 3 is a process of the ROM parity check method of the present invention. The flowchart of FIG. 4 and FIG. 5 are explanatory diagrams of the conventional example. 1. System body, 2. Keyboard, 3. Display device, 1a. Processor, 1b. ROM. PCi: Parity check method, BLi: Block length

Claims (2)

[Claims] (1) Divide the data in the ROM into blocks of a predetermined length, add a parity bit to each block, and set the value of the parity bit so that the sum of bits in the block including the parity bit becomes the predetermined value. R is determined by the system.
In the ROM parity check method for checking the parity of data in the OM, multiple parity check methods are prepared according to the ROM capacity, and when checking the parity of the data in the ROM, the multiple parity check methods are sequentially performed. If the bit sum by any one of the plurality of parity check methods matches the predetermined value, it is determined to be good, and if it does not match by any of the parity check methods, it is determined to be defective. R characterized by generating an alarm
How to check OM parity. (2) The ROM parity check method according to claim (1), wherein the plurality of parity check methods have different block lengths to which parity bits are added.