JPS59154698A - Protecting system of control storage - Google Patents

Protecting system of control storage

Info

Publication number
JPS59154698A
JPS59154698A JP2876483A JP2876483A JPS59154698A JP S59154698 A JPS59154698 A JP S59154698A JP 2876483 A JP2876483 A JP 2876483A JP 2876483 A JP2876483 A JP 2876483A JP S59154698 A JPS59154698 A JP S59154698A
Authority
JP
Japan
Prior art keywords
memory
address
area
protecting
control storage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2876483A
Other languages
Japanese (ja)
Inventor
Tadashi Hanada
正 花田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP2876483A priority Critical patent/JPS59154698A/en
Publication of JPS59154698A publication Critical patent/JPS59154698A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0751—Error or fault detection not based on redundancy
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/073—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in a memory management context, e.g. virtual memory or cache management

Abstract

PURPOSE:To transmit an error signal before memory access is executed when the address of the memory access is coincident with the address of a protecting area by providing a means setting optionally the address of the protecting area of the memory in a firmware computer and a means comparing an address accessing the memory and an address designating this protecting area. CONSTITUTION:A memory address register 1 stores an address accessing a memory 3. The protecting table 2 comprising registers stores an address set optionally by a control storage area 3-1 in which control information in the memory 3 to be protected in advance is stored. The memory 3 is divided into the control storage area 3-1 in which the control information is stored and a working area 3-2 in which a working data is stored. Coincidence/dissidence between each bit of the memory address register 1 and each bit of the protecting table 2 is detected by AND circuits 5-7. When bits coincident with each other exist, an OR circuit 8 is set and its output is fed to an error processing section 4 as an error signal.

Description

【発明の詳細な説明】 （ａ）発明の技術分野 本発明はマイクロプログラムを用いて計算機の機能や命
令を実現するファームウェア計算機に係り、特に一つの
メモリを制御記録領域と作業領域に分けて共用する場合
の制御記記憶領域にある制御情報を保護する制御記憶の
保護方式に関する。Detailed Description of the Invention (a) Technical Field of the Invention The present invention relates to a firmware computer that implements computer functions and instructions using microprograms, and particularly relates to a firmware computer that uses microprograms to realize computer functions and instructions. The present invention relates to a control storage protection method for protecting control information in a control storage area when a control storage area is used.

（ｂ）従来技術と問題点 一つのメモリに制御情報を記憶する領域と作業用のデー
タを記憶する領域とを設け、共用して使用する場合、制
御情報の作成誤りとかハードウェアの障害等により、間
違って制御情報の記憶されている制御記憶領域に他のデ
ータが書き込まれる等の原因で制御情報が破壊されるこ
とがある。このため計算機システムに悪影響を与える欠
点がある。(b) Conventional technology and problems When an area for storing control information and an area for storing work data are provided in one memory and used for shared use, errors in the creation of control information, hardware failures, etc. The control information may be destroyed due to reasons such as erroneously writing other data to the control storage area where the control information is stored. For this reason, it has the drawback of adversely affecting the computer system.

（ｃ）発明の目的 本発明の目的は上記欠点を除く為、予めメモリの保護領
域を定めたアドレスを設定したテーブルを用意し、メモ
リアクセス時にメモリアクセスのアドレスを該テーブル
に格納されているアドレスと比較し、一致した場合はメ
モリアクセスに先立ってエラー信号を送出し．エラー処
哩部に通知する制御記憶の保護方式を提供することにあ
る。(c) Purpose of the Invention The purpose of the present invention is to eliminate the above-mentioned drawbacks by preparing a table in which addresses are set that define protected areas of memory in advance, and when accessing the memory, the address of the memory access is set to the address stored in the table. If they match, send an error signal before accessing the memory. An object of the present invention is to provide a control storage protection method for notifying an error handling unit.

（ｄ）発明の構成 本発明の構成は一つのメモリを制御記憶領域と作業領域
とに分けて共用する計算機に於て、メモリの保護領域の
アドレスを任意に設定する手段と、メモリをアクセスす
るアドレスと該保護領域を指定するアドレスとを比較す
る手段を設け、メモリアクセスのアドレスが保護領域の
アトレスと一致した場合、メモリアクセスを行う前にエ
ラー信号を送出する様にしたものである。(d) Structure of the Invention The structure of the present invention is, in a computer in which one memory is divided into a control storage area and a work area and shared, a means for arbitrarily setting the address of a protected area of the memory, and a method for accessing the memory. Means is provided to compare the address with an address specifying the protected area, and if the address of the memory access matches the address of the protected area, an error signal is sent out before the memory access is performed.

（ｅ）発明の実施例 図は本発明の一実施例を示す回路のブロック図である。(e) Examples of the invention The figure is a block diagram of a circuit showing one embodiment of the present invention.

メモリアドレスレジスタ１はメモリ３をアクセスするア
ドレスを格納する。レジスタで構成される保護テーブル
２は予め保護しなければならぬメモり３内の制御情報が
記憶される制御記憶領域３−１の任意に設定されたアド
レスを格納する。メモリ３は制御情報の記憶される制御
記憶領域３−１と作業用のデータが記憶される作業領域
３−２とに分けられる。メモリアドレスレジスタ１の各
ビットと保護テーブル２の各ビツトはＡＮＤ回路５、６
、７により１枚か不一致かを検出される。一致するビッ
トが有った時はＯＲ回路８がオンとなりエラー信号とし
てエラー処理部４に送出される。Memory address register 1 stores an address for accessing memory 3. A protection table 2 composed of registers stores arbitrarily set addresses of a control storage area 3-1 in which control information in the memory 3 that must be protected in advance is stored. The memory 3 is divided into a control storage area 3-1 where control information is stored and a work area 3-2 where work data is stored. Each bit of memory address register 1 and each bit of protection table 2 are connected to AND circuits 5 and 6.
, 7, it is detected whether there is one sheet or a mismatch. When there is a matching bit, the OR circuit 8 is turned on and sent to the error processing section 4 as an error signal.

（ｆ）発明の効果 以上説明した如く、本発明は一つのメモリを制御記憶領
域と作業領域とに分けて共用する計算機で、保護すべき
制御記憶領域を仕意に設定し、該制御記憶領域の記憶内
容を保護し得る為、その効果は大なるものがある。(f) Effects of the Invention As explained above, the present invention provides a computer in which a single memory is shared by dividing it into a control storage area and a work area, a control storage area to be protected is intentionally set, and the control storage area is The effect is great because it can protect the memory contents of.

【図面の簡単な説明】[Brief explanation of drawings]

図は本発明の一実施例を示す回路のブロツク図である。 １はメモリアドレスレジスタ、２は保護テーブル、３は
メモリ、４はエラー処理部である。 代理人弁理士　　松岡宏四郎The figure is a block diagram of a circuit showing one embodiment of the present invention. 1 is a memory address register, 2 is a protection table, 3 is a memory, and 4 is an error processing section. Representative Patent Attorney Koshiro Matsuoka

Claims (1)

【特許請求の範囲】[Claims] 一つのメモリを制御記憶領域と作業領域とに分けて共用
する計算機に於て、メモリの保護領域のアドレスを任意
に設定する手段と、メモリをアクセズするアドレスと該
保護領域を指定するアドレスとを比較する手段を設け、
メモリアクセスのアドレスが保護領域のアドレスと一致
した場合、メモリアクセスを行う前にエラー信号を送出
することを特徴とする制御記憶の保護方式。In a computer that shares one memory by dividing it into a control storage area and a work area, a means for arbitrarily setting the address of a protected area of the memory, an address for accessing the memory, and an address for specifying the protected area is provided. provide a means of comparison,
A control memory protection method characterized in that if a memory access address matches an address in a protected area, an error signal is sent before memory access is performed.
JP2876483A 1983-02-23 1983-02-23 Protecting system of control storage Pending JPS59154698A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2876483A JPS59154698A (en) 1983-02-23 1983-02-23 Protecting system of control storage

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2876483A JPS59154698A (en) 1983-02-23 1983-02-23 Protecting system of control storage

Publications (1)

Publication Number Publication Date
JPS59154698A true JPS59154698A (en) 1984-09-03

Family

ID=12257469

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2876483A Pending JPS59154698A (en) 1983-02-23 1983-02-23 Protecting system of control storage

Country Status (1)

Country Link
JP (1) JPS59154698A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6441033A (en) * 1987-08-06 1989-02-13 Mitsubishi Electric Corp Data processor
JPS6441034A (en) * 1987-08-06 1989-02-13 Mitsubishi Electric Corp Data processor
JPH0387936A (en) * 1987-10-01 1991-04-12 Mitsubishi Electric Corp Abnormality detecting circuit for computer

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6441033A (en) * 1987-08-06 1989-02-13 Mitsubishi Electric Corp Data processor
JPS6441034A (en) * 1987-08-06 1989-02-13 Mitsubishi Electric Corp Data processor
JPH0387936A (en) * 1987-10-01 1991-04-12 Mitsubishi Electric Corp Abnormality detecting circuit for computer

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