JPH01251253A - Memory protecting device - Google Patents

Abstract

PURPOSE:To execute the memory protection by executing an inhibition and a detection of write by other semiconductor storage device than a RAM, with respect to write to a write inhibiting area in the RAM. CONSTITUTION:A detection use memory 1 being a semiconductor storage device exists in the same address space as a RAM 2. A detection input 4 is connected to a data read terminal 6 of the memory 1, and by this signal, a protecting address detection, namely, a memory protection of the RAM 2 is executed. Also, by using the memory 1, whether an address brought to address by data written in the memory 1 in advance is a protecting area of a write inhibition or not is decided, and if it is the protecting area, write is inhibited. Also, by generating an interruption request, etc., the detection can be informed to a CPU.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory protection device for inhibiting and detecting writing to RAM in a storage device in a microcomputer system.

[Prior Art] In a conventional memory protection device, a memory address to be detected is set in a register 20 as shown in FIG.
A comparator 21 compares this set value with an address value written to the RAM, and a memory protect address is detected based on a match.

[Problems to be Solved by the Invention] For this reason, a large number of registers and comparators are required for a plurality of addresses and areas to be memory protected, resulting in a complicated configuration. Furthermore, it is difficult to provide a memory protection device that is flexible enough to allow settings for each address.

SUMMARY OF THE INVENTION The present invention aims to solve these problems, and provides a memory protection device that has a simpler configuration, can easily set multiple addresses and areas for memory protection, and reliably detects and protects memory. By the way.

[Means to solve the problem]

In a microcomputer system, the memory protection device of the present invention detects whether an accessed address is a write-prohibited area when writing to a RAM in the memory, and performs memory protection on a memory other than the above-mentioned memory. It is characterized by using .

[Operation] According to the above configuration of the present invention, in the memory protection device, by using the memory, it is determined whether the address accessed with data written in the memory in advance is a write-protected protected area, and the protected area is protected. If so, by prohibiting writing and generating interrupt requests etc., the microprocessor (hereinafter referred to as CPU)
shall be. ) to notify the detection.

[Embodiment] FIG. 1 is a block diagram of an embodiment of the memory protection device of the present invention. In the figure, 1 is a detection memory for memory protection, and 2 in the figure is a RAM normally used in microcomputer systems.In this embodiment, the detection memory 1 has a data width of 1 bit. R
Use AM. Furthermore, the detection memory 1 exists in the same address space as the RAM 2. The detection power 4 is connected to the data read terminal 6 of the detection memory 1, and this signal detects the protect address, that is, protects the memory of the RAM 2.The setting power 3 passes through the data write power 9 and the AND gate 11, is connected to the data write terminal 5 of the memory 1. This signal allows detection data to be written into the detection memory 1.

First, the writing of detection data to the detection memory l for protection will be described with reference to a timing chart shown in FIG. Data input terminal 7 of detection memory 1
The least significant bit of the data bus is connected to , and data is given to the detection memory 1 by a signal from the data input terminal 7 .

When writing to the detection memory 1, the setting manual 3 signal a
is set to level 1, and otherwise set to level 0. (Hereinafter, the level O° of the signal will be referred to as a low level, and the level 1 will be referred to as a high level.) Then, when the write timing signal C from the data write human power 9 becomes a high level, the data write terminal of the detection memory 1 5 becomes high level, and the lowest bit data of the data bus is written from the data input terminal 7 to a certain address in the detection memory l. When the written data is at a low level, the written memory address becomes the memory protection detection address. Area setting is also done by writing low-level data to consecutive addresses. When writing to the detection memory 1, the signal a of the setting manual 3 is at a high level, and the NOT gate 13 causes one input of the AND gate 14 to go to a low level, causing the signal f to go to a low level and writing to the memory 2. will not be performed.

In this way, it is assumed that low level data regarding the protect address is written in advance in the detection memory 1.

Next, execution of memory protection for writing to a protect address will be described with reference to a timing chart shown in FIG. Assume that the detection address has been set as described above, and the detection address has been set at address A where the detection memory l is located. CPU is this A on RAM2
When writing is performed to an address, the address data of address A is output to the RAM 2 on the address bus. Since the detection memory 1 exists in the same address space as the RAM 2, similar address data is also sent to the detection memory 1. While memory protection is being executed, the signal a of the setting manual 3 is at a low level, and the detection memory 1 is read-only. Then, the low level data set at address A of the detection memory 1 is output from the data output terminal 8. In this manner, a low level is output from the detection memory 1 at the memory protection detection address. On the other hand, the signal from the data write power 9 passes through the AND gate 14 and becomes the signal f.・Input in 12. The signal g from the data output terminal 8 is input to the other side of the AND gate 12 . The output of the AND gate 12 is connected to the data write terminal 10 of the RAM 2.

At this time, since the signal a is at a low level, the signal f
is equal to signal C. Therefore, if the signal g at the data output terminal 8 is at a low level, the CPU cannot write to the RAM 2, and memory protection is performed.

When the signal g at the data output terminal 8 is at a low level, at the same time as the memory protect is performed, the signal g is inputted to the AND gate 16 via the NOT gate 15, and is ANDed with the data write input signal to become the detection signal. .

The detection signal 11 is sent to the CPU as an interrupt request signal or the like.
to notify the detection.

In this way, set the protect address using memory,
It is possible to detect and protect memory. Further, in this embodiment, the detection memory 1 is a RAM, but
A read-only memory (hereinafter referred to as ROM) is also possible. When a ROM is used, it is impossible to change the setting address, but since there is no need to perform setting, the setting manual 3 and the gates 11, 13, 14 are unnecessary, and the configuration becomes simpler.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to easily set and change the address or area to be protected, and to realize write protection and detection of writing to a write-protected area on RAM with a simple configuration. is possible. During software development for microcomputer systems, the stack and RA may be damaged due to software inadvertence.
By using the memory protection device of the present invention, it is possible to easily set and change the memory protection on RAM in a microcomputer system for each address in the RAM area. It is possible to do so. Therefore, settings and changes can be made frequently during software development and debugging, which improves work efficiency and is highly effective in improving operational reliability.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a memory protection device of the present invention. FIG. 2 is a diagram showing a conventional detection method. FIG. 3 is a timing chart for writing setting data in the memory protection device of the present invention. FIG. 4 is a timing chart of memory protection and detection in the memory protection device of the present invention. 1...Detection memory 2...RAM 3...Setting manual power 4...Detection input 5...Data write terminal 6...Data read terminal 7...Data input terminal 8...Data Output terminal 9...Data write input 10...Data write terminal 11...And gate 12...And gate 13...Not gate 14...And gate 15...Not gate 16... AND gate 20...Register 21...Comparator 22...Write signal 23...Detection signal and above Applicant Seiko Epson Co., Ltd. 1'7-Harm of the drawing (no change in content) Figure 3, Figure 4 Draft procedure amendment (method) 1. Indication of case 1986 Patent application No. 7
No. 8924 2, Title of invention Memory protection device 3
, Relationship to the amended person case Applicant 2-4-1 Nishi-Shinjuku, Shinjuku-ku, Tokyo (236) Tsuneya Nakamura, Representative Director of Seiko Epson Corporation 4, Agent Address: 2-6 Kyobashi, Chuo-ku, Tokyo 104 As shown in the engraving appendix of the drawings (Figures 3 and 4) originally attached to Application No. 21 (no change in content)

Claims (1)

[Claims] In a microcomputer system having a readable/writable semiconductor memory device (hereinafter referred to as RAM), write inhibition and detection for writing to a write-protected area in the RAM, etc. A memory protection device characterized in that the protection is performed separately by a semiconductor storage device.