JPS6233627B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a small electronic calculator that processes data expressed in exponential form.

[Prior art and its problems]

Recently, when inputting and calculating normal numeric data that is not expressed exponentially, it is done with (m + n) digits, and when inputting and calculating numerical data that is expressed exponentially, the mantissa part is m digits, and the exponent part is is n
A small electronic calculator using the so-called exponential method, which uses digits, has been developed and put into practical use. Conventionally, in this type of small-sized electronic calculator, the number of digits that can be placed in the mantissa data of numerical data expressed in exponential form and the number of digits that can be operated on are limited to m digits. In other words, when inputting numerical data expressed as an index, first input the mantissa data up to m digits, and then operate the special key for inputting the exponent data such as EXP. Mantissa data at least n
A procedure is followed in which the digits are shifted to the upper digits, and then the exponent part data is input into the lower n digits. By the way, the number of digits for the first input data can be up to (m+n) digits, so if the number of digits for this data exceeds m and you want to use this data as mantissa data, then use the following method to input exponent data: Even if the dedicated key is operated, the mantissa data will not be carried forward, and the exponent data cannot be input next. As described above, in the conventional exponential type compact electronic calculator, data exceeding m digits cannot be used as mantissa data. Therefore, when inputting numerical data expressed in exponential form, the operator must always take into consideration that the input mantissa data does not exceed m digits.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and is a compact device that allows input numerical data that is not expressed as an exponent to be used as mantissa data regardless of the number of digits, and also allows input of exponent data. The purpose is to provide electronic calculators.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram of a small electronic calculator according to the present invention. In the figure, 1 is a ROM (read-only memory), and this ROM 1 stores microinstructions that execute various operations of this computer, and corresponds to the address signal output from the ROM address section 2. , outputs various microinstructions. One microinstruction is S _U , F _U , S _L , F
It consists of _L , C _O , M, O _P and Na, each of which has a predetermined binary code fixedly incorporated therein. Each binary code of the microinstructions mentioned above is output simultaneously and in parallel according to the address designation of the ROM address section 2. S _U and _{F U} specify the row address of _RAM (Random _Access Memory) ₃ , which will be described later. terminal UA
is input to. The gate circuit G ₁ is opened when the timing signal t ₁ is periodically output from the timing signal generation circuit 4, and the timing signal t ₁ is applied to the gate circuit G ₂ via the inverter circuit 5. Therefore, it is opened at times other than when the timing signal _t1 is output. Incidentally, the timing signal outputted from the timing signal generation circuit 4 is shown in FIG. Timing signals t ₁ , t ₂ , t ₃ are sequentially and periodically outputted in synchronization with clock pulses ψ ₁ and ψ ₂ . Then, a clock pulse ψ _D =t ₃ ·ψ is output every cycle of the timing signals t ₁ to t ₃ . Among the above microinstructions, S _L and F _L are in the RAM 3 above.
Normally, S _L is paired with the row address specified by S _U above, and F _L is paired with the row address specified by F _U above. And S _L is a timing decoder 9, which will be described later.
F L is input to the terminal LA of the RAM 3 via the gate circuit G ₃ which is opened when the timing signal ta is output from the timing decoder 9, and F _L is the gate circuit G which is opened when the timing signal tb is output from the timing decoder 9. ₄ to terminal LA of RAM3. The above timing signals ta and tb are usually logical formula ta
This is a signal obtained by =·S _T +M·t ₁ , tb=M· ₁ . Details of the signals M and S _T will be described later, but when one microinstruction is an instruction that ends in one digit period, the signal M outputs "1" during the output period (one digit period) of this microinstruction. Signal S _T outputs a "1" for the first one digit period of each microinstruction. Therefore, when M=1, ta= _t1 , tb= ₁ = _t2 + _t3 , and the address of RAM3 during the timing signal _t1 output period is determined by the row address S _U and column address S _L. specified,
The address of the RAM 3 during the timing signal t ₂ -t ₃ output period is specified by the row address F _U and the column address _FL . If one microinstruction requires multiple digit periods, M=0, and in this case, t _a =
S _T , t _b =“0”. That is, during the first one digit period, S _L is output via the gate circuit G ₃ and becomes the column address of the RAM 3. Further, this value of S _L is input to a counter 6 which performs a counting operation in synchronization with the clock pulse ψ _d =ψ _D ·. This counter 6 performs a down or up counting operation depending on the presence or absence of a DN signal, which will be described later. From the second digit of the microinstruction made up of the plurality of digits, the value of the counter 6 is input to the terminal LA of the RAM 3 via the gate circuit _G5 , which opens when the timing signal t _c =M S _T is output.
This is the column address of RAM3. At the same time, the value of the counter 6 is fed back to the counter ₆ again via the gate circuit G5, and is counted down or up, and is input into one of the matching circuits 7. In the microinstruction consisting of a plurality of digits, the gate circuit _G4 is closed, and F _L output from the ROM 1 is input to the other matching circuit 7. When the value of the counter 6 becomes equal to _F.sub.L , a coincidence signal is output from the coincidence circuit 7, and the microinstruction consisting of a plurality of digits is terminated, as will be described later. That is, in a microinstruction consisting of multiple digits, the processing start digit of the storage area (hereinafter referred to as a register) in RAM 3 specified by S _U or F _U is specified by S _L , and the processing end digit is F. _L
specified by. Furthermore, the microinstruction is
In the case of a shift command to shift the register of RAM3 to the left or right, each of the above timing signals is t _a
= t ₁ , t _b = “0”, t _c = t ₁ ·S _T . Further, among the microinstructions mentioned above, C ₀ is also used as a binary code such as a numerical value or a code, and is outputted via a gate circuit G6 that is opened when the signal CI is outputted. Further, M of the above microinstructions is a mode signal that outputs "1" when one microinstruction is an instruction that ends in one digit. Among the microinstructions mentioned above, O _P outputs various instruction codes such as _addition , subtraction, transfer, judgment, left shift, right shift, display, and key sampling. After being disconnected, the signal is input to the timing decoder 9. This timing decoder 9 selectively outputs signals CI, OF, OS, ID, KE, SB, etc. according to each of the above instructions. Further, timing signals t ₁ , t ₂ , t ₃ and clock pulses ψ ₁ , ψ ₂ , ψ _D outputted from the timing signal generation circuit 4 are connected to gate circuits G ₁ , G ₇ , G ₈ .
The signal is given as a timing signal to circuits such as the above, and is also input to the timing decoder 9. Therefore, the timing decoder 9 further outputs timing signals _ta , _tb , _tc , _td and signals DN, R/W.
Select and output. Signals CI, OF, OS, ID, and KE are control signals for gate circuits G ₆ , G ₉ , G ₁₀ , G ₁₁ , and G ₁₂ , respectively, and when these signals are “1”, the corresponding gate circuits are opened. . The signal SB is a subtraction designation signal, and when this signal SB is input to the arithmetic circuit 16, the arithmetic circuit 16 executes a subtraction operation.
In addition, the signals ψ _a , ψ _b , and ψ _c are buffers B ₁ , ψ c , respectively.
It is given as a continuation clock signal of B ₂ and B ₃ , and expressed as a logical formula, ψ _a = ψ _D・O _P1 , ψ _b =
ψ _D・O _P2 , ψ _c =t ₂ , ψ・O _P3 . However, O _P
1 = Decimal point display data output command, O _P2 = Display data output command, O _P3 = Key sampling data (count digit data) output command. Also, ψ _d is the operation signal of the counter 6, and when expressed in a logical formula, ψ _d =
ψ _D・・O _P4 +ψ ₁・O _P4 . However, O _P4
= Shift command. As described above, the signal DN is a signal sent to the counter 6 to designate a down-count operation. The signal R/W is a signal that specifies reading/writing of the RAM 3. Further, the mode signal M is also input to the timing decoder 9. This mode signal M is inputted to one of the OR circuit 10 and the AND circuit 11, and is also inputted via the inverter circuit 12 as the enable signal to the coincidence circuit 7. The coincidence signal from the coincidence circuit 7 is input to the other of the OR circuit 10 and one of the AND circuits 13. The mode signal M and the coincidence signal are input to the flip-flop circuit 14 via the OR circuit 10, and the output signal S _T is input to the timing decoder 9. Since the flip-flop circuit 14 operates in synchronization with the clock pulse _.phi.D at digit intervals, the signal S _T is a signal output for the first digit period of each microinstruction. In addition, the AND circuits 11 and 1
A clock pulse ψ _D is input to the other of the AND circuits 11 and 13 , and both of the AND circuits 11 and 13 output the signal ψ _e as a signal ψ e through an OR circuit 15 and serve as a read clock for the address conversion circuit 17 . Among the microinstructions, N _a is a signal specifying the address of the next step microinstruction of the microinstruction currently being executed in the ROM 1 and is input to the address conversion circuit 17 . Furthermore, AND circuits 18 and 19 are input to this address conversion circuit 17. AND circuit 1
Data is input from the arithmetic circuit 16 to one of the AND circuits 19, a carry (or borrow) is input to one of the AND circuits 19, and the signal JU from the timing decoder 9 is input to the other of the AND circuits 18 and 19. . This signal JU is output at the time of a judgment command, and at this time, the address conversion circuit 17 executes OR addition of the contents of N _a and the outputs of AND circuits 18 and 19, and calculates the address indicating the next step in ROM1. and sent to the ROM address section 2. Next, the configuration of the RAM 3, arithmetic circuit 16, etc. controlled by the microinstructions of the ROM 1 will be explained. As mentioned above, RAM3 is addressed by the row addresses S _U , F _U input to the terminal UA and the column addresses S _L , F _L input to the terminal LA, and when the signal R/W is “0”. Data within the specified address is output from the output terminal OUT in parallel 4
Read as bit data, R/W="1"
Writes the parallel data given from the input terminal IN into the address specified when . Normally, the above signal R/W is designated as read (R/W="0") when the timing signals t ₁ to _{t 2} are output, and the timing signal
Specified for writing (R/W="1") when outputting _t3 . Furthermore, since the gate circuits G ₁ and G ₃ are normally synchronized with the timing signal t ₁ , the data in the RAM 3 designated by S _U and S _L is sent to the output terminal OUT when the timing signal t ₁ is output. and stored in the latch 20 via the gate circuit _G8 which is opened by the timing signal _t1 · _ψ1 . Furthermore, the gate circuits G ₂ and G ₄ normally use the timing signal t ₁ = t ₂ + t ₃
Since the data in the RAM 3 specified by F _U and F _L are read out when the timing signal t ₂ is output, the data is read out through the gate circuit G ₇ which is opened by the timing signal t ₂ · ψ ₁ . and stored in the latch 21. The data stored in latches 20 and 21 are sent to input terminals S, F of arithmetic circuit 16 via gate circuits G ₁₀ , G ₉ opened by signals OS, OF, respectively. The arithmetic circuit 16 executes addition or subtraction in parallel based on data applied to input terminals S and F. The designation of addition and subtraction is performed by the signal SB; addition is performed when SB="0", and subtraction is performed when SB="1". The above calculation result data is output from terminal D and applied to input terminal IN of RAM3. Further, carry (or borrow) data of the arithmetic circuit 16 is outputted from the terminal C. The above calculation result data given to the input terminal IN of RAM3 is output when the timing signal _t3 is output.
It is written into the RAM 3 specified by the addresses F _U and F _L. Further, the parallel data of the calculation result of the calculation circuit 16 is inputted from the terminal D to one side of the AND circuit 18 via the OR circuit 22, and
The carry (or borrow) of 6 is input from terminal C to one side of the AND circuit 19. Also, above
1 digit of storage area in RAM3 (count digit)
However, during display and key sampling, the calculation circuit 1
It is counted up through 6. The count value of this count digit is the gate circuit _G8 and latch 2.
0 is applied to the buffer _B3 via the gate circuit _G10 . Buffer _B3 reads the value of the count digit in synchronization with clock pulse _ψc . This batshua
The value read into B ₃ is sent as a digit signal on the display section 24 via the decoder 23 and as a digit signal on the key input section 25.
output as a key sampling pulse. Further, the Z register in the RAM 3 is used as a display register. When displaying data, the value of the count digit is first read out, and this value is passed through gate circuit _G8 , latch 20, and gate circuit _G11.
This is the column address of RAM3. At this time, the row address specifies the Z register, so data in a predetermined digit of the display register Z corresponding to the value of the count digit is read out, and this data is sent to the gate circuit _G7.
and is applied to the buffer _B2 via the latch 21 and the gate circuit _G9 . Buffer B ₂ reads the given data in synchronization with clock pulse ψ _b ,
Furthermore, it is sent to the display section 24 via the decoder 26. As described above, since the corresponding digit signal is sent to the display section 24 from the decoder 23, the contents of the count digits among the digits on the display section 24 are shown as a result. The contents of the same digit of the Z register are displayed in the digit. Further, the buffer _B1 reads decimal point data in synchronization with the clock pulse _.phi.a , and this data is further sent to the display section 24 via the decoder 26 and displayed in the same manner as described above. The key input section 25 has a line to which the key sampling signal is supplied and a key common line output to the buffer _B4 arranged in a matrix, and has a key at the intersection of each _line . The data inside is a gate circuit that opens with the signal KE output at the time of the key sampling command.
Input to terminal S of arithmetic circuit 16 via _G12 ,
Further, the data is written into the RAM 3 from the terminal D of the arithmetic circuit 16. At this time, when the key common data is detected in the buffer _B4 , the counting operation of the count digit is stopped, and the operation key is determined based on the count value at this time and the data in the buffer _B4 . If it is a numeric key, the numerical data corresponding to that key is input to the display register (Z register), and if it is a function key, Na of ROM1 is input to address conversion circuit 1 according to the judgment result.
A ROM that was changed in 7 and is used to perform specific processing.
The first address of the address is specified.

The storage area in the RAM 3 designated when the column address input to the terminal LA of the RAM 3 is 0 to 15 and the row address 0 is input to the terminal UA is called a register X. Furthermore, the storage areas in the RAM 3 that are designated when column addresses 0 to 15 and row addresses 1, 2, 3, and 4 are input are respectively referred to as register Y, register Z, register A, and register B. The storage area of the register X is shown in FIG. 3a. _{Register _} Or the answer is stored, and the code of the data in the digits X ₀ to X 10 is stored in the digit X _s specified by the column address value 11, and the code of the data in the digits X 0 to X ₁₀ specified by the column address value 12 to ₁₃ is stored. _P2 stores data indicating the decimal point position of the data in the digits X ₀ to X ₁₀ , and digit X _DP specified by column address value 14 contains a decimal point flag indicating whether or not the decimal point key □・ has been operated. However, in the digit X _EXP designated by the column address value 15, an EXP flag indicating whether or not the exponent key EXP has been operated is stored. Register Y stores an arithmetic number or decimal point, and in particular during key sampling and display, the decimal point is displayed in a predetermined digit of register Y according to the data of digits z _P1 to z _P2 indicating the decimal point display position of register Z, which will be described later. data for is stored. Register Z is a register for setting and displaying numbers, and as shown in Figure 3b,
Digits z _{0 to z 10 specified by column address values 0} to ₁₀ contain display data, and digit z _F specified by column address value 11 contains data indicating the number of digits of display data.
Data indicating the decimal point display position of display data is stored in digits z _P1 to z _P2 designated by column address values 12 to 13. Registers A and B are temporary storage for calculations and auxiliary registers in which various flags are stored.

Next, the operation of the circuit configured as described above will be explained.

FIG. 4 is a flowchart representing a series of microinstructions stored in the ROM1.
Each processing step of the series of microinstructions described above expressed in this flowchart will be explained below. First, in step A, key sampling for sampling the data supplied from the key input section 25 and display of the data in the register Z are performed as described above. and in step A 0
When it is detected that a numeric key for inputting a numerical value such as ~9 has been operated, the program proceeds to step B, where the numerical data corresponding to the numeric key is stored in the least significant digit of register Z. is memorized.
Next, the process advances to step C, where it is determined whether the key EXP for inputting index data has been previously operated or not, based on the presence or absence of the EXP flag. _{Since the EXP} flag is stored in the 16th digit of register
Flag, M=1, O _P =judgment instruction code, Na=
Output the address of step I. The instruction code for the above judgment is input to the timing decoder 9 via the operation decoder 8, and from this timing decoder 9, the signals CI, OF, SB, JU, t _b ,
R/W etc. are output. Therefore, the above F _U , F _L
The digit x _EXP (see FIG. 3a) of the register X designated by is inputted to the terminal F of the arithmetic circuit 16 via the gate circuit _G7 , the latch 21, and the gate circuit _G9 . On the other hand, the binary code C _O storing the EXP flag is input to the S terminal of the arithmetic circuit ₁₆ via the gate circuit G6. This arithmetic circuit 16 is a signal
Since subtraction is specified by SB, the data input to terminal S is subtracted from the data input to terminal F above, and as a result, data is output from terminal D and a carry (or borrow) is output from terminal C. be done. The above data is input to the address conversion circuit 17 via the OR circuit 22 and the AND circuit 18 to which the signal JU is input, and the carry (or borrow) is input to the AND circuit 18 to which the signal JU is input. It is input to the address conversion circuit 17 via the circuit 19. That is, if x _EXP has an EXP flag, both the data and carry output from the arithmetic circuit 16 are "0". Therefore, at this time, the address of step I input from Na to the address translation circuit 17 is not translated, and the address for outputting the next microinstruction of step I is designated. On the other hand, when data or carry is output from the arithmetic circuit 16, the address of step I output from Na is OR-added with the data or carry in the address conversion circuit 17, and the address is converted into the address of step D. Become. In the following flow, a detailed explanation of the above-mentioned judgment operation will be omitted. In this way, step C
If the EXP flag is not detected in step D, the process proceeds to step D, while if the EXP flag is detected, the process proceeds to step I. Next, in step D, it is determined whether or not the key □. for inputting a decimal point has been previously operated based on the presence or absence of a decimal point flag. If this flag is detected, the process proceeds to step E. In step E, the numerical value 1 is added to the digits z _P1 and z _P2 indicating the decimal point position of the display register Z. The microinstructions for the operation shown in step E are F _U =2, S _L =12, F _L =13, C _O =1, M=
0, _OP = addition of binary code and data in RAM3, Na = address of step F. At this time, the signals CI, OF, ψ are output from the timing decoder 9.
_d and t _a are output. Therefore, the data in _zP1 of register Z specified by the addresses of F _U and S _L is read out, and gate circuit G ₇ and latch 2
1. Input to terminal F of arithmetic circuit 16 via gate circuit _G9 . On the other hand, since the value "1" of the binary code of C _O is input to the terminal S via the gate circuit _G6 , in this arithmetic circuit 16, z _P1 +
1 is performed, and the operation result is written to z _P1 of register Z designated by F _U and S _L . The above operation is performed in one cycle of timing signals _t1 to _t3 .
On the other hand, the value 12 of S _L is set to counter 6, and ψ _d
counted up to 13 by
This is the column address for the period _t1 to _t3 . Furthermore, M=0
The output of is sent to the matching circuit 7 via the inverter circuit 12.
Since it is given as an enable signal for the counter 6, the matching circuit 7 detects a match between the value of the counter 6 and the value of _F.sub.L. That is, in the next cycle, the data in z _P2 is read and the data circuit G ₇
It is input to the arithmetic circuit 16 via the latch 21 and gate circuit _G9 , and if a carry occurred in the previous addition operation, the carry and the above data are added and written to _zP2 again. At this time, since the match signal from the match circuit 7 is input to the AND circuit 13, the clock signal ψ _D input to the other side of the AND circuit 13 is passed through the OR circuit to the read clock ψ _e of the address conversion circuit 17. The address Na for outputting the next step F microinstruction is read. Furthermore, the coincidence signal is inputted to the flip-flop circuit 14 via the OR circuit 10, and from this flip-flop circuit 14, the signal _ST is output during the first cycle period of the next step F (at the time of output from _t1 to _t3 ). It is output to the timing decoder 9. In the following flow, a detailed explanation of the code addition operation as described above will be omitted. Next, in step F, the contents of z _P1 and z _P2 of display register Z after addition of 1 are transferred to digits x _P1 and x _P2 of digit register X indicating the decimal point position. The microinstruction output in step F is S _U =
2, F _U =0, S _L =12, F _L =13, M=0, O _P =
Transfer, Na=address of step G. That is, when the timing signal _t1 of the first cycle is output, the digit _zP1 of the register Z specified by S _U and S _L is read out to the latch 20 via the gate circuit _G8 , and when the timing signal _t3 is output, , the data in the latch 20 is written to the digit x _P1 of the register X designated by F _U and S _L via the gate circuit G ₁₀ and the arithmetic circuit 16. next cycle timing signal t ₁
At the time of output, the digit z of register Z specified by counter 6 counted up by S _U and ψ _d
P2 is stored in the latch 20 via the gate circuit _G8 , and when the timing signal _t3 is output, the latch 20
The data stored in is written to digit x _P2 of register X specified by F _U and counter 6 via gate circuit G ₁₀ and arithmetic circuit 16, and at the same time, a coincidence signal is output from coincidence circuit 7, This step F is completed. In the following flow, a detailed explanation of the above-mentioned transfer operation will be omitted. After the step F is completed, the process proceeds to step G. On the other hand, if the decimal point flag is not detected in step D, the process proceeds to step G. The digit in which the digit data of the digit and display register Z is stored in step G.
The contents of z ₀ -z ₁₀ are transferred to digits x ₀ -x ₁₀ of register X. Next, after transferring the set number data, the process advances to step H.
In this step H, the number and display register Z
The numerical value 1 is added to the digit z _F indicating the number of displayed digits. After this, proceed to step I. In step I, the decimal point display position of digits z _P1 and z _P2 of register Z is detected, and decimal point data is written to the digit of Y register indicated by the data in z _P1 and z _P2 . Furthermore, the presence or absence of data 8 indicating that the numeral data is negative in digit _xs is detected, and if it is negative, the beginning of the numeral data in register Z is
A “-” sign is input. After this, the process returns to step A again. In step A, the numeric data and decimal point are displayed and key sampling is performed. For example, −123456789×
When inputting 10 to ¹² sequentially from the key input unit 25, first, the keys are operated in the order of □-, □1, □2...□8, □9. At this time, the operations of steps A to I described above are performed for each key operation. However, in the numeric processing of process B, numeric data of up to 10 digits can be input. FIG. 5 shows the storage state of the registers X and Z and the display state of the display unit 24 after the above series of key operations are completed. That is, EXP key and □Γ
Since the key has not been operated yet, step E.
The operation of F is not performed, and the digit indicating the decimal point position z _P
1 , z _P2 and x _P1 , x _P2 are both 0. Also,
_zF , which stores the number of digits of the numeric data, is 9 because it is incremented by 1 at step H every time the numeric key is operated. Furthermore, by operating the □- key, 8 is stored in the digit _xs for storing the sign, indicating that the set number data is negative. Therefore, the display section 24 shows 1
A decimal point is displayed in the digit, and a minus sign is displayed in the 10th digit.

Then, when it is detected in step A that the key EXP has been operated, the process proceeds to step J. In step J, it is determined whether the contents of digit _xs of register X is 0 or not. That is, it is determined whether the numeric data stored in register X represents a negative number or a positive number, and x
If the content of _s represents 8, that is, a negative number, proceed to step K. Next, in this step K, 1 is added to the contents of the digit z _F in the register Z indicating the number of digits to be set. Then proceed to step L. On the other hand, in step J, if the contents of _xs are 0, that is, if the contents of register X are numeric data representing a positive number, the process immediately proceeds to step L. That is, if the digit data is negative, z _F +1 is performed to treat the sign "-" between registers Z as one digit worth of data. In the above example, the numeric data is negative (x _s =8), so it is determined at step J that x _s ≠0, and it is incremented by 1 at step K, resulting in z _F =10. Next, in step L, 9 is extracted from the contents of digit z _F of register Z.
is subtracted, and the number of digits of the set number data including the sign "-" in register Z is detected. Then, when the number of digits of the above set number data is 10 digits, proceed to step M,
In this step M, the stored contents of register Z from _z0 to _z10 are carried up by one digit. Thereafter, the process proceeds to step N, where 1 is added to the contents of the digits z _P1 and z _P2 indicating the decimal point position, and then the process proceeds to step V. On the other hand, when the number of digits of the set number data is 9 digits in step L, the process advances to step O, and in this step O, the contents of register Z are set to 1.
Carry is carried. Thereafter, the process proceeds to step P, where the number is further incremented by one digit. Thereafter, the process proceeds to step Q, where 2 is added to the contents of the digits z _P1 and z _P2 indicating the decimal point position, and then the process proceeds to step V. Furthermore, in step L, when the number of digits of the digit data in register Z is less than eight digits, the process advances to step R, where the digit data is incremented by one digit. Thereafter, the process proceeds to steps S and T, and after the set number data is incremented by one digit in each step, the process proceeds to step U. At step U, 3 is added to the contents of z _P1 and z _P2 , and the process then proceeds to step V.
The microinstructions for carry operations in steps M, O, P, R, S, and T above are F _U =2, S _L =10,
F _L = 0, M = 0, O _P = carry shift instruction, Na
= address of next step. Furthermore, the timing decoder 9 outputs the signal OF and t _a =t ₁ ,
t _c = ₁ · _T , ψ _d = ψ ₁ , DN = t ₁ + t ₃ are output. That is, the first cycle (timing signal t ₁
The operation when ~t ₃ is output is that when the timing signal t ₁ is output, S _L = 10 is read into the counter 6 which counts down at ψ _d = (t ₁ + t ₃ )・ψ ₁ , and when the timing signal T ₂ is output, the counter 6 reads S L = 10. 6 to gate circuit G ₅
The count value 9 is input to the terminal LA of the RAM 3 via the counter 6, and is fed back to the counter 6 again. At this time, the register Z specified by the address of F _U =2 and the count value 9 of the counter 6
z ₉ is read out and stored in latch 21 via gate circuit G ₇ . At this time, counter 6 is ψ _d =
It is counted up at t ₂・ψ ₁ and becomes 10. When the next timing signal _t3 is output, the value 10 of counter 6 is output, and it is passed through gate circuit _G5 to the terminal of RAM3.
Input to LA. At this time, the data stored in the latch 21 is transferred to the register Z specified by the address of F _U =2 and the count value 10 of the counter 6 via the gate circuit _G9 and the arithmetic circuit 16.
Written to z ₁₀ . In the above one cycle, the data in _z9 of register Z is written to _z10 one digit higher. In the next cycle, the value of the counter 6 becomes 8 when the timing signal t ₂ is output, and the value of the counter 6 becomes 9 when the timing signal t ₃ is output. Therefore, data in z ₈ is written to z ₉ . Thereafter, the carry is incremented by one digit in each cycle in the same way, and the value of counter 6 becomes 0.
This is continued until the matching circuit 7 detects a matching signal with the value 0 of F _L . A detailed explanation of the above-mentioned carry operation will be omitted in the following flow. In the embodiment of the present invention, since z _F =10 at step K, the process proceeds from step L to step M, and after z ₀ to z ₁₀ are carried up by one digit, z _P2 ,z _P1 = 1. Next, step V
At this point, the contents of digits z ₀ and z ₁ of register Z are cleared. In the next step W, an EXP flag is set to _xExP to confirm that the key EXP for inputting index data has been operated. Next, the program advances to step BA, where a blanking code is stored in the third digit _zJ of register Z, and then the program advances to step I. After the decimal point display positions of z _P1 and z _P2 and the sign of x _s are detected in step I, they are displayed in step A. The states of registers X, Z and display section 24 at this time are
As shown in the figure.

In this way, the mantissa part of the numeric data is displayed in the mantissa display part, including the upper eight digits including a "-", such as "-1234567", and the decimal point is displayed in the second digit in the instruction display part. As a result, the operator cannot visually recognize the last two digits of the numerical value "89", but the display of the decimal point makes it easier to recognize that the number data is nine digits. At this time, no index data has been input into the index section yet.

Next, enter the exponent data “12” into the key input section 25.
When inputting from
The EXP flag is detected and the process immediately proceeds to process I.
After this processing I, processing A is displayed. The states of the registers X, Z and the display section 24 at this time are shown in FIG. In other words, the mantissa has 9 digits, and the upper 7
The digit is "-1234567" and the exponent part is "12"
It shows that.

Next, when it is detected in step A that a function key for performing four arithmetic operations has been operated, the process proceeds to step BB. This step
In BB, the contents of digits x _P1 and x _P2 of register X are subtracted from the contents of digits z ₁ and z ₀ of register Z, and the result is transferred to digits z ₁ and z ₀ of register Z. In this case, x
Since _P2 x _P1 = 0, the value of z ₁ z ₀ remains unchanged and is 12. Next, the program advances to step BC, in which the contents of digits z ₁ and z ₀ of display register Z are transferred to digits x _P1 and x _P2 of digit register X. Therefore x
_P2 x _P1 = 12. Next, the program advances to step BD, in which various operations corresponding to the function keys are executed, and the results of these operations are stored in register X. In the above embodiment, since the function key is operated immediately after setting the number, no calculation is performed and the process proceeds to the next step BE. Then, in step BE, the contents of register X are transferred to register Z. Next, proceed to step BF,
In this step BF, the digit z _P1 of register Z,
z 11 corresponding to the number of displayed digits is added to the contents of z _P2 z _P2 z _P1
=22. Then proceed to step BG. In step BG, it is determined whether digit _z10 of register Z is 0 or not, that is, whether digit _z10 contains numerical data. If it is determined in step BG that there is no numerical data in digit _z10 , the process advances to the next step BH, where _z0 to _z10 of register Z are incremented by one digit. Thereafter, the process advances to step BI, in which 1 is subtracted from the contents of digits z _P1 and z _P2 of display register Z, and the process returns to step BG again. On the other hand, if it is determined in step BG that there is data in digit _z10 , the process advances to the next step BJ. In the above embodiment, z ₀ to z ₁₀ are carried up by two digits, so that z _P2 z _P1 =20. In step BJ, the contents "20" of digits z _P1 and z _P2 of register Z are transferred to digits z ₁ and z ₀ . Proceeding to step BK, the contents of digit _zF of register Z are referred to and it is determined whether the set number data stored in register Z is a positive number or a negative number. When the content of digit _zF is 0, that is, when it is a positive number, the program proceeds to step BL, and this step
In BL, 10 is transferred to digits z _P1 and z _P2 of register Z. After this, proceed to step BN. As in the above embodiment, when the content of _xs is 8 in the step BL, that is, when the set number data stored in the register Z is a negative number, the process proceeds to step BM. In this step BM, 9 is transferred to digits z _P1 and z _P2 of register Z. After this, the process proceeds to step BN, where x _ExP , x _DP , and z _F are cleared. In the next step BA, a blanking code is input to z ₂ , and in the next process I, the data "9" in z _P2 and z _P1 is detected, and the data "8" in x _s is detected, and the process A
A decimal point is displayed in the 10th digit of the display section 24, and a "-" is displayed in the most significant digit. The state at this time is shown in FIG.

〔Effect of the invention〕

As explained above, according to the present invention, numerical data that can be input can be used as mantissa data regardless of the number of digits, and it is also possible to input exponent data. When inputting data, there is no need to consider the number of digits of the mantissa data, and operability can be improved. In particular, the decimal point related to the mantissa data is displayed within all display digits including the display digits that display the exponent data, which has the advantage of making it easier to check the scale of numbers that cannot be seen beyond the number of mantissa digits. be.

[Brief explanation of the drawing]

Fig. 1 is a circuit configuration diagram showing an embodiment of a small electronic calculator of the present invention, Fig. 2 is a time chart,
3a and 3b are memory state diagrams of register It is. 1...ROM, 3...RAM, 16...arithmetic circuit, 24...display section, 25...key input section.

Claims (1)

[Claims] 1. Has a display digit capacity of at least m + n digits, and when displaying data expressed in exponential form, a display section that separately displays m digits of mantissa data and n digits of exponent data, and at least m + n digits of numerical data are input. In a small electronic calculator that is capable of calculating data expressed in exponential form, the computer has a first storage means for storing numerical data input as mantissa data, and a first storage means for storing numerical data input as mantissa data; a second storage means for storing input numerical data; and a second storage means for displaying the upper m digits of the mantissa data in the first storage means on the m digits of the display section, and displaying the upper m digits of the mantissa data on the n digits of the display section; A display means for displaying the exponent part data in the second storage means and a decimal point of the mantissa data stored in the first storage means within all display digits including the display digits for displaying the exponent part data. A small electronic calculator characterized by comprising display means.