JPH0619758B2 - Numerical data input device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a numerical data input device capable of register correction.

A small electronic computer is generally provided with an AC (all clear) key and a C (register number clear) key, and all digits of the register data are cleared by operating either key. Some computers are provided with a so-called right shift key and the key operation allows the digit data to be cleared digit by digit from the least significant digit.

On the other hand, recently, a small electronic computer capable of inputting for each unit by using, for example, 100 million and 10 thousand keys has been put into practical use. Even in this type of computer, the AC key, C
All digits of the digit data are cleared by any operation of the key.Therefore, when correcting the digit data, you must re-register from the upper unit data, that is, from the beginning. However, the operation was very troublesome.

The present invention has been made in view of the above points, for example, in a small electronic calculator capable of inputting for each unit, it is possible to correct the numerical data of each unit, the numerical value that can be easily corrected input data An object is to provide a data input device.

An embodiment of the present invention will be described below with reference to the drawings. First
In the figure, reference numeral 1 denotes a key input section, including a numeric keypad 2, a function key 3, and unit keys 4a of "100 million", "thousand", and "ten thousand".
˜4c, unit clear key 5 is provided, and the key input data is sent to the control unit 6. Although not shown, the key input unit 1 also includes normal AC keys and C keys. The control unit 6 responds to a key operation in the key input unit 1 by inputting numerical data DA, a data input command IN, control signals a to f,
The flag conversion command TC or the like is output. Then, the numerical data DA output from the control unit 6 is input to the shift register 9 having, for example, 13 digits via the gate circuit 7 and the AND circuit 8. The data input command IN output from the control unit 6 is input to the gate circuit 7 as a gate switching signal, and the control signal a is input to the AND circuit 8 via the NAND circuit 10. Then, the shift register 9
Output of the AND circuit 12 is sent to the display unit 11.
Is sent to the gate circuit 7 via. AND circuit 12
Is gate-controlled by a control signal f provided from the control unit 6 via the inverter 13. On the other hand, the display unit 1
1 is "100 million" with digital display for numerical value,
The unit display of "10,000" and "thousand" can be displayed.
Further, the shift register 9 is adapted to take out an output between the lowest digit and its upper digit, that is, the point P,
The output is input to the AND circuit 14. This AND circuit 14 is gate-controlled by a control signal b from the control section 6, and its output is a 4-bit shift register 1
Input to 5. The shift register 15 includes a control unit 6
The shift control is performed by the control signal c from the first to fourth bits, and the outputs of the first to fourth bits are input to the AND circuits 17a to 17d in the flag conversion circuit 16. Further, the output of the second bit of the shift register 15 is the AND circuit 17a via the OR circuit 18a, and the output of the third bit is the OR circuit 18a.
AND circuits 17a and 17b via the 18b, and the output of the fourth bit via the OR circuits 18a to 18c.
It is also input to 7a to 17c. Also, the OR circuit 18a-
The flag conversion command T output from the control unit 6 is included in 18c.
C is input via the inverter 19. Further, the output of the inverter 19 is input to the AND circuit 17d. The outputs of the AND circuits 17a to 17d are input to the respective bits of the 4-bit shift registers 20 and 21 as the output of the flag conversion circuit 16. The shift registers 20, 21 have control signals d,
The shift control is performed by e. Then, the serial output of the shift register 20 is input to the shift register 9 via the AND circuit 22 which is gate-controlled by the control signal f from the control unit 6. The serial output of the shift register 21 is input to the NAND circuit 10 via the inverter 23, and the output of the NAND circuit 10 is input to the shift register 9 via the AND circuit 8.

FIG. 2 shows the details of the shift register 9. This shift register 9 is composed of 13 digits of D _{1 to} D ₁₃ , less than 1000 units of data in D _{1 to} D ₃ digits, data of 1000 units in D ₄ digits, data of 10,000 units in D _{5 to} D ₈ digits, D ₉ ~
D ₁₂ stores 100 million units of data.
And the _13th digit of D is a flag digit.
Flags F _{1 to} F ₄ for units of “thousand” and “less than a thousand”
Memorize

Next, the operation of the above embodiment will be described. Now for example third
FIG When the key input of the key input unit 1 than 123,400,000,000 as shown in (A) and row of ivy, numeric data "1234" is written in the D ₁₂ to D ₉ of the shift register, D ₁₃ most significant digits A flag F ₁ indicating the unit of “100 million” is written in the digit.
That is, when data is input from the key input unit 1, the control unit 6 outputs a data input command IN, and the gate circuit 7
Is switched to select the data DA from the control unit 6. Further, the control signal a output from the control unit 6 is "0" in the normal state, and therefore the output of the NAND circuit 10 is input to the AND circuit 8 as "1". Therefore, the data D output from the key input unit 1 via the control unit 6
A is written in the shift register 9 via the gate circuit 7 and the AND circuit 8. Further, the flag F ₁ is written in the D _13th digit of the shift register 9 by operating the billion key 4a. When the input data is written in the shift register 9, the data input command IN becomes "0", and the gate circuit 7 is switched to select the output of the AND circuit 12. The AND circuit 12 is connected to the inverter 1 from the control unit 6.
The signal f is controlled by a control signal f supplied via the signal No. 3, but this signal f is output only from the point P to the output of the D ₁ digit, that is, the output of the shift register 9 as shown in FIG. It is output only while the contents of D ₁₃ digits are output from the end, and the gate of the AND circuit 12 is closed. Therefore, of the data input to the shift register 9, the contents of D _{1 to} D ₁₂ are circularly held via the AND circuit 12, the gate circuit 7, and the AND circuit 8. On the other hand, at the timing when the content of D ₁₃ is read from the point P of the shift register 9, the control signal b is output from the control unit 6 as shown in FIG. 4, and the gate of the AND circuit 14 is opened. Further, at this time, as shown in FIG. 4, the control unit 6 outputs four shift clocks C corresponding to each bit of D ₁₃ digits. As a result, the contents of the D _thirteenth digit output from the point P of the shift register 9 are read into the shift register 15. The contents read into the shift register 15 are transferred to the shift registers 20 and 21 through the flag conversion circuit 16 as they are under normal conditions. That is, normally, the flag conversion command TC is not output, and the output of the inverter 19 is "1" and is given to the AND circuits 17a to 17d. Therefore, the contents of the shift register 15 are directly output to the AND circuits 17a to 17d. It is transferred to the shift registers 20 and 21 via the. Then, the data transferred to the shift register 20 is read from the shift register 20 by three clock signals d generated at the timing when the control signal f is output, and is read from the shift register 9 via the AND circuit 22. D is written in the _13th digit. The contents of the shift register 9 in this way, D ₁
.About.D _12- digit and D _13- digit are cyclically held through different circuits. Then, the data held in the shift register 9 is sent to the display unit 11 to display "123 billion" as shown in FIG. 3 (A).

Then, as shown in FIG.
Assuming that a key input of, 000,000 is performed, the numerical data "5000" is written into the shift register 9 in the D _{8 to} D _5th digits, and the unit of "10,000" is written in the D _13th digit. A flag F ₂ indicating that is written. Then, "123.45 billion" is displayed on the display unit 11.

Then, when the number data of "50 million" is entered and the number data is corrected, the unit clear key 5 is first operated as shown in FIG. 3 (C). When the unit clear key 5 is operated, the flag conversion command TC is output from the control unit 6 at the timing of T ₂ as shown in FIG. 4, that is, at the timing of reading the contents of D ₁ digit from the point P of the shift register 9. To be done. Then, the flag conversion command TC
Is output, the output of the inverter 19 becomes "0" and is given to the AND circuits 17a to 17d via the OR circuits 18a to 18c or directly. In this case, the data of the flags F _{1 to} F ₄ are written in the shift register 15 at the timing of T ₁ one digit before. When the units of "100 million" and "10,000" are entered as described above, the flags F ₁ and F ₂ are "1" and the flags F ₃ and F ₄ are "0". The content of the shift register 15 is "1100" from the input end direction. When the output of the inverter 19 becomes "0" in this state, the AND circuit 1
The gates of 7a to 17c are closed, and only the flag F ₁ is transferred to the shift registers 20 and 21 via the AND circuit 17a. That is, the flag conversion circuit 16 is adapted to convert only the lowest flag of the flags for which "1" is set to "0" and output it. Therefore, as described above, when the flags F ₁ and F _{2 in} units of “100 million” and “10,000” are set, the flag F ₂ for “10,000” becomes “0”, and the flag F for “100 million” is set. Only ₁ is shift register 2
0,21 are transferred. Therefore, the shift registers 20, 2
The content of 1 is "0001" when viewed from the output end.
Further, in the timing of the T _2, the control signal f is outputted together with the gate of the AND circuit 22 is opened, Shifutokurotsuku d is applied to the shift register 20. The contents of the shift register 20 are read by the shift clock d, and the D of the shift register 9 is read through the AND circuit 22.
Written in ₁₃ digits. After that, the control signal a is output from the control unit 6 during T _{3 to} T ₁₄ as shown in FIG. 4, and is input to the NAND circuit 10. On the other hand, the shift register 21
Indicates that the content of the most significant bit during T _{3 to} T ₅ , that is, the output data is “0”, is inverted to “1” by the inverter 23, and is input to the NAND circuit 10. Therefore, the output of the NAND circuit 10 becomes "0", and the gate of the AND circuit 8 is closed. Then, Shifutokurotsuku e from the controller 6 at a final timing of T ₅ is outputted, the contents of the shift register 21 is 1 Bitsutoshifuto. Even after this shift, the output of the shift register 21 is "0", and the gate of the AND circuit 8 is closed in the same manner as the above case.
Furthermore, Shifutokurotsuku e from the controller 6 at a final timing of T ₆ is output, but the contents of the shift register 21 is 1 Bitsutoshifuto, the output of the shift register 21 at this point is "0", the gate of the AND circuit 8 Close. This state continues until _{T 10,} Shifutokurotsuku e is outputted at the final timing of the _{T 10.} This shift clock e is used when different units of data are read out from the shift register 9, that is, D ₄ digit thousand unit data, D ₅
This is output when the ten-thousandth digit unit data and the _nine- thousandth digit D data are read out. When the contents of the shift register 21 are shifted at the reading timing of the hundredthousandth digit unit, the highest bit is flagged. F ₁ is shifted and its output becomes “1”. Therefore, the output of the inverter 23 becomes "0" and the output of the NAND circuit 10 becomes "1", and the gate of the AND circuit 8 is opened. Therefore, as shown in FIG. 3 (C), only 100 million units of data are circulated and retained, and 10,000 units of data are erased.

Then, as shown in FIG. 3 (D), the correction data, for example, 600
If you enter 00000, the registered number data "6000" is written in the _D 8 to D _5-digit shift register 9, the flag _{F 2} to "ten thousand" units is written to _{D 13.} In this way, the numerical data is corrected for each unit.

Then, the data input as described above is sent to a calculation unit (not shown) by a subsequent calculation command and processed.

In addition, in the above-mentioned embodiment, the case where it is implemented in the computer having the unit of "100 million" has been shown, but the case of having the unit of "trillion" can be similarly implemented. In addition, "100 million",
Not only a computer having a unit key such as "ten thousand", but also an ordinary small electronic computer can be implemented by correcting every three-digit or four-digit division. That is, in the above embodiment, a flag corresponding to each unit of 100 million, less than 1,000 is provided, and depending on the state of this flag, 4 digits, 4
The digit, 1 digit, and 3 digits are cleared, but not limited to this. For example, in an ordinary small electronic computer, even if the flag is not provided, the digit data is cleared in advance every 3 digits or 4 digits. You may do it.

Further, in the above-mentioned embodiment, the data correction for each predetermined unit is performed by the unit clear key (Ct key), but the present invention is not limited to this, and the clear key and the unit clear key are commonly used to clear the unit number and the unit. A clear key (for example, C / Ct) that clears the unit after operating ten million keys.
Key) may be provided.

As described above, according to the present invention, it is possible to correct the data for each predetermined unit, and it is not necessary to clear the digit data of all digits even if the number is erroneously entered, and the number of key operations required for correction is reduced. By doing so, it is possible to promptly correct the registered number.

[Brief description of drawings]

The drawings show one embodiment of the present invention. FIG. 1 is a circuit configuration diagram, FIG. 2 is a configuration diagram showing details of the shift register in FIG. 1, and FIGS. 3 (A) to (D) are keys. FIG. 4 is a timing chart for explaining the operation, and FIG. 4 is a diagram showing changes in the shift register and display contents with respect to the operation. 1 ... Key input section, 4a-4c ... Unit key, 5 ... Unit clear key, 9,15,20,21 ... Shift register, 11 ... Display section, 16 ... Flag conversion circuit.

Claims (1)

[Claims] 1. A key input means for inputting numerical data, a plurality of unit keys, and a delete key, and a unit key operated by operating the numerical keys of the key input means. Storage unit for storing in accordance with the unit of, a flag storage unit for storing a flag corresponding to each operation of the plurality of unit keys, operation of the erase key of the flag stored in the flag storage unit A numerical data input device comprising a flag of a unit key of the smallest unit and control means for erasing the numerical data stored in the storage means corresponding to the flag.