JPS6051730B2 - Display data conversion method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a display data conversion method for changing the display format of data including index data.

Conventionally, in a small electronic calculator having a mantissa data display section and an exponent data display section, the exponent data is increased or decreased by a fixed number each time a specific key is pressed, and the decimal point position of the mantissa data is also changed according to the number of changes in the exponent data. Changes are being made.

As described above, if the display form is changed by operating a specific key and the index data is set to a predetermined number, the magnitude of the numerical value of the display data can be determined at a glance. However, in the display data conversion operation in which 1 exponent data is decreased by a fixed number, as this operation is repeated, the number of digits beyond the decimal point of the mantissa data may exceed the number of digits in the mantissa data display section of the display section. At this time, there was an inconvenience that the upper digits of the mantissa data were erased. Furthermore, in a conversion operation in which exponent data is increased by a fixed number, significant digits of the mantissa data may be deleted from the lower digits as this operation is repeated. The present invention has been made in view of the above circumstances, and provides a display data conversion method that detects the decimal point position of mantissa data and prohibits the above-mentioned display data conversion if this value exceeds the limit. The purpose is to provide.

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit configuration diagram for explaining one embodiment of the present invention.

In the figure, 1 is a ROM (read-only memory), and this ROMI stores microinstructions for executing various operations of this computer/machine, and address signals output from the ROM address section 2. It sequentially outputs various microinstructions in response to the following. One microinstruction includes various signals SulFu. ．． sL,. FLNcO. ．． MlOp. N
a, each of which has a predetermined binary code fixedly incorporated therein.

Depending on the address designation of the ROM address section 2 of each binary code of the microinstruction, the microinstructions are simultaneously output as parallel signals. Su. The Fu signal specifies a row address of the RAM (Random Access Memory) 3, which will be described later, or one of the multiple registers provided in the RAM 3. is input to terminal UA of RAM3 via gate circuit G2.

The gate circuit G1 is a timing signal which will be described later! The gate circuit G2 is opened when the timing signal t1 is output.
Since it is applied via the inverter circuit 5, it is opened except when the timing signal is output. The timing signal ζ is sequentially and periodically output from the timing signal generating circuit 4 together with the timing signals T2 and t3 in synchronization with the clock pulses φ1 and φ2 shown in FIG. Further, from this timing signal generation circuit 4, the above-mentioned timing signals t1 to
The clock pulse φD is generated every 1 cycle (this 1 cycle period is referred to as 1 digit period in the following explanation).
(=T3·φ1) is also output. The SL and FL signals specify the column address of the RAM 3, that is, the digit of each register in the RAM 3, and are usually the column address S.
L is paired with the row address Su, and only the column address F is paired with the row address Fu.

The column address SL is input to the terminal LA of the RAM 3 via a gate circuit G3 that is opened when a timing signal beat is output from the timing decoder 9, which will be described later, and the column address FL is a timing signal output from the timing decoder 9. Gate circuit G that opens when Tb is output
4 to the terminal LA of the RAM3. The above-mentioned timing signals Ta and Tl are usually expressed by the logical formula Ta=M-
This is a signal obtained by ST+M-t1, T,=M·〒1. The details of the signals M and ST will be described later, but when an instruction whose execution time for one microinstruction ends in one digit period, the signal M outputs ゜゜1゛ during the output period of this microinstruction. The signal ST outputs "1" during one digit period during which each microinstruction is executed. Therefore, the above timing signal t and T5 are expressed as M=
1, TO=t1, Tb=U=T2+T3, and the address of RMA3 when the timing signal t1 is output is:
The address of RAM3 specified by the row address Su and column address S, and when the timing signal ~T3 is output, is:
It is specified by a row address Fu and a column address FL. In addition, when M=0, that is, when the execution time of a 1ma microinstruction spans a plurality of digit periods, Ta=ST, tb=
"゜0゛", and first, the row address signal supplied to the terminal UA of ROM3 from ROM1 is the timing signal t1.
At this time, the row address Su signal is supplied, and at the same timing, the row address Fu signal is supplied, and the registers of the RAM 3 are respectively selected. Also, the register digit selection at each timing mentioned above is based on the ROM.
Column address SL from l is sent to RA via gate circuit G3.
This is done by being supplied to the terminal LA of M3. On the other hand, at this time, the value of the column address S is preset to counters 5 and 6. This counter 6 receives a clock pulse φd (=φD
-M), and a one-count operation is performed in the up or down direction depending on the presence or absence of a signal DN, which will be described later. Therefore, the selection of digits after the first digit of the register is performed by sequentially inputting the output of the counter 6, which is updated every digit time, to the terminal LA of the RAM 3 via the gate circuit G5, which is opened by the timing signal Tc. It is specified. Also, the value of the count 6 is simultaneously supplied to one end of the match circuit 7, and specifies the value of the column address FL input to the other end of the ROM1 sort circuit 7, that is, the last digit of the register to be processed in this step. is compared with the signal. When the comparison values match, the matching circuit 7 outputs a sort signal, and the execution of this microinstruction is completed, as will be described later.
That is, in the case of a microinstruction that requires execution time for a plurality of digit periods as described above, the processing start column of the storage area (register) in RAM 3 specified by the row address Su or Fu is specified by the column address SL, and the processing end column is specified by the column address SL. The digit is specified by column address FL. In addition, the microinstruction is RA
At the time of a shift command to shift the data in the specified storage area (register) of M3 to the left or right, the above timing signals are Ta=t1, Tb=“0゛TO=chi・ST
becomes. Also, C of ROMl.

is generated as a code signal when a numerical symbol code consisting of binary codes such as numeric values and symbols is required inside the computer, and the gate circuit G is opened when the signal CI is output.
6. Further, M is a mode signal that outputs ゜゛1゛ when the microinstruction is an instruction that ends with one digit.

Further, 0p output from ROM1 is an instruction code for addition, subtraction, transfer, judgment, left shift, right shift, data output, data input, etc. This instruction code 0p is decoded by the operation decoder 8. , are input to the timing decoder 9.

This timing decoder 9 uses signals CI. OF. ．． OSllD. ．． K
E. ．． Selectively outputs SB etc. Further, timing signals Tl, t2, t output from the timing signal generation circuit 4
3 and clock pulses φ1, φ2, φD are gate circuit G
It is given as a timing signal to circuits such as 19G29Gll9Gl2 and so on, and is also input to the timing decoder 9. A mode signal M1 signal ST is also input to this timing decoder 9, and in response to this signal, the above-mentioned timing signal, and each of the above-mentioned commands, the timing decoder 9 further inputs a timing signal Ta. ．． tb. ．． tO and signal DN. , R/W1 clock pulse φA, φB, φC,
Selectively output φd. The above signals CI, OF, OS, ID
, KE are gate circuits G6, G7, G8, G9, respectively.
These are control signals for GlO, and when these signals are "゜1゛", the corresponding gate circuits are opened.The signal SB is input to the arithmetic circuit 16 and becomes a subtraction designation signal.The timing signals TO, t5, and tO are respectively , gate circuits G3, G4,
It is input to G5 and becomes the aforementioned control signal. The signal DN is sent to the counter 6 and becomes a signal specifying a down-count operation. Signal R/M is sent to RAM3 and read/
This is a signal specifying writing. Signals φA, φB, φc
are given as clock pulses for reading buffers Bl, B2, and B3, respectively, and expressed as a logical formula, φa
=φo・0P1? φb:φDOOP29φC:T2φφ
There is one. However, 0P1 = decimal point display data output command, 0
P2 = display data output command, key sampling pulse and digit drive pulse output command, signal φd is the counter 6
It is the operation signal of
-To? +φ1・0P3. However, 0P3 = shift command. Further, the mode signal M is inputted as an enable signal to the coincidence circuit 7 via the inverter circuit 10 and also inputted to one side of the AND circuit 11. The coincidence signal from the coincidence circuit 7 is inputted to one side of the AND circuit 12. Further, the mode signal and the coincidence signal from the coincidence circuit 7 are inputted to the flip-flop circuit 14 via the OR circuit 13. This flip-flop circuit 14 operates in synchronization with a clock pulse φD at digit intervals, and outputs a signal ST for one digit period to the timing decoder 9. Also,
A clock pulse φD is input to the other of the AND circuits 11 and 12, and the output signals of the AND circuits 11 and 12 are outputted as a signal φe via an OR circuit 15 and serve as a read clock for the address conversion circuit 17. Also, N
a is the address code of the microinstruction currently being executed in ROM1, and is input to the address conversion circuit 17. This address conversion circuit 17 further includes AND circuits 18 and 19.
The output signal of is input. One of the AND circuits 18 receives data from the arithmetic circuit 16, one of the AND circuits 19 receives a carry (or borrow), and the other of the AND circuits 18 and 19 receives the signal Ju from the timing decoder 9. ing. This signal Ju is output at the time of a judgment command, and at this time, the address conversion circuit 17
The contents of the address code Na and the output signals of the AND circuits 18 and 19 are OR-added to calculate the address that specifies the next two steps of microinstructions in the ROM1.
It is sent to the address section 2. Next, the configurations of the ROM 3, arithmetic circuit 16, etc. controlled by the microinstructions of the ROM 1 will be explained.

Column address number O~1 input to terminal LA of ROM3
In step 2, the storage area in the RAM 3 designated when the row address ROJ is input to the terminal UA is called a register A. Furthermore, the column address is RO~12, and the row address is 1.
1J. , r2. j. The memory areas in RAM3 specified by r3, 14, and R5 are stored in register B, respectively.
1 register C1 register D1 register E1 register F. That is, each of the above registers has a storage capacity of one register up to ROj-Rl2. The RAM 3, which is composed of the above registers, stores the row address S input to the terminal UA.
u. ．． It is input to Fu and terminal LA. column address S,
, FL, and when the signal R/W=゜゜0゛, the data within the specified address is output terminal 0.
Read as parallel 4-bit data from UT, R/W
="1", the parallel data applied to the input terminal 1N is written into the specified address.Normally, the above signal R/
W is the timing signal signal ~ Read at the time of T2 output (R/W
= “゜0゛)”, and write (R/W=゜“1゛) is specified when the timing signal T3 is output. Furthermore, since the gate circuits G1 and G3 are normally opened when the timing signal t1 is output, at this time, the data in the RAM3 specified by the row address Su and the column address S is read out from the output terminal 0UT. , timing signal t1・φ
Latch 2 via gate circuit Gl2 that is opened when 1 output
Stored as 0. Furthermore, since the gate circuits G2 and G4 are normally opened when the timing signal T2 is output, first, when the timing signal T2 is output, the data output terminal 0UT in the RAM3 specified by the row address Fu and the column address F is output. The timing signal is read out from the timing signal φ1.
The signal is stored in the latch 21 via the gate circuit Gll, which is opened at . Furthermore, the data applied to the input terminal 1N is written into the RAM 3 specified by the row address Fu and column address FL when the timing signal T3 is output. The data stored in latches 20 and 21 are gated by gate circuits G8 and 0F, respectively, which are opened by signals 0S and 0F.
The signal is sent to input terminals S and F of the arithmetic circuit 16 via G7. The arithmetic circuit 16 performs addition in parallel based on data given to input terminals S and F. Or perform subtraction. The designation of addition and subtraction is performed by the signal SB, and addition is performed when SB=゜゜0゛, and subtraction is performed when SB=゜゜1゛.
The above calculation result data is output in parallel from terminal D, and RA
The signal is applied to the input terminal 1N of M3, and is also input to one side of the AND circuit 18 via the OR circuit 22. Further, the carry (or pollo) of the arithmetic circuit 16 is output from the terminal C and input to one of the AND circuits 19. Also, 1 of register F, which will be described later, in the storage area in AM3 mentioned above.
When the digits are displayed and key sampled, the arithmetic circuit 16
, and after reaching the numerical value ROJ, a specific value is stored and used as a circulating count digit.

The value of this count digit is determined by gate circuit Gl2 and latch 20.
, the value of the count digit is read in the buffer B3 via the gate circuit G8 in synchronization with the clock pulse φc. This buffered value is output via the decoder 23 as a digit driving pulse for the display section 24 and as a key sampling pulse for the key input section 25. Also, RAM
Register C in 3 stores display data, and when displaying this data, the value of the count digit is first read out when the tandem timing signal is output, and this value is sent to gate circuit Gl2, latch 20, and gate RA via circuit G9
This is input to the LA of M3, and this becomes the column address of RAM3. At this time, the row address specifies register C, and therefore, data in a predetermined digit of register C corresponding to the value in the count digit is read out when the timing signal is output, and this data is sent to gate circuit Gll, latch 21, It is applied to buffer B2 via gate circuit G7. Buffer B
2 reads the given data in synchronization with the clock pulse φb, and further sends it to the display section 24 via the decoder 26.As mentioned above, the display section 24 has the decoder 24.
As a result, the contents of the same digit of the register C are displayed in the digits of the display section 24 indicated by the contents of the count digit. Also,
Buffer B1 reads decimal point data from register D for decimal point display in synchronization with clock pulse φa, and further sends it to display section 24 via decoder 26, where it is displayed in the same manner as described above. The key input section 25 also connects the line to which the key sampling pulse is supplied and the buffer B4.
The key common lines output to the buffer B4 are arranged in a matrix, and each line has a key at the intersection.The key common data input to the buffer B4 by key operation is the signal XE output at the time of a data input command. is input to the terminal S of the arithmetic circuit 16 via the gate circuit Gl2 that opens at
Further, the data is written from the terminal D of the arithmetic circuit 16 to a predetermined area via the input terminal 1N of the RAM 3. If the key common data of the buffer B4 is present within this predetermined area, the counting operation of the count digit is stopped, and the operation key is determined based on the count value at this time and the data of the buffer B4. If it is a numeric key, the numerical data corresponding to that key is input to the display register C, and if it is a function key, the address code Na of ROM1 is input to the ROM address section 2 via the address conversion circuit 17 based on the judgment result. microinstructions for performing predetermined processing are sequentially output. The key input section 25 includes numeric keys for inputting numerical values, function keys for instructing the start of various calculations, and a conversion key [25a and reverse conversion key] for converting display data into a specified exponential format. It has country 25b. FIG. 3 shows the storage area of each register in the RAM 3. The i-th storage area of register A (7) is indicated by Ai. However, i is an integer from 1 to 12. Similarly, the i-th digits of registers B, C, D, E, and F (7) are indicated by Bi, Ci, Di, Ei, and Fj, respectively. AO-
AIO stores inputs, answers, operands, etc., and among these, A3 to AIO store exponent data Ex, and A3 to AIO store mantissa data. All stores a flag F indicating that the conversion key [ has been operated, and Al2 stores a flag I indicating that the reverse conversion key (1) has been operated. 8-BIO stores the calculation number, DO-DlO stores display and calculation auxiliary data, and DO-DlO stores decimal point display and calculation auxiliary data. Bll~Bl2, Cll~Cl. stores various flags during the performance, but the details are omitted. EO2 stores decimal point data Dp, and E3 to El2 and register F store other data. The operation of the present invention will be explained below.

FIG. 4 shows the display state of the display section 24. First, as shown in FIG. 4, mantissa data Rl2345678
and index data ROOJ are displayed. This display operation is performed in process a shown in FIG. That is, the display data of the mantissa and exponent parts are stored in register C of the RAM 3, and this register C(7) CO-C2 digits are 700, and C3 to ClO digits are R12345678. On the other hand, the decimal point display data is R. AM3 register D
(7) Stored in the 6th digit of D. Therefore, in the above process a, Su (=5), SL (=12) from ROM1
With the register specification instruction and the R/W instruction, at the timing t1, the count value of the counter that counts up sequentially with a constant cycle of the first register F in RAM3 and circulates at a specific value is read out, and the gate Circuit G
12, the latch circuit 20, and the gate circuit G8, the data is stored in the buffer B3 at the timing of the signal φc. If the count value is, for example, RlOJ, the data in the buffer 8 is output as a first digit driving pulse of the display section 24 via the decoder 23, and is also supplied to the key input section 25 as a key sampling signal. At the same time, the value RlOJ of the count digit is input as a column address, that is, a digit designation signal, to the terminal LA of the RAM3 via the gate circuit G9, and at this time, the value Fu (=2) from the ROMl is inputted to the terminal UA.
A signal is input via gate circuit G2 at timing T2. Therefore, at the timing of T2, Fu(
The data in the register C(7) ClO (10th digit) specified by =2), that is, the display data RlJ, is read out and buffered at the timing of the signal φb via the gate circuit Gll, latch 21, and gate circuit G7. It is input to B2.
This data 10. u is output from the buffer B2 at a predetermined timing, converted into a segment code by the decoder 26, and then sent to the display unit 24. Also, register D (7
) The data in DlO, that is, the data for the decimal point, is transferred to the buffer B1 in another step in the same manner as the display data described above.
and sent to the display unit 24 via the decoder 26. As a result, the numerical value 11 is displayed on the display section 24 in the first order of the display section 24 based on the first order digit drive pulse and the display data. O because DlO does not have decimal point display data.
No decimal point is displayed in the digit. In the next step, a signal KE for opening the gate circuit GlO is output, and a key common signal based on the sampling signal [output signal of the decoder 23 corresponding to the count value RlO] supplied to the key input section 25 from the buffer type described above is output. It is detected whether data exists in buffer B4 or not. If the key common data is not present, the next step is to perform the same operation as described above, and the count value of the 12th digit of register F in RAM3 is The value of the count digit read out again is counted down by the arithmetic circuit 16 to 19, and the above-described series of operations is performed again. At the same time, the data in C9 and D9 are sent to the display section 24 and displayed at the ninth digit of the display section 24. Below, the value of the count digit is counted down,
When the value is equal to the lowest digit of the display section 24, in the next counting step, the borrow is detected by the arithmetic circuit and the signals from the output terminals D and C of 16, and this signal is passed through the AND circuits 18 and 19. ROM to the address conversion circuit 17.
The C of ROM1 is read with the Na signal of ROM1 by its addressing signal. Outputs the code signal RlOJ and selects R specified by Fu (=5) and F (=12).
At the timing after the 12th digit of the register F of AM3, it is written via the arithmetic circuit 16 and the numerical value 110 is again preset, and the same operation as described above is repeated. In process a described above, if a key on the key input section 25 is operated and key common data for that key is detected in the buffer B4, the operation of process a is interrupted and a predetermined process corresponding to the operated key is executed. For this process to take place, press the
Descriptions of the operations other than the country key operation will be omitted since they are not the gist of the present application. When the P key 25a is operated, a process b to be described later is performed, when the country key 25b is operated, a step c is performed, and when the operation of the process b or step c is completed, the operation of the process a is performed again. Next, the operation of process b will be explained with reference to the display data conversion flow shown in FIGS. 6 and 7.

In the state shown in FIG. 4, register A stores the same data as register C, and registers E(7) EO-2 store data Dp=6 indicating the display position of the decimal point.
First, in step d, A. C for the index data Ex=0 within ~2. Transfer to ~2. The microinstruction for the transfer operation shown in step d is Su=0, FU=2, SL=0
, FL=2, M=0, 0P=transfer, Na=address of step d. That is, when the timing signal T3 of the first cycle is output, input data ROJ specified by SU and SL is read out to the latch 20 via the gate circuit Gl2, and when the timing signal T3 is output, the data in the latch 20 is read out from the gate. Through the circuit G8 and the arithmetic circuit 16, Fu
(=2), C specified by SL (=0). That is, R, AM
3 is written to the 0th digit of register C. Also, the above SL
(=10) is simultaneously sent to the counter 6 and preset. Its output. The signal is input to the other input terminal of the coincidence circuit 7 via a gate circuit G5 which is controlled by the signal. At this time, one input terminal of the matching circuit 7 has ROM1.
2F (=R2J) is input, and the two are compared to see if they match. In this case, since the two do not match, no match output is output from the match circuit 7, and the contents of the address conversion circuit do not change, so the various signals output from ROM1, SU
, FU, SL, and F remain unchanged. Then,
In this cycle, the contents of counter 6 are changed to + by signal φD.
1, and its value becomes 11J. Then, at the timing signal t1 in the next cycle, the contents of the counter 6 (supplied to the terminal LA of the RAM3 via the gate circuit G5) and the signal Su (=0) from the ROM1 are used to store the register in the RAM3. The first digit of A, ie A1, is specified. Then, data 10J in this A1 is read out from RAM3 by the R/W read signal, and gate circuit G
l. The data is stored in the latch 20 via the latch 20. When the timing signal T3 is output, the signal Fu output from the ROM1
[=12jo (specifies register C)] Contents 1 of counter 6
1J (designating the first digit) and the write signal W are supplied to the RAM 3, whereby the data 10J stored in the latch 20 is written to the register C(7)C1 via the gate circuit G8 and the arithmetic circuit 16. It will be done. At this time, the counter 6 counts up in the same manner as described above, and its contents are 12. Then, the next cycle begins. Then, as described above, the data in A2 is written to C2, and at the same time, the match circuit 7 outputs the sort signal, and this signal is passed through the AND circuit 12 and the OR circuit 15 as the read clock φe to the address conversion circuit 17. is applied to As a result, the signal is applied here in the address conversion circuit 17. According to the address signal Na for the next step from ROM1 and the signals from AND circuits 18 and 19, the address contents are updated, step d is completed, and the process proceeds to the next step e. In this step e, the data (Dp=6) from the Oth digit to the second digit of the register E (7) in the RAM 3 is transferred to the Oth digit to the second digit of the register D (7). Since this operation differs from the operation in step d above only in the designation of registers to the RAM 3, a detailed explanation of the invention will be omitted. When this step e is completed, the process proceeds to the next step f. In this step f, it is determined whether the conversion key for converting display data into a predetermined exponential format is operated, and it is determined whether the flag code F is stored in the 11th digit of register A. It is something to do.
In this case, since the conversion key has not been operated before, the flag ● code is not stored. The various microinstruction signals output from ROM1 for the judgment operation shown in step f are Fu=0, F=11, CO=
F. ．． Outputs M=1, 0p=judgment instruction code, Na=address of step t. The instruction code for the above judgment is sent to the timing decoder 9 via the operation decoder 8.
From this timing decoder 9, the gate G
Signal 0F controlling gate C7
1 subtraction command SB, judgment signal JUL read/write signal R
Various control signals such as /W are output. For this reason, first,
The 11th digit of register A of RAM3 is specified by Fu and FL, the data 10 of the 11th digit is read from the 0UT terminal of RAM3, and at the timing of T2, gate circuit Gll and latch 21, T via gate circuit G7
It is input to the terminal F of the arithmetic circuit 16 at timing 3.
On the other hand, at this time, C of ROM1. A binary code corresponding to the flag F is outputted and supplied to the S terminal of the arithmetic circuit 16 via the gate circuit G6. Since this arithmetic circuit 16 is designated for subtraction by the signal SB, the arithmetic circuit 16 converts the flag code data input to the terminal S from the 11th digit data RO of the register A input to the terminal F. Perform subtraction and perform subtraction jersey. As a result, in this case, numerical data is output from the terminal D of the arithmetic circuit 16 from (0-F), and a carry (or borrow) is output from the terminal C. OR circuit 22 according to the above numerical data
and an AND circuit 1 to which the signal JU is input.
8 as a judgment signal to the address conversion circuit 17, and the carry (or borrow) is input as a judgment signal to the address conversion circuit 17 through an AND circuit 19 to which the signal JU is input. Ru. As a result, the address conversion circuit 17 converts the address signal output from Na of ROM1 and the AND circuits 18, 1
An address signal for the next step is supplied to the ROM address section 2 based on the address signal based on the determination signal from 9. In this case, it is determined that the flag code F is not stored in the 11th digit of register A, and the process proceeds to step g.Also, if the conversion key P is operated, When flag code F is stored in the 11th digit, neither numerical data nor carry is output from the arithmetic circuit 16 during subtraction by the arithmetic circuit 16. As a result, it is determined that there is a flag code, and the address conversion circuit 17 converts the next step address signal to RO based only on the address signal output from Na of ROM1.
The data is supplied to the M address section 2, and the process proceeds to step t. In this case, the process proceeds to step g, but in step g, in order to remember that the conversion key [ has been operated, the corresponding flag code RF is stored in the 11th digit of register A. Perform the action. Various signals accompanying the microinstruction from ROMl output in step g are Fu=0, FL=11, CO=code RF, M=゜゜1-0p=numeric symbol code input instruction, Na=
This is the address code of step h. In response to the above 0p, the timing decoder 9 outputs the signal CI, R/W signal, etc. By the various signals mentioned above, first the C of ROM1 is
. A code RFJ (for example, RllOO) is output from the circuit and is supplied to the terminal 1N of the RAM 3 via the gate circuit G6 and the arithmetic circuit 16. On the other hand, the signal Fu from ROM1
(=0) and F (=11) specify the 11th digit of register A in RAM3. As a result, the code RFJ is written to the 11th digit of the register A by the write signal W applied to the RAM 3 at the timing T3. Then, proceed to the next step h. Below, in order to briefly explain the operation of each step, explanations regarding various signals output from ROM1 will be omitted unless the operation is different from the above-mentioned contents, that is, transfer, code writing, and subtraction operations. Explain.

In this step h, the 0th to 2nd digits of register E are E.

Decimal point data ROO6 within ~2 (i.e. data R6)
is read out to terminal F of the arithmetic circuit 16 for each digit, while C of ROM1 is read out to the terminal S of the arithmetic circuit 16. More numerical RO
lOJ (that is, data RlO.J) is sequentially supplied to 10
-6=4 is subtracted, and data ROO4 becomes E. ~
Written to 2. In the next step i, the register E
Decimal point data E.・~2 and index data A of register A
. .about.2 is performed and the result is written into the exponent data storage section of register A. That is, index data RO. of register A. J is read out from RAM3 at the timing of (the exponent data of register E) R4J is read out at the timing of T2, and each gate circuit Gl2
, latch circuit 20, gate circuit G8 and gate circuit G
T3 is input to the terminals S and F of the arithmetic circuit 16 via the latch circuit 21 and gate circuit G7, respectively.
At this timing, the arithmetic circuit 16 performs the addition of R4+0J, and as a result, R4 is stored in the exponent storage section A of the register A of the RAM 3. ~2 is written. Then, proceed to the next step j. In this step j, it is determined whether the data in the exponent storage section 1-2 of the register A is greater than R99. In this judgment, if exponent storage part A of register A. If the data within ~2 is larger than 199, it will exceed the 2 digits on the index display section of the display section 24, so
Its contents cannot be displayed. In such a case, the present invention prohibits the conversion key from being pressed after this, and temporarily saves it to register C (7) CO ~ 2nd digit and register D (7) DO ~ 2nd digit in step d and step e above. The exponent data from register A (7) AO to the second digit and the decimal point data from register E (7) EO to the second digit are returned to each register A1 and E, and the conversion key (G) is not operated. , so that it is displayed. For this purpose,
After the above judgment, the process proceeds to step 1, and in this step 1, contrary to step d, registers C(7)CO~2
Transfer the contents of the digit from register A (7) AO to the second digit to the second digit of register A (7) AO, and proceed to the next step m.
At step e, the contents of register D (7) DO to second digit are transferred to register E (7) EO to second digit. Then, in the next step n, which will be described later, 10 is written in the first row of register A, that is, after clearing flag I, which will be described later, the current conversion key (
g) Display the original state before the operation. Therefore, in the above example, in step i, register A (7) AO
Since the data within ~2 is R4J, it is determined to be smaller than 199J, and the process proceeds from step j to step k. In this step k, as shown by 2 in FIG. 4, the register E of the register E stores the data of the decimal point display digit position so that the decimal point is displayed at the first position of the display digit. ~Number Rl in second digit
0 is written and the process advances to the next step o. In this step o, each data stored in digits AO-AIO of register A (7) is stored in each digit C of display register C. -ClO
will be forwarded to. In the next step p, the decimal point display digit position of register E is stored. A judgment is made as to whether the data in ~2 is greater than 10, and if it is greater than RlOJ, the process proceeds to the next step q, where the mantissa display data of register C is stored. C3 to C10 are for one digit. It is shifted to the right and proceeds to the next step r. In this step r, the numerical value RL is subtracted from the 1 decimal point display digit data within the register E (7) EO to 2 digits, and r1 is again subtracted from the step data.
is subtracted, and the process returns to step p. That is, the above E. The above steps P, q, r are repeated until the decimal point display digit data within 2 becomes less than or equal to the maximum display digit RIO of the display unit
The following actions are performed. At this time, the signals output from ROM1 in response to the microinstruction in the right shift operation of step q are FU=2, SL=3, FL・=10, M=
゜゜0゛, 0p = right shift command, Na = address code of step r. Then, upon receiving the instruction code 0p, the timing decoder 9 outputs the signal 0F and Ta=
Control signals such as t1, TO=t1·STlφd=φ1, DN=T2, and timing signals are output to control various gates. That is, the operation during the first 1-digit period during which this step is executed, the timing period from t1 to ζ, is performed when the above-mentioned SL=
3 counts down at counter 6 [chi・φ1, (t1
+T3)・φ, to count up],
Here, the count is increased by +1, and the count value of counter 6 is 14. is input to the terminal LA of the RAM 3 via the gate circuit G5 and fed back to the counter 6 again. At this timing of T2, the fourth digit C of register C in RAM3, which is addressed by FU=2 and the count value R4 of counter 6, is
4 data is read out from RAM3, and the data of gate circuit Gl is read out from RAM3.
It is stored in latch 21 via l. On the other hand, at this time, the counter 6 is counted down by 0-1 by the clock signal of φ1, and the count value is R3! becomes. Then, at the next timing signal T3, the value of the counter 6 is 1.
The output of 33J is input to terminal LA of RAM3 via gate circuit G5. At the same time, RAM3 has ROM1
Therefore, the signal FU=2 and the write signal W are also applied.
The fourth digit C of the register C stored in the latch 21 at this time. The data of gate circuit G7 and arithmetic circuit 16
is supplied to the input terminal 1N of R and AM3 via
The data of the fourth digit C4 is written into the third digit C3 of the register C of No. 3. That is, the one digit period t1 to T
3, the data in the fourth digit C4 of register C is shifted one digit to the right to the third digit C3. Also, at the timing of T3, the counter 6 is set to 0+1 by the clock signal φ1, and the count value becomes R4J. Then, in the next digit period, at the timing t1, first, at the timing t1, the counter 6 increases by +1 in the same way as above.
It is counted up and the value is set to 15, and the signal of this value is R through the gate circuit G5 at the next timing T2.
It is supplied as a column address signal to terminal LA of AM3.
As a result, the data in the fifth digit C5 of the register C is read out, and its contents are held in the latch circuit 21 in the same manner as described above. Also, at the timing of T2, the value of the counter 6 counts down by 1-1, and becomes R4j. Then, at the next timing, the signal of the value of R4J is supplied to the LN element of RAM3 via the gate circuit G5, and at this time, the data of the fifth digit C5 of the register C read out at the same time. is from the latch circuit 21 to the gate circuit G7,
The signal is supplied to the terminal 1N of the RAM 3 via the arithmetic circuit 16. As a result, the data in the fifth digit C5 of the register C is written into the fourth digit C4. Similarly, the contents of the sixth digit C6 to the first Cf1 ClO of the register C are shifted to the right one digit at a time. Then, when the value of counter 6 becomes RlOJ and becomes equal to FL=10,
A coincidence signal is output from the coincidence circuit 7. This coincidence signal is input to one side of the AND circuit 12, and this AND circuit 12
The clock pulse φ is input to the other side of the clock pulse φ. (=T3・
φ1) is applied as a read clock pulse to the address conversion circuit 17 via the OR circuit 15. As a result,
The address signal of the next step r outputted from Na of ROM1 to the address conversion circuit 17 is read, and step q is completed. In this case, in step p, the 0th digit to the 2nd digit E of register E.
The upper 2 decimal point display digit data Dp is 1Dp from RIO.
If it is determined that ≦10, the process proceeds to the next step s. In this process s, corresponding to the value RIO of the decimal point display digit data Dp stored in the upper two digits of the register E (7) EO,
Write the decimal point display data to the first digit DlO of register D. This completes the display data conversion glow, and the process a.
Then, the data in register C and the decimal point display data in register D are displayed on the display section 24 as shown in FIG. 42. That is, by operating the conversion key (g) for the first time, the normal display state of only the mantissa as shown in FIG. , there is an advantage that the magnitude of the displayed data can be easily determined from the value of the index data. Next, the operation when the conversion key (g) is operated will be further explained.

First of all, conceptually, when the conversion key P is operated for the second time, the exponent data before this conversion key is operated is changed to the decimal point display digit data of the mantissa part until it becomes a smaller and nearest multiple of 3. Subtract.

That is, in the display state on the display unit 24, the decimal point position is shifted to the right by the number of digits. In each subsequent operation of the old conversion key, the exponent data, which is a multiple of 3, is incremented by 1-3J, and the decimal point position of the mantissa is shifted to the right by 3 digits. .
This operation will be explained in detail below. The second time? When the key is operated, steps d1 and e1 in FIG. 6 are performed, and the 0th digit to the 2nd digit A of register A.

~2 exponent data Ex=4 is in register C(7) CO~2
To digit, register E (7) EO ~ 2 digit decimal point data Dp=
10 is D. ~ Saved to 2 digits. After this, the process advances to step f, and in this step f, a flag F is used to store that the conversion key ``was operated before the 11th digit of All register A.
In this case, the second D
Since this is a key operation, there is a flag F, and the process advances to the next step t. In this step t, the first ? Row A
A determination is made as to whether or not there is a flag I in l2 that stores whether the reverse conversion key 1 has been operated before. In this case, (1) the key has not been operated yet, so the first lucid eye Al
Flag I is not detected within 2, and the process proceeds to the next step u. In this step u, the 0th digit to the 2nd digit A of register A. A judgment is made as to whether or not the index data Ex of ~2 is smaller than 0-99, which is the maximum number of negative-side index data that can be in the calculation state, and if the index data Ex is 0-99.
When it is smaller than J (for example, EX=-100), this calculator cannot display it. At this time, use the conversion key [
In order to return to the state before it was operated, proceed to step 1..m in the same way as '' mentioned above, and then go through each step o-s from step n onwards, so that the previous contents are displayed. , even if the subsequent conversion key (g) is operated, the conversion operation is not performed. In this case, the exponent data is Ex = 4, so the process goes to the next step (2). In this step v, the register E(7) EO - It is detected whether the 2-digit decimal point data Dp is larger than 13 yo.This number R3J is the lowest display digit of the mantissa data, and if the decimal point data Dp is smaller than R3J, the mantissa data The decimal point cannot be displayed on the display section. Therefore, when it is determined in step v that the decimal point data Dp≦3, the process proceeds to steps 11 and m in the same way as described above, and in steps d and e, the register C ( 7) CO~
2 digits and D. Each data saved to ~2 digits is returned to register A (7) AO~2 digits and register E (7) EO~2 digits and the process proceeds to the next step n, and the steps o to s described above are repeated. conversion is performed, and no conversion of display data is performed. Therefore, in this case, register E(7) EO~
Since the two-digit decimal point data Dp is RlO, the process proceeds to the next step w. In this step w, the 2-digit exponent data Ex (=4) of the register A is read out, and the arithmetic circuit 16
At , the above contents are subtracted by -1, and the contents are again written into the AO to 2 digits of register A (7). That is, the exponent data Ex of register A (7) AO to the second digit becomes 13. Then proceed to the next step x, and this step x
E of register E. ~2-digit decimal point DP (=RlOJ)
is subtracted by -1, and R9 is stored. Then, the process proceeds to the next process y, and in this process y, the register A (7) AO~
3 is added to the absolute value of the two-digit exponent data Ex, and the result of this addition is stored in register F(7)FO~2 digits. In the next step z, the data stored in FO~2 digits of register F is read from RAM3. Then, it is determined whether this data is a multiple of 3 or not. That is, the data of 2 digits from register F(7) FO is read from RAM3 at the timing of T3, and the gate circuit 11 and latch circuit 12
, is supplied to the terminal F of the arithmetic circuit 16 via the gate circuit G7, and C of the ROM1. The code ROOll, that is, the value R3 is output, and supplied to the terminal S of the arithmetic circuit 16 through the gate circuit G6. data) −
3] and store this result in the register F above. ~Write in the second digit. And F of register F again. -Read the contents of the second digit and determine whether the subtraction result is positive or not. (This judgment is made, for example, depending on whether the sign code stored in the second digit of F.~2 digits is a positive sign or a negative sign.) From the above register F (7) FO ~ 2 digit data, repeat the numerical value R3.
Repeat the operation of subtracting J, and if it is negative, the numerical data in the 2nd digit from register F(1) FO is
It is determined whether or not Oj. Therefore, this result is RO
If it is determined that the data is a multiple of R3J, the data stored in the register F(7) FO to second digit is a multiple of R3J. In this case, the process advances to the jth step n. In addition, if the above result is determined to be numeric rather than RO, that is,
The result of the above subtraction is a negative number, and the above data is not a multiple of 3. In this case, the process returns to the above step t, and the F of the above register F is set. A series of operations from step t to step z are repeated until the data stored in the second digit becomes a multiple of R3. In the above embodiment, in step w, register A (7) AO to second digit exponent data Ex is a multiple of 3 than the value R3, so in step z, R
It is determined that the number is a multiple of 3, and the process proceeds to the above-mentioned step n, where 10 is written in the first row of register A, that is, I
After clearing the flag, the display as shown in FIG. 4 is displayed in process a after the above-mentioned steps os. That is,
The exponent data is 13, and a decimal point is displayed in the ninth digit of the display section 24. Next, when the conversion key position is operated for the third time, the same operation as the operation when the conversion key [ is operated for the second time is executed, and the process proceeds to step df, and then step t-
The above exponent data Ex and decimal point data Dp in z are 1
When it is detected in step z that the index data Ex is a multiple of 3, the following steps ns are performed, and in process a, as shown in FIG. is 10.0J, and the decimal point is displayed in the sixth digit of the display section 24.

At the next fourth key operation, each operation is executed in exactly the same manner as above, and the display is displayed as shown in FIG. 4. In this case, the index data is 0-03J and the decimal point is displayed in the third digit of the display section 24. At this time, if you further operate the key, step v of the series of step operations will be executed.
Then register E (7) EO ~ 2-digit decimal point data Dp is R
3J, and as described above, the operations following step l are performed, and no further conversion of display data is performed. Next, when converting the data converted as described above back to its original state, for example, inverse conversion key 1
This is done by operating the conversion key OLD after operating .

First, when the ■ key is operated, a flag I is written into the 12th digit Al2 of the register A, as shown in step C in FIG. 5, to indicate that the ■ key has been operated. Then, when the conversion key P is operated, steps df are performed, and then the process proceeds to step t. In this step t, Al. It is determined that there is a flag ■, and the process proceeds to the next step i1.
In this step i1, it is determined whether the exponent data Ex within 2 digits of register A(7) AO is greater than R99J. However, in the above example, since Ex=-3, the process proceeds to the next step I2. In this step I2, the decimal point data Dp within 2 digits of register E (7) EO is Rl6.
A determination is made as to whether or not it is smaller than . When Dp=16, DP=10 as shown in steps pr below.
The mantissa data in digits 3 to 10 of register C (7) C is lowered until the upper 2 of the mantissa data
The digits are displayed in the third to fourth digits of the display section 24,
For this reason, when Dp=116j, the process proceeds from step J2 to step 1, m and below, so that the mantissa data is not erased. Also, if Ex is determined to be greater than 199 in step i1, step i1,
m or less operations are performed, and the display data conversion operation is stopped immediately before the index data overflows. Therefore, in the above example, step J2 is E. ~2 data Dp is R
3! Therefore, the process proceeds to the next steps I3 and i4. In steps I3 and I4, RlJ is added to the exponent data Ex and decimal point data Dp, so that Ex=-2 and Dp=
It becomes 4. Next, the process advances to steps Y and z, where it is determined whether the index data Ex is a multiple of 3 as described above, and if it is not a multiple of 3, the operations following steps T and il described above are performed. When the above exponent data Ex becomes Ex=0, the data in the second digit of register F (7) FO becomes F in step y. ~2
= 3, and in the next step z it is determined that it is a multiple of 3, and thereafter the operations from step n onwards are performed. At this time, the decimal point data is Dp=5, so in process a, FIG.
It will be displayed like this. Thereafter, the above-mentioned operation is performed for each consecutive operation of the reverse conversion key box and the conversion key old, and
, 9, R3J is sequentially added to the exponent data Ex, and the decimal point position of the mantissa data is also moved to the right by three digits in correspondence with the exponent data Ex.

In the state shown in FIG. 4, the exponent data Ex within 2 digits of register A (7) AO is R9, and register E (7) EO is
Decimal point data Dp within two digits is Rl5J. If the country key and P key are further operated in this state, Ex added in step I4 will be Rl6. When this happens, it is determined in step I2 that EX=16, and thereafter the operations from step 1 onwards are performed. That is, from now on, even if the reverse conversion key (1)
, even if the conversion key country is operated continuously, the display data will not be converted and the display data will remain in the state shown in FIG. 4 and 9. In addition, the means for prohibiting the conversion of display data as used in the present invention refers to a method in which the position of the decimal point of the mantissa data protrudes beyond the display digit of the mantissa data display section by pressing the conversion key or by sequentially operating the inverse conversion key ■ and the conversion key [. In this case, it goes without saying that all means are intended to assume that a specific key such as the conversion key (g) or reverse conversion key country has not been operated. Although the index data is changed by ±3, it is of course possible to set any value without being limited to this.

Furthermore, in the above embodiment, an example was shown in which a conversion key position and a reverse conversion key ■ were specially provided as specific keys.
The present invention is not limited to these, but may include, for example, a combination of any one special key and a numeric key or function key normally provided in a calculator, or if this can be determined from the internal state of the calculator, the above-mentioned keys can be used. It goes without saying that it can itself be used as a specific keno, and in addition, in the above embodiment, an example of continuous operation of the country key and [ key was shown as an inverse conversion operation, but if a special key is provided, one It can be operated using keys. As described above, the present invention detects the decimal point position of mantissa data every time a specific key is pressed, and if this value exceeds a limit value determined by the display capacity of the mantissa data display section, conversion of the display data is prohibited. This can prevent the upper digits of the mantissa data or the lower digits of the significant digits below the decimal point of the mantissa data from being erased.

[Brief Description of the Drawings] Figure 1 is a circuit configuration diagram for explaining an embodiment of the present invention, Figure 2 is a time chart, Figure 3 is a diagram explaining the storage area of each register, and Figure 4 is a diagram for explaining the storage area of each register. 1 is a diagram showing key operations and the display state at that time, and FIGS. 5 to 7 are flows for explaining the operation of the present invention.1...ROM13...
・R. AMll6...Calculation times 24...Display section, 25...Key input section.

Claims (1)

[Claims] 1. In a small electronic calculator that is equipped with a mantissa data display section and an exponent data display section and is capable of calculating data including exponent data, the first memory stores the decimal point position data of the lowest digit of the mantissa data display section. a second storage means for storing decimal point position data higher than the most significant digit of the mantissa data display section by a number of digits corresponding to the number of digits of the mantissa data display section; and a second storage means for storing decimal point position data of the mantissa data. 3 storage means, and conversion means for increasing or decreasing the index data by a fixed number each time a specific key is operated, and converting the decimal point position data in the third storage means in accordance with the number of changes in the index data. , detection means for detecting whether or not the decimal point position data converted by the converting means is within a range that is greater than or equal to the decimal point position data in the first storage means and less than or equal to the decimal point position data in the second storage means; and means for prohibiting further conversion by the converting means when the detecting means detects that the decimal point position data is not within the above range.