JPS6032228B2 - Clear control method for small electronic calculators - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a clear control method in a small electronic calculator.

Small electronic calculators, such as electronic desktop calculators, are equipped with an all-clear key (AC key) that clears all data, including input data and calculation results, and a clear key (CE key) that clears only the latest calendar number data. There is.

Therefore, when performing an arithmetic operation on a general relatively short calculation formula, if the two clear keys described above are provided, even if an erroneous arithmetic operation is performed, there will not be much problem.
However, in the above-mentioned conventional calculator, when the function key for the calculation content command is operated, it is impossible to correct the previous calendar data and function data, and all input data must be cleared. In so-called complete formula-based calculators that allow you to perform various complex calculations by operating keys according to the formula, if you operate the wrong function key when performing a long calculation including parenthesis calculations, the current All the data input up to that point had to be cleared using the all clear key and the input operation had to be performed again from the beginning, which was extremely troublesome. The present invention has been made in view of the above points, and it is an object of the present invention to provide a clear control method for a small electronic calculator that allows correction of previously input data even after a function key is operated.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit block diagram showing one embodiment of the present invention.
11 in the figure is a ROM in which various microinstructions are stored.
It is.

Then, from the ROMI I, a signal [SU] designating the row address of the register storing the operands of the RAM 12, which is a memory for calculations described later, and a signal [SU] specifying the row address of the register storing the operands are sent. Specify the signal [FU] to specify, the column address of the register storing the operand or the processing start column address [SL], and the column address of the register storing the operand or the processing end column address. signal [FL], operation instruction, numerical code [C. ], operation code such as transfer command [OP
], the signal [Na] for designating its own next address is output in parallel via bus lines a to g, respectively. and,
The signal [Na] output via the bus line g is temporarily stored in the address register 13. The output of the address register 3 is input to the ROM address section 14. The ROM address section 14 specifies the address of the ROM II in accordance with a signal input from the address register 13. Further, the operation code [OP] is supplied to the operation decoder 15 via the bus line f. This operation decoder 15 decodes the operation code [OP] and outputs, for example, a data output command OF, OS, a key input input command KE, an indirect address read command ID, for the register designated by the row designation address FU or SU. Code input command CI, stack input command SI, stack output command S○, subtraction command S
It outputs various control commands such as B, down count command DN, designated digit length mode M, and judge command JU. Further, a control command is sent from the operation decoder 5 to the timing decoder 16. This timing decoder 1
6 is a control command from the operation decoder 15, a specified digit length mode M, and clock pulses shown in FIG. 2 given from a timing pulse generator (not shown).
2, various timing signals Ja~? according to the timing pulses t,~t3. Outputs d, ta to tc, draft/write commands R/W1, R/W2, etc. Each of the above timing signals is a=t3・g.・〇P, ◇b:t2・〇.・〇P・ JC=t2・〇.・〇P2 0d=ra・0.・Mt.

=M・ST+M・t, tb=h4・t, tc=MST It is.

In addition, in Fig. 2, t, ~t3 is one digit, and RAM1
When reading data from 2, the contents of the register addressed by SU are read out at timing t, and the contents of the register addressed by FU are read out at timing t. is written to the register addressed by the FU at the appropriate timing. Also,
When the operation decoder 15 outputs a display and key sampling command, OP2 of the above timing signal is a stack-in SI or a stack-out command S.
This is a command given to the timing decoder 16 when O is output, and ST is a start command given to the timing decoder 16 from the flip-flop 17 at the beginning of the instruction step. In addition, the specified digit length mode M is R
If the AM12 designation is one digit, it will be “1”, and if it is two or more digits, it will be “1”.
0''.The row designation addresses [SU] and [FU] output from the ROMI1 are applied to the gate circuits G, , G2 via the bus lines a, b, respectively, and the gate circuits C, , G2 are The output of G2 is input to the row address input terminal [RAU] of RAM12 via the bus line h.The gate circuit G is directly connected to the timing signal t output from a timing signal generator (not shown). The timing signal is supplied to the gate circuit 02 via the inverter 18 to control the opening and closing of the gate.
1 2 column address or processing start column specification address [
SL] and address or processing end column designation address [
FL] are applied to gate circuits G3 and G4 via bus lines c and d, respectively. The gate circuits 3 and 4 are gate-controlled by timing signals ta and tb output from the timing decoder 16, respectively. The outputs of the gate circuits ○3 and 04 are output to the input/output bus line i, and the column address input terminal RA of the RAM 12
At the same time, it is input to the column address input terminal RAL of the stack RAMI9, which is a temporary storage memory. Further, the output of the gate circuit C3 is supplied to the counter 20. This counter 20 performs a counting operation in response to a timing signal Jd, and normally the timing signal Jd
The count is incremented by 1 each time . . Then, the counter 20
The output is applied to the column address input terminal RAL of the RAM 12 and the stack RAMI 9 via the gate circuit ○5, and also applied to one input terminal of the coincidence circuit 21. The other input terminal of this matching circuit 21 is given a processing end column designation address FL outputted from ROMI I to bus line d. The specified digit length mode M output from the operation decoder 5 is input to the matching circuit 21 by the inverter 2.
The matching circuit 21 operates when the output of the inverter 22 is "1". The coincidence output of this coincidence circuit 21 is applied to an AND circuit 23 and is also inputted to a flip-flop 17 via an OR circuit 24. Furthermore, the specified digit length mode M output from the operation decoder 5 is applied to the flip-flop 17 via an OR circuit 24. This flip-flop 17 is connected to a timing signal et al. It inputs an input signal in synchronization with , and outputs the above-mentioned start command ST. Further, the designated digit length mode M output from the operation decoder 15 is applied to the AND circuit 25. The AND circuits 23 and 25 have timing signals etc.? ，
is input, and its output signal is sent to the address register 13 as a logic signal via the OR circuit 26.
On the other hand, the RAM 12, which is the calculation memory, operates the registers for calculations of x, Y, and Z, the stack pointer SP that addresses the row of the stack RAM 19, and the clear key (CE key), as shown in FIG. 3, for example. ``1 every time
'' or C8 in which ``0'' is written.Registers A are arranged in the row direction.

Each of the x and Y registers above has numerical data storage digit VT (0
~14 lines), and function data storage digit F (13
The Z register is composed of a numerical data storage digit VT for display (lines 0 to 14) and a flag storage digit F (line 19) for determining whether or not it is the number of the first layer. The stack pointers SP and C8 are each 1 of the A register.
It is located at the 5th digit and the 1st nail row. Each of the registers X, Y, Z, and A is assigned an address number (0) to (3), and each register corresponds to the address number from the row designation address FU or SU. Code is output and addressed. Furthermore, the digits of each register are the column specified addresses FL and SL.
The reading and writing are addressed by the read/write signal R/ which is output from the timing decoder 16.
Conducted by WI. That is, when R/WI is "0", the information stored in each register is read and becomes "1".
Writing is performed when . Therefore, the operands, operands, or data output for transfer, etc., addressed by the row and column designation addresses are output to the output terminal OU.
T is output as parallel 4-bit data, and a timing signal t. The signal is sent to the latch circuit 27 via the gate circuit ○6 whose gate is controlled by the timing signal t2 and the latch circuit 28 via the gate circuit G7 whose gate is controlled by the timing signal t2 and the timing signal t2. And the latch circuit 2
The output of 7 is connected to the column address input terminal RA of the RAM 12 via a gate circuit G8 controlled by an indirect address issuing command m output from the operation decoder 15.
It is input to L. Furthermore, the output of the latch circuit 27 is supplied to the input terminal a of the arithmetic circuit 31 and sent to the buffer 32 via a gate circuit G9 controlled by the data output command OS output from the operation decoder 15. This buffer 32 lowers the input signal according to the timing signal ◇c, and its output is stored in the stack RAM.
It is applied to the row address input terminal RAU of I9. The stack RAMI 9, which is this temporary storage memory, has a plurality of registers M, ~Mn stacked as shown in Fig. 3, and each of these registers M, ~Mn is designed to store calculation data, respectively. There is. These registers M
, ~Mn have the same configuration as the arithmetic registers x, Y, and Z. The output of the latch 28 is connected to the input/output terminal A of the stack RAMI 9 through gate circuits ○, o, G, . Input via . The gate circuits C, o are controlled by the data output command OF output from the operation decoder 15, and the gate circuits G, . [Mastack input command S
Controlled by I. In addition, the above stack RAMI9
The issue/write mode is specified by the issue/write command R/W2 output from the timing decoder 16, and the data output from the input/output terminal A is sent to the data input terminal IN of the RAM 12 via the gate circuit GM. is input. Above gate circuit ○. 2 is controlled by a stack output command SO output from the operation decoder 15. Further, from the latch circuit 28 to the gate circuit G
, o are sent to the input terminal b of the arithmetic circuit 31 and also to the buffer 33. This buffer 33 operates in synchronization with the timing signal a, and its output is sent via a decoder 34 to a display section 35 for display. The arithmetic circuit 31 is equipped with an arithmetic data output line i and a carry output line k, and the data output from the line j is sent to the gate circuit G.
, 3 to the input terminal IN of the RAM 12.
The gate circuits G and 3 are controlled by a stack output command SO input via an inverter 36. The data output from the arithmetic circuit 31 to the line i is applied to the AND circuit 38 via the OR circuit 37, and is applied to the line k'
The output carry signal is applied to an AND circuit 39. The AND circuits 38 and 39 output signals when a judge instruction JU is given from the operation decoder 16, and the outputs of the AND circuits 38 and 39 are input to the address register 13 as address data. Further, data output from the latch circuit 27 via the gate circuit G9 is input to a buffer 40 that operates in synchronization with the timing signal ◇b. The output of this buffer 40 is sent via a decoder 41 to a key input section 42 as a key sampling signal, and also to a display section 35 as a digit signal. The key input data output from the key input section 42 is stored in a buffer 43 that operates in synchronization with the timing signal et al. 4 to the input terminal a of the arithmetic circuit 31. Also, this input terminal a has a ROMI
Numerical code Co output from I to line e is input via gate circuits ◯ and 5. This gate circuit ◯, 5 is controlled by the code input command CI output from the operation decoder 15. Next, according to FIG. 4, the address register 13, ROM address section 14, ROMI
1. Details of the operation decoder 5 and timing decoder 16 will be explained.

Note that FIG. 4 shows only the parts related to the processing when the CE key is operated for each of the above-mentioned circuit parts, and other parts are omitted. The address register 13 has, for example, a 4-bit foundation, and each bit has a ROMII
The 4-bit next address Na output from the 4-bit address is input. In this case, the outputs of the AND circuits 38 and 39 are input to the first and second bits of the address register 13 via the OR circuits 51 and 52 together with the next address Na. Each bit output from the address register 13 is sent directly or via an inverter to the ROM address section 14, where it is decoded and specifies the address of the ROM II. ROM
II outputs signals such as SU, FU, SL, FL, Co, OP, Na, etc. according to the address designation from the ROM address section 14. In this case, the row specification address SU, F
Only U is output as a 2-bit code, and other signals are output as 4-bit codes. The operation decoder 15 is RO
Decode the operation code OP output from MI1, for example, SB, S○, JU, M, OS, CI, O
Outputs control commands such as F. The timing decoder 6 outputs control signals such as 0c, R/W1, and R/W2 in synchronization with the timing signal in response to the control signal output from the operation decoder 15. That is, the timing signal 0c is the timing signal 0c when the data output command OS is output from the operation decoder 15.
The issue/write command R/WI is output in synchronization with the timing signal 3 when something such as subtraction command SB, stack output command S○, code input command CI, etc. is output. be done. In addition, the display/write command R
/W2 is 3 on the timing signal when the operation code OP of "0010" is output from ROMI I.
output in sync with FIG. 5 shows the relationship between the operation code OP for the main operations and the control signal output at that time. Next, the operation of the present invention configured as described above will be explained. Although not shown in the RAM 12, a control counter for obtaining a display digit control signal and a key sampling signal is provided, and outside this control counter, the calculation circuit 31 counts by 1 at a constant cycle according to instructions from the ROM II. It has been uploaded. The contents of the above control counter are displayed on the display section 35.
When the most significant digit reaches the specified value, it is set and the count-up operation starts again. The contents of the above control counter are changed to gate circuit ○6, G9 every time it counts up.
The data is read out to the buffer 40 via. The contents read out from this buffer 4 are decoded by a decoder 41,
The signal is sent to the key input section 42 as a key sampling signal, and is also sent to the display section 35 as a digit signal. In this manner, key sampling signals and digit signals are supplied to the key input section 42 and the display section 35 according to the contents of the control counter. Further, the contents of the control counter are applied to the column address input terminal RAL of the RAM 12 via the gate circuit G8, and the digits of the display register are sequentially addressed from the lower digits to the upper digits according to the count contents of the counter. The contents of the digits of the display register which are sequentially addressed by the contents of this control counter are sent to the decoder 3 via the gate circuits G7, G, o and the buffer 33.
4, is decoded by the decoder 34, and displayed on the display section 35 in synchronization with the digit signal. In this way, a normal display operation is performed. When a key is operated in this state, a code signal corresponding to the operated key is output from the key input section 42 and stored in the buffer 43. Further, at this time, the count-up operation of the control counter in the RAM 12 is prohibited by a signal output from the key input section 42 in synchronization with the key sampling signal.
Next, key input command K is sent from operation decoder 5 according to operation code OP from ROMII.
E is output, and the key input data stored in the buffer 43 is read out via the gate circuit ◯, 4, and sent to the RAM 12 via the arithmetic circuit 31 and the gate circuit G, 3. Then, the operation key is determined based on the input data stored in the RAM 12 and the contents of the control counter at this time. That is, the key sampling signal output from the decoder 41 is commonly given to a plurality of keys, and the same code signal is output for each predetermined key group, so that the key input code is The operation key is determined based on the key sampling signal at that time. Then, in accordance with this determination result, the input code corresponding to the operation key is stored in the RAM 12, and thereafter the operation of the control counter is restarted. The data writing operation to the RAM 12 when the number of layers is manipulated will be described below with reference to FIG. As shown in FIG. 6, when the calendar number operation 1 is performed in the key input unit 42, the operation decoder 15 outputs the judge instruction JU according to the operation code OP from the ROMII, and as shown in the step-pro, the Z register in the RAM 12 is It is determined whether the contents of the function storage digit ZP are "0" or not.

In other words, StepRo determines whether the input data is the first layer number data. The contents of the above ZF are “
0'', the input data is the first layer number data, and the process proceeds to step m, where the contents of the numerical data storage digit XvT and the function storage digit XF of the x register shown in FIG. 3 are cleared. Then, as shown in step W, Z of the Z register is
Write "1" in the F digit, remember that the first calendar number has been performed, and proceed to step V, where C8 of the A register is written.
, writes “0” to . Also, if the step number is determined as NO, that is, if the calendar number has already been set and the input data this time is not the second layer number G, proceed to the step and read the contents of the calendar number data input digit of the X register. Increase by one digit. When the above step V or step 2 is completed, the input data En is stored in the lowest digit XvT (Melon D) of the × register as shown in the step field, and then the contents of ×vT of the X register are stored as shown in the step field. ZvT of Z register
Transfer to. The contents stored in this Z register are then displayed on the display unit 35 as shown in step K. When accessing the RAM 12, the ROM II outputs row designation addresses SU, FU, processing start column designation address S, and end column designation address FL depending on the processing content.

Further, the ROM II provides the operation code OP to the operation decoder 15 according to the processing content at that time, and as a result, various control commands are output from the operation decoder 5 to execute predetermined processing. For example, when executing the step flow in FIG. 6, the Z register is specified by the row specification address FU, and the column specification address F
Function storage digit F is designated by L. That is, the function storage digit ZF of the Z register is specified by the addresses of FU and FL. Then, the contents of this addressed ZF are sent to the arithmetic circuit 31 via gate circuits G7, G, and o, and the next address of the ROMII for step m or step W is specified according to the contents of ZF. In this case, since one digit is specified, the specified digit length mode M output from the operation decoder 15 is "1", the output of the inverter 22 becomes "0", and the operation of the matching circuit 21 is prohibited. ing. Also, the 6th
When executing step C in the figure, line specification address F
U specifies ×registry, and column designation address SL,
FL specifies the processing start column and the processing end column, that is, the least significant digit and the most significant digit in this case. In addition, in this case, the specified digit length mode M output from the operation decoder 15 becomes "0", and the timing decoder 1
The issue/write command R/WI output from 6 is “1”
Then, a write command is given to RNM12. Therefore, the row designation address FU output from ROMI I is
R via gate circuit ○2 at timings other than L
It is input to the row address input terminal RAU of AM12. Then, in accordance with the operation code OP output from the ROMII, the timing signal ta is first output from the timing decoder 16 and applied to the gate circuit 3.
As a result, the gate of gate circuit ○3 is opened and the ROMI
The processing start column address SL output from I is RAM1
2 column address input terminal RAL and the counter 20. At this time, the specified digit length mode M is "0" and the timing signal d is output from the timing decoder 16, so the process start column address SL is d in the timing signal.
is set in the counter 20 in synchronization with. Then, by the row designation address FU and column designation address SL,
Specifies the least significant digit of the register. Furthermore, when executing step m, a write command is given to the RAM 12 and data "0" is given to the input terminal m of the RAM 12, so "0" is written to the lowest digit of the X register. Next, the timing signal ◇d is outputted from the timing decoder 16, and the contents of the counter 20 are incremented by 11.
When the specified digit length mode M is "0" and the start signal ST is not output from the flip-flop 17, the timing signal tc is output from the timing decoder 16, and the gate of the gate circuit C5 is opened. Therefore, the output of the counter 20 is passed through the gate circuit G5 to the RA
It is input to the column designation address input terminal RAL of M12, and
Specify the register digit. The counter 20 is sequentially incremented by 11 by the timing signal gd, and the x registers are designated in the order of mixing the lower digits to the higher digits. By specifying two digits of the counter, "0" is written into the X register in order from the lower digit. Furthermore, the contents of the counter 20 are the contents of the gate circuit G5.
is input to the matching circuit 21 via
Anzu is always being compared. Then, as the counter 20 counts up, its contents are changed to the specified processing end column address F.
When the signal reaches L, the matching circuit 21 outputs a "1" signal, and the flip-flop 17 is set. As a result, a start command ST is output from the flip-flop 17 and input to the timing decoder 6. Therefore, the timing signal tc that had been output from the timing decoder 16 becomes "0", the gate of the gate circuit C5 is closed, and input of the column designation address to the RAM 12 is prohibited. Further, the coincidence output of the coincidence circuit 21 is output from the AND circuit 23.
given to open the gate. Therefore, AND circuit 2
3 to timing signal t3.? , is output and sent to the address register 13 as a logic signal via the OR circuit 26. The address register 13 reads the next address data in response to the input signal applied via the OR circuit 26 and inputs it to the ROM address section 14. Therefore R.O.
The MII starts the next processing operation when the next address is specified. In this way, the process of step m is completed, but
Processing is performed in the same manner in other steps in FIG. Next, the operation when a function key is operated will be explained with reference to FIG. When a function key is operated in FIG. 7, a function key input process is first performed as shown in step A. That is, the function data input from the key input unit 42 is temporarily stored in the buffer 43, and then sent to the gate circuit G. by the key input command KE. 4, and is read out from the RAM via the arithmetic circuit 31 and gate circuit G,
12. The function data input to the RAM 12 is written into the function storage digit xF of the x register by addressing from the ROMII. Next, proceed to step B, write "0" to function storage digit ZF of the Z register, and then proceed to step C.
As shown in , C8, (14th digit of A register) is “0”.
”. This CB, is clear (CE)
When the function data storage digit in the stack RAMI9 is cleared by a key operation, "IJ" is written.First, in this step C, if C8 is determined to be "OJ", the process advances to step D, and the stack pointer SP Write the previously input numerical data and function data stored in the register in the stack RAMI9 addressed by to YvT and YF of the Y register.Then, in step E, write the previously input numerical data and function data stored in the register in the stack RAMI9 addressed by . function data and XF of the X register
It is determined whether or not to execute the calculation by comparing it with the currently input function data stored in . In other words, when performing continuous calculations such as parenthesis calculations, weighting is performed on function data such as addition, subtraction, multiplication, division, etc., the weights are compared between the function data input last time and the function data input this time, and the calculation is performed according to the comparison result. Decide whether to perform the operation. For example, "XJ" ÷
If you set the weight of "10" to be larger than "1", the previous input function data was "×" or "÷" which was large, and the current input function data was "11" or "1" which was 4. determines that the calculation is to be performed, and performs the calculation process according to the previously input function data. Further, if the weight of the previous input function data is 4 points less than the weight of the current input function data, it is determined that the calculation is not performed. If it is determined in this step E that there is no operation, the process proceeds to step F and the RAM 1 2
The contents of the stack pointer SP inside are incremented by 11. Next, the process proceeds to step G, and the contents of the stack pointer incremented in step F are set in the address buffer 32 of the stack RAMI 9. Then, the numerical data and function data stored in the X register XvT'XF in the RAM 12 are transferred to the register, for example M2, in the stack RAM 19 which is addressed by this buffer 32 according to the step date. Next, as shown in step 1, the numerical data stored in XvT of the X register is transferred to ZvT of the Z register, and as shown in step J, the numerical data transferred to the Z register is displayed on the display section 35. Further, if the judgment result in step E is to execute the operation (YES), proceed to step K, and send the numerical data stored in XvT of the × register and YvT of the Y register to the arithmetic circuit 31, and store it in the Y register. A predetermined arithmetic process is performed according to the function data, and the result of the arithmetic operation is stored in the x register. Furthermore, if the determination in step C is NO, the process proceeds to step L and writes "0" into CE. and step M
The numerical data stored in the numerical data storage digit of the register in the stack RAMI 9 addressed by the stack pointer SP is written to the x register. When step K or M is completed, the process proceeds to step N and the contents of the stack pointer SP are decremented by 1. If the result is other than "0", the contents of the stack pointer SP decremented by 1 are stacked in step ○. Set in address buffer 32 of RAM 19. Note that if it is "0", proceed to step 1. When step ○ is completed, the process returns to step D and repeats the above-described operation. Steps 1 to 7 in FIG. 8 are the registers X, Z, A (
SP, CE, ) and the changes in the storage contents of the registers M, -M3 in the stack RAMI9.

First, when the calendar number "2" is performed, step 1 in Figure 8
As shown in
" is written, the contents of this XvT are transferred to ZvT, and the contents of this ZvT "2" are displayed on the display section 35. Also, due to the completion of the first calendar number, ZF received “1
" is written. Next, when the ``11'' function key is operated, the function data ``11'' is written to XF as shown in step 2 of FIG. The contents of the register M in the stack RAMI9 addressed by the stack pointer SP, and the function data storage section M, F'xvT of this register M.
” and the contents of ×F “11” are transferred. Also, the contents of ZF are cleared by operating the above function key. Similar processing is performed in response to subsequent key operations, and “5” is transferred. When the several-layer key is operated, "5" is set to ×vT, "5" is set to ZvT, as shown in step 7 of Fig. 8.
"1" on ZF, "3" on SP, "2" on M, Next, clear (CE), which is the main operation of the present invention, is shown in the flowchart of FIG.
A case where a key is operated will be explained.

Steps 8 to 11 in FIG.
It shows changes in the contents of AM12 and stack RAMI9. The CE key has a clearing function when correcting the calendar number and a function of sequentially clearing data from the latest input data to the first input data for each operation. Therefore, when the CE key is operated in the key input unit 42, the ninth
As shown in step P in the figure, it is determined whether the content of the function data storage digit ZF of the Z register is "0".
In this step P, address 1 of the ROMII is addressed by the ROM address section 14, and "1110" is outputted from the ROMII as the operation code OP. This operation code OP is decoded by the operation decoder 5 whose details are shown in FIG.
OF and JU become "1". At this time, the row designation address Fu output from the ROMII is "10" 2, and the column designation address FL is "1111" 15, so the Z register is designated via the gate circuit ○2 at the timing of tl, and the tb The IS row is designated at the timing via the gate circuit G4. The above address specification specifies the 19th line of the Z register, that is, ZF, and reveals its contents.
It is set in the latch circuit 28 at timing t2·J. At this time, since OF is "1", the latched contents of the latch circuit 28 are input to the arithmetic circuit 31 via the gate circuits ◯ and o. The output of this arithmetic circuit 31 is inputted to an AND circuit 38 via an OR circuit 37. Also, at this time, since the AND circuit 38 is given the judge command JU, if the content of the above ZF is "1", the AND circuit 38 outputs a "1" signal, and the read signal output from the OR circuit 26 Address register 13 by pulse
is loaded into the first bit of This address register 13
When M is “1”, the read pulse is output from the AND circuit 25 at the timing t3·J, and the read pulse is output from the OR circuit 26.
is applied to the address register 13 via the address register 13. moreover,
When M is "1", the flip-flop 17 is set at the above timings, and the start signal ST is given to the timing decoder 16. Therefore, the start signal ST will be output at the beginning of the next processing cycle. Also, when the first address of upper ROM11 is specified, the next address N output from ROM11
Since a is "0010" 2, if Zp is "1", the contents of the address register 13 will be "3", and Z
If F is “0”, the contents of address register 13 are “2”.
”. Depending on the contents of this address register 3, R
The address of OMI I is specified and we proceed to the next step. That is, in the determination at step P, if the content of ZF is "0", "2" is set in the address register 13 and the process proceeds to step Q. In this step Q, the determination operation is performed in the same manner as in the above step P, but at this time, the ROMI
The row designation address FU "11" 3 and the column designation address FL "1110" 14 are output from I, and as a result, RAM1
The 14th digit of the A register in 2, CE, is addressed. Therefore, the content of CE, is the arithmetic circuit 31
, and it is determined whether or not it is "0" in the same manner as in step P. Further, if the determination result in step P is NO and address 3 of ROMII is designated, the process proceeds to step T, where "0" is written in the function data storage digit ZF of the Z register. In this step T,
Row specified address FU “10” Column specified address FL “11
11'' specifies ZF of the Z register. Furthermore, with the operation code ○p "1001", the operation decoder 15 outputs M and the timing decoder 16 outputs R/WI. At this time, since the operation decoder 15 does not output any of OS, OF, and CI, the gate circuits ○9, ○, o, G, and 5 are not opened, and therefore the input terminal IN' of the RAM 12 becomes "0". It has become. In this state, when R/W1 (1") is applied to the RAM 12, "0" at the input terminal is written to ZF. Furthermore, if CE is determined to be "0" in the determination process of step Q, the address register 1 is set according to the next address Na "0100" output from the second ROMII.
3 is set to "4".

4 of ROMII depending on the contents of address register 3.
The address is specified and the process proceeds to step R. This step R is to write "0" into the function data storage digit of the register in the stack RAM 19 corresponding to the contents of the stack pointer SP. First, the address register 13 specifies address 4 of RAM II. Then, “101” is displayed from the operation code OP.
0" is output, which causes operation decoder 1
5 outputs M, and timing decoder 16 outputs R/W2. Also, from this time series specified address FL, “111
1" is output and the 15th digit is addressed. Furthermore, the contents of the stack pointer SP are set in the address buffer 32 of the stack RAMI9, and this buffer 3
The row of stack RAMI 9 is addressed by the contents of 2. That is, if the CE key is operated immediately after the function key is operated, the contents of the stack pointer SP are set in the buffer 32 in step G of FIG. ``0'' will be written to the function data storage digit of the register within 9. In this way, when "0" is written and cleared in the designated function data storage digit of stack RAMI9,
By the output M of the operation decoder 15, t3・J
, the flip-flop 17 is set via the OR circuit 24, and the start signal ST of the next step is set.
At the same time, a read pulse of the address register 13 is outputted via the AND circuit 25 and the OR circuit 26.
This read pulse causes the output "0110" of the next address Na of step R to be set in the address register 13, and the process proceeds to the next step S. When address 6 of ROMI I is specified by the address register 13, "1011" is output from the operation code OP,
The operation decoder 15 decodes and outputs M and CI commands, and the timing decoder 16 outputs R/WI. In addition, from several layer code Co “00
01”1 is output, and this output “1” is the code input command C
It is applied to the input terminal a of the arithmetic circuit 31 via the gate circuit G, 5 which is opened by I. The output of this arithmetic circuit 31 is applied to the input terminal IN of the RAM 12 via the gate circuit 13. At this time, the row specified address Fu
"11" as column specification address FL, and "1110" as column specification address FL.
'' are applied to the terminals RAU and RAL of the RAM 12 via gate circuits G2 and G4, respectively. Therefore, R/
When WI is output, "1" is written to CE of the A register specified by FU and FL. Also,
If the determination in step Q is NO, "5" is set in the address register 3 and the process proceeds to step U. In this step U, the contents of the stack pointer SP are set in the counterfeit data storage digits VT (digits 0 to 14) of the register in the stack RAMI 9 that is addressed by the address buffer 32 of the stack RAMI 9.
0" is written and cleared. That is,
In step U, address 5 of the ROMII is specified according to the contents set in the address register 13,
"0010" is output as the operation code OP. According to this operation code OP, the timing decoder 16 outputs R/W2. At this time, a timing signal ta is output from the timing decoder 16 in response to the start signals ST and M, and the gate of the gate circuit G3 is opened. As a result, the column designation address SL "0000" output from the ROMII is sent to the RAL of the stack RAMI9 via the gate circuit 03, designating the 0th digit, and in synchronization with the timing information MAD.
One item is set. Also, at this time, since the stack input command SI is not output from the operation decoder 15, the gate circuits ○, . is not opened and "0" is applied to the input/output terminals of the stack RAM. Therefore, "0" is written in the 0th digit of the register addressed by the address buffer 32 of the stack RAMI 9 in R/W2. On the other hand, at this time, the content "0" of the counter 20 is sent to one input side of the matching circuit 21 via the gate circuit G5, and the processing end column input from the ROMII to the other input side of the matching circuit 21. Specified address FL “11
11'', that is, compared with ``15''. In this case, since there is no match, no match signal is output from the match circuit 21, so no read pulse is output from the AND circuit 23 and the OR circuit 26, and the contents of the address register 3 remain unchanged.
At the same time, the timing signal ◇d is applied to the counter 20', and the counter value is incremented by 11. Then, when the next digit cycle is successful P, and the first digit cycle is entered, "0" is written to the first digit of the register in the same manner as the operation of writing "OJ" to the 0 digit described above. Thereafter, from the second digit to the first digit of the above-mentioned digit, the digits are sequentially designated from the counter 20' and "0" is written. Then, when the counter value of the counter 20 reaches "15", this counter value is supplied to the terminal RAL of the stack RAMI9 as a column address signal via the gate circuit ○5, and the above-mentioned signal is sent to the 13th row of the register. Similarly, "0" is written. At this time, the counter value "15" is sent via the gate circuit G5.
is applied to one input terminal of the coincidence circuit 21, so
FL applied to the other input terminal of the matching circuit 21
A match is made with "1111" (content=15), and a match signal is output from the match circuit 21. This match signal is applied to the AND circuit 23 and to the flip-flop 17 via the OR circuit 24. Therefore, a "1" signal is outputted from the AND circuit 23 at the timing of ra, d, and is sent to the address register 13 as an input pulse via the OR circuit 26. The next address "0111" is set in the address register 3 by this read pulse, and the process proceeds to the next step V. Further, the output of the coincidence circuit 21 is loaded into the flip-flop 17 at the above timing, and the start command ST for the next step is outputted from the flip-flop 17. In this way, the process of step U is completed, but while the contents of the counter 20 are counted up from "0" to "14", digits 0 to 14 of the register in the stack RAMI 9 addressed by the buffer 32 are counted up. “OJ” is written to “OJ”. Step V is
In the step of reading the contents of the stack pointer SP, incrementing it by 1, and writing the result to the stack pointer SP, the ROM
From II, row designation address Fu "11", column designation address FL "1111" and code signal C.

"0001" 1, operation code OP "1111"
”, and the next address Na “1000” is output. When the above operation code OP “1111J” is output,
Control commands SB, M, C from the operation decoder 15
I, OF, are output, and the timing decoder 1
A write command (R/W1) is output from 6. By outputting a code input command CI, the ROMI
I to code signal C. "0001" 1 is gate circuit ○,
5 to the arithmetic circuit 31. Then, by the row designation address FU and column designation address FL, RAM1 is
The stack pointer SP of 2 is addressed and its contents are set in the latch circuit 28 at the timing of .J. The contents set in the latch circuit 28 are sent to the arithmetic circuit 31 via the gate circuits G and o. At this time, since the subtraction command SB is given to the arithmetic circuit 31, the stack pointer S input to the arithmetic circuit 31
The content of P is code signal C. "0001" is incremented by 1, and the result is written to the stack pointer SP via the gate circuits ◯ and 3. When the operation in step V is completed, address 8 of the ROMII is designated by the next address Na "1000" and the process proceeds to step W. This step W transfers the contents of the stack pointer SP to the stack RAM.
It performs the operation of setting the address in the address buffer 32 of I9. First, when address 8 of ROMI1 is specified according to the contents of the address register 13, the ROMI
From I, row designation address Su “11”, column designation address S
L "1111", operation code OP "1100"
”, and the next address Na “1001” is output. With the above operation code OF "1100", the operation decoder 15 outputs M, OS, and the timing decoder 16? c is output. Therefore, the contents of the stack pointer SP addressed by the row designation address SU and column designation address SL are t. The data is read out to the latch circuit 27 via the gate circuit C6 at the timing of . The output of the latch circuit 27 is then given to the address buffer 32 of the stack RAMI 9 via the gate circuit ○9 opened by the data output command OS, and is set in synchronization with the signal ◇c from the timing decoder 16. Ru. When the contents of the stack pointer SP are set in the buffer 32 in this way, an input pulse is sent to the address register 13 via the AND circuit 25 and the OR circuit 26 at a timing of 0 according to the output of M from the operation decoder 15. However, the OR circuit 24
is set in flip-flop 17 via ST, and the next start signal ST is output. As a result, the next address Na "1001" is set in the address register 13 and the process advances to the next step X. This step x writes "0" to C8 of the A register in ROMII to clear it.
The application code OP is the same code as in step T above.
001" is output. Therefore, the operation decoder 15 and timing decoder 16 output instructions exactly the same as in step T above. However, step X
In this case, "11" is output as the row designation address FU and "1110" is output as the column designation address FL, so that CE of the A register is addressed. That is, by the same operation as in step T, "0" is written and cleared in CE of the A register. Each step S above,
When the operation of T or × is completed, 1 of ROMI I
Tochidenchi is addressed and the process proceeds to step Y.

This step Y is performed by the stack RAMI addressed by the address buffer 32 of the stack RAMI9.
Read the numerical data storage digit VT of the register in 9, and
The data is written to the numerical data storage digit ZvT of the Z register in the AM12, and address 10 of the ROMII is first addressed according to the contents of the address register 13. With this address specification, the row specification address FU "1" is sent from ROMII.
0", processing start column designation address SL "0000", processing end column designation address FL "1110", and operation code OP "0101J". With this operation code OP "0101", the operation decoder 15 outputs S○, The timing decoder 16 outputs timing signals ta, mad, and write command R/WI. First, the 0th digit of the Z register of the RAM 12 is designated by the row designation address FU and the process start column designation address SL. In addition, the column designation address SL is the counter 2.
It is set in synchronization with the timing signal MAd. Is the content of this counter 20 a timing signal? The number 11 is reached by d, and the Z register is sequentially specified from the 1st digit to the 14th line. At this time, the contents of the register in the stack RAMI9, which is addressed by the buffer 32, are input to the RAM 12 via the gate circuit G,2 opened by the command SO, and written to the Z register, which is addressed by the row designation address FU. be included. That is, the contents of the register specified by the buffer 32 are 0 to 1 of the Z register.
Written in line 4 (ZvT). When the contents of the counter 20 match the processing end column designation address FL "1110", a match signal is outputted from the match circuit 21 and given to the AND circuit 23. Therefore, from the AND circuit 23,
? A “1” signal is output at the timing of , and the OR circuit 2
6 to the address register 13 as an interrupt pulse. This read pulse causes address register 1
The first step of the display and key sampling flow is set to 3, and display and key sampling operations are performed. Therefore, the numerical data written in ZvT in step Y was displayed on the display section 35. This completes the process when the CE key is operated.

For example, if you notice an erroneous operation after the key operation for "203 (45)" is performed as shown in steps 1 to 7 of FIG. 8, and you operate the CE key, in this case, the Since the content of ZF is "1" after completing the calendar number, the processing flow advances from step P to step T in FIG.
After clearing the contents of the stack pointer SP, the contents "4" of the register M3 in the stack RAM 9, which is addressed by the address buffer 32 of the stack RAM 19 to which the contents of the stack pointer SP have been set, are extracted and written to ZvT. As a result, the data displayed as "5" changes to the previous numerical data "4". In this way, the first CE key operation erases only the latest numerical data. In this state, when a new numerical key is operated, the operated numerical value is inputted and displayed on the display section 35 according to the flow shown in FIG. That is, when the CE key is operated after the calendar number, normal calendar number correction is performed. Also, the second C key after the first CE key is pressed.
When the E key is operated, since the contents of ZF have been cleared at this point, the process advances from step P to step Q, where it is determined whether CE is "0" or not. This C
E, is cleared each time a numeric key or function key is operated as shown in FIGS. 6 and 7, so when this CE key is operated, it is determined as YES and step R is executed.
Go in the direction. As a result, as shown in step 9 of FIG. 8, the content "11" of the function storage digit F (M3F) of M3 is cleared and "1" is written in C8.
If you press the CE key again in this state, Y will appear at step P.
ES, NO is determined in step Q, and the process proceeds in the direction of step U. As a result, as shown in FIG. 8, the content "4" of the numerical data storage digit is cleared and the content "3" of the stack pointer SP is decremented by one to become "2". The content "2" of this stack pointer SP is then set in the buffer 32. Next, after "0" is written to CE, the numerical data "3" of M2 addressed by the contents set in the buffer 32 is read out to the Z register and displayed. If the CE key is further operated in this state, the process advances to step R based on the determination results of steps P and Q, and the same operation as when the CE key was operated for the second time is performed. As a result, Fig. 8 Step 1
1, the contents of the function data storage digit F (Pond F) in M2 of the stack RAMI 9 are cleared.As described above, according to the present invention, even after normal function key operation, The input data can be corrected before then.

``In addition, not only the last input data, but also numerical data or function data can be erased sequentially in the opposite order to the input order each time the CE key is operated to correct the input data 1. Therefore, parenthesis calculation When processing long calculation formulas such as, even if you notice that there is an error in a function key input or an error outside of the input data several times ago, you can erase up to the erroneous data without erasing all data. Therefore, error data can be easily corrected, and actual processing time can be shortened.

[BRIEF DESCRIPTION OF THE DRAWINGS] The drawings show one embodiment of the present invention, and FIG. 1 is a circuit configuration diagram, FIG. 2 is a diagram showing timing pulses used in FIG. 1, and FIG. 3 is a diagram showing a timing pulse used in FIG. 1. FIG. 4 is a diagram showing an example of the configuration of the ROM and operation decoder portion in FIG. 1. FIG. 5 is a diagram showing the correspondence between operation codes and control signals. The figure is a flowchart showing the process when a counterfeit operation is performed.
Fig. 7 is a flowchart showing the processing when a function key is operated, and Fig. 8 is a flowchart showing the processing when a function key is operated.
FIG. 9 is a flowchart showing the process when the CE key is operated. 1 1...ROM, 1 2...RAM
, 1 4. ．． ．． ．．・ROM address section, 15...
Operation decoder, 16... Timing decoder, 19... Stack RAM, 20... Counter, 2
1... Matching circuit, 42... Key input section. Figure 2 Figure 3 Rudder Figure 4 Figure 5 Figure 6 Figure 7 Figure 9 Figure 8

Claims (1)

[Claims] 1 A calculation memory that stores numerical data, various function data weighted according to the calculation, calculation results, etc., and a calculation memory that stores the weight of the function data input at that time each time the function key is operated. a determining means for comparing the weight of the previously inputted function data to determine whether or not the calculation can be executed; calculation means for performing calculation processing according to the data; and temporary storage for sequentially storing the numerical data and function data in a predetermined order in order to temporarily save the numerical data and function data from the calculation memory according to a negative determination result of the determination means. Each time a storage memory and an instruction key for correcting the contents of the temporary storage memory are operated, the data stored in the temporary storage memory is cleared for each data in an order opposite to the predetermined order. and means for reading numerical data stored before the data to be cleared in the temporary storage memory and writing it into the display data storage memory in the calculation memory. control method.