JPS6029130B2 - Miscalculation prevention method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for preventing fraudulent calculations in a small electronic calculator that performs predetermined calculation processing based on input data.

In general, a small electronic calculator is controlled by a microprogram that is fixedly installed in advance to perform a series of calculations, and input data is processed based on this program to obtain desired data.

Therefore, when a plurality of results are obtained for one or one set of input data, the operations are processed as one lotus, and the obtained results are sequentially stored in a plurality of memories. Therefore,
If an error, such as an overflow, occurs during this calculation process, the calculation result will be input without overflowing up to a certain memory, and the memo after that will be interrupted because the calculation process will stop due to the overflow. is not input, and the memory has the disadvantage that a mixture of correct and incorrect calculation results is stored. For example, in a computer with a built-in fixed program for linear regression calculation, each time data x and y are input,
n (n is the number of data inputs), 2×, 2×2, Zy, Z
v2, 2xy are sequentially calculated by a built-in program, and the calculation results are stored in corresponding internal memo files.

Thereafter, the values of A and B of the linear equation y=A+Bx are calculated by operating, for example, the 4 key or the country key. However, for example, the nth data (xn, yn
) If you input yn incorrectly as a very large number, calculations will be performed based on xn up to ZnZx, 2x2, and the correct calculation results will be input into each internal memory, but during the calculation to obtain 2y. An overflow occurs, the arithmetic processing is stopped, and the erroneous data is stored in the Zy memory, and the previous data remains in the 2y2 and 2xy memories. Therefore, even if the above A and B are calculated, the answer will be a contrived answer.For that reason, all the memories will be cleared and the first data x,,y
, I had to reinstall it. The present invention has been made in view of the above-mentioned circumstances, and provides a method for preventing erroneous calculations that enables accurate calculation processing by writing the calculation result data into a predetermined register after confirming that no errors occur during calculation processing. This is what we provide. below,
An embodiment of the present invention will be described with reference to the drawings.

In Figure 1, 1 is ROM (read only memory)
This ROMI stores microinstructions in predetermined binary codes for controlling the operations of each section, which will be described later. ,SI,F1,Co,M,
Cp and Na are output simultaneously and in parallel. However,
Fu specifies the row address of RAM (Random Access Memory) 3, which will be described later, to the output S from the ROMI, Su goes through gate circuit G, and Fu goes through gate circuit ○2. address input terminal UA of RAM3.
is input. Since the gate circuit G, is given a timing signal t, and the gate circuit G2 is given a timing signal t, via the inverter 4, the gate circuit G,
At the timing of the bee, the gate circuit G2 also operates other than t,
That is, it is opened at timings t2 and so on. The timing signal t is output from the timing signal generation circuit 5, and FIG. 2 shows the signal output from the timing signal generation circuit 5. In other words, the timing signal generation circuit 5 outputs clock pulses ◇, 2 and clock pulses ◇, ? Timing signals t, , t2, and t3 that are generated periodically in sequence in synchronization with 2 are output, and a clock pulse is generated every cycle of the timing signals t, to t3 (hereinafter, one cycle is referred to as one digit). ?
A clock pulse ◇o synchronized with , is also output. Also,
It specifies the column address of the output SI, F1, and RAM3 from the ROMI, and usually the column address SI is the row address Su, and the column address FI is the row address Fu.
Addressing of the RAM 3 is performed in pairs with each other.

The column address SI is a timing signal ta, which will be described later.
Through gate circuit ○3 whose gate is opened when the output of
Further, the column address FI is input to the address input terminal LA of the RAM 3 via a gate circuit 04 whose gate is opened when the timing signal th is output. Also, 6 is a timing decoder, which performs addition and subtraction output from ROMI.
When the instruction code ○p for transfer, judgment, shift, data input and output, etc. is decoded and input by the operation decoder 7, control signals CI, OF, OS, ID, KE, SB are generated.
, JU, etc., to control each circuit. The timing coder 6 also receives a mode signal M from ROMI, which will be described later, and a signal ST from the flip-flop circuit 8.
and clock pulses J·, ? from the timing signal generating circuit 5. 2,0o,timing signal t,,t2,t
3 is also input, and these signals and the instruction code from the operation decoder 7 generate timing signals ta, tb, tc, and clock pulses ? It outputs signals a'gb, gc and signals DN and R/W, which will be described later. Note that the timing signals ta and tb are calculated using the logical formula ta=M・
This is a signal obtained by ST+M·t·, tb=M·t. In addition, signal M can be processed by one microinstruction in one
This is output from ROMI when the digit period ends, and the logic value is “1” during the output period of this microinstruction.
Output. Still signal S from flip-flop circuit 8
T outputs "1" during the first digit period of each process, the details of which will be described later. Therefore, the timing signals ta and tb are t when M=“1”, that is, when the processing ends in one digit period.
a=t,,tb=t3, and the address of RAM3 is specified by the row address Su and column address SI when the timing signal t is output, and the address of the RAM 3 is specified by the row address Su and column address SI when the timing signal t,
When outputting, it is specified by row address Fu and column address FI. On the other hand, if M=0, that is, if the processing by one microinstruction does not end with one digit but consists of multiple digits, the row address Su when the timing signal et al., and the row address Su when the timing signal et al. Fu is input to the input terminal UA of RAM3 as a row address signal, but the column address is ta:ST, Tb.
= ,, 0'', the column address SI is given to the input terminal LA during the first digit period of the microinstruction. Also, this column address SI is the clock pulse output from the timing decoder 6 (=? It is also given to count 9, which operates in synchronization with o・M),
This count 9 is the signal DN from the timing decoder 6.
Performs down or up counting operation. From the second digit of the microinstruction, the value of count 9 is input to the input terminal LA of the RAM 3 via the gate circuit G3, whose gate is opened by the timing signal tc (=M ST), and becomes the column address. It is what it is. This count value of count 9 is returned to the input terminal of the counter 9 via the gate circuit 5, and is incremented or decreased by the signal DN, so that it becomes a new column address sequentially. Further, the count value of the counter 9 is inputted to the matching circuit 1 together with the column address F. The coincidence circuit 10 outputs a coincidence signal to one input terminal of the AND circuit 12 when the count value of the counter 9 and the column address FI match.
The other input terminal of this AND circuit 12 has a clock pulse ◇
n is given, and when a coincidence signal is input, the AND circuit 12 outputs a clock pulse ◇o. This clock pulse? o is given as e in the read pulse to the address conversion circuit 14 via the OR circuit 13, and when the address conversion circuit 14 receives the read pulse d8, it converts its own next address NA from the ROMI as will be described later.
is read, thus completing the processing of the plurality of digits described above. That is, as mentioned above, the column address of a microinstruction consisting of a plurality of digits starts with the column address SI, and then starts with the column address FI.
This ends the column addressing. ROM
The output Co from I is a numerical symbol code such as a numerical value or a symbol, and is input to the input terminal S of the arithmetic circuit 15, which will be described later, via a gate circuit ○6 whose gate is opened by the control signal CI from the timing decoder 6. Ru. Further, the output M, which becomes "1" when the microinstruction consists of one digit, is supplied as an enable signal to the matching circuit 10 via the inverter 16, and a clock pulse? It is applied to the flip-flop 8 through the OR circuit 18 together with the other input terminal of the AND circuit 17 to which o is applied and the coincidence signal from the coincidence circuit 10.

The flip-flop circuit 8 operates in synchronization with the clock pulse ◇o, and receives a signal S that is "1" for one digit period.
T is output to the timing decoder 6. That is, M is “1”
” and the processing ends with 1 digit, and M is “0”
”, and when a microinstruction consisting of a plurality of digits is terminated by the output of a match signal from the match circuit 10, a signal is output from the OR circuit 18 to the flip-flop circuit 8, and the first digit period of the next microinstruction is completed. The signal ST is output.ROMI output N
a is the address code of the next process after the process currently in progress, and is input to the address conversion circuit 14.

The output signals of AND circuits 19 and 20 are also input to this address conversion circuit 14, and output data from the arithmetic circuit 15 is input to one input terminal of the AND circuit 19 via an OR circuit 21. A carry (or borrow) signal from the arithmetic circuit 15 is input to one input terminal of the . Further, a judgment signal Ju from the timing decoder 6 is input to the other input terminals of the AND circuits 19 and 20, and this judgment signal Ju is output when a judgment command is issued. Then, in the address conversion circuit 14, the contents of Na and the output signals of the AND circuits 19 and 20 are OR-added to calculate the address for the next process, and the address is sent to the ROM address section 2, where a new microinstruction is selected. It is something that As shown in FIG. 3, the RAM 3 has a row address "
0" and column addresses "0 to 15"; registers B, C, and D, whose row addresses are "1", "2", and "3", and whose column addresses are "0 to 15"; Registers M whose addresses are "4", "5", "6", "7↓"81 "9" and whose column addresses are "0 to 15", respectively.
It has Earth, Earth, M4, M5, and Dove.

Then, when the read/write signal R/W from the timing decoder 6 is "1", the data input to the input terminal IN is written to the address specified by the terminals UA and LA, and the signal R/W is "1". 0'', the data at the address specified by the terminals UA and LA is read from the output terminal OUT. Normally, the above signal R/W becomes "0" when the timing signals t, t2 are output, and "0" at the time of t3.
1". Therefore, as mentioned above, since gate circuits ○ and ○3 are opened when the timing signal is output, the data in RAM3 specified by row address Su and column address SI is read at this time. The output timing signal t,0 is stored in the latch circuit 22 via the gate circuit ○,2 which is opened when the timing signal t,0 is generated.Also, the gate circuit G2,
G4 is opened when the timing signal t2, etc. is output, so when the timing signal t2 is output, the data at the address specified by the row address Fu and column address FI is read out, and the gate is opened by the timing signal t2. Circuit C, . is stored in the latch circuit 23 via the latch circuit 23. The data stored in the latch circuits 22 and 23 are gate circuits ○8 and G? which are opened by the control signals OS and OF outputted at the time of the timing signal t3 from the timing decoder 6, respectively. input terminals S, F of the arithmetic circuit 15 via
is sent to and calculated. This arithmetic circuit 15 performs subtraction or addition based on the signal SB from the timing decoder 6. When SB is "0", addition is performed, and when SB is "1", subtraction is performed. Further, the carry signal from the arithmetic circuit 15 is sent to the AND circuit 20, and the arithmetic result is sent to the OR circuit 21.
is sent to the AND circuit 19 via
It is also sent to the input terminal IN of , and written at the timing specified by the row address Fu and column address FI at timing t3. Furthermore, one digit of the above-mentioned AM3 is a count digit that is counted up sequentially through the arithmetic circuit 15 during display and key sampling, and the value of this count digit is the gate circuit ○, 2, the latch circuit 22, and the gate circuit. 0
8 to buffer B. This buffer B reads the value of the count digit in synchronization with the clock pulse 0b (=ra・0.・op, , op is the key sampling and digit drive command) from the timing decoder 6, and the read value is The signal is output via the decoder 24 as a digit driving pulse for the display section 25 and as a key sampling pulse for the key input section 26 . The display section 25 displays the R.A.
It displays the data of register A in M3, and the row address is always "0" during display and key sampling.
register A is specified, and the value of the count digit that is counted up sequentially is gate circuit ○, 2, latch circuit 22
and is input to the terminal LA via the gate circuit G9 whose gate is opened by the display from the timing decoder 6 and the control signal ID output at the time of key sampling, and this is input to the terminal LA.
This is the column address of M3. Then, gate circuits G, . , latch circuit 2
3 and gate circuit G7 to buffer B2. Buffer & clock pulse given data?
This data is then read in synchronization with the decoder 27.
It is sent to the display section 25 via. As mentioned above, since the corresponding digit drive pulse is sent from the decoder 24 to the display section 24, the content of the same digit of register A is displayed in the display digit corresponding to the value of the count digit among the display digits of the display section 25. Is displayed. However, "the key input section 26 has calendar number key group 2.
6a, a square for inputting data (x, y) for linear regression calculation, ear 3key, and A of y=Ax10B as mentioned above.
, B are provided, and a function key group 26b including a country key is provided.

Each of these keys is arranged at each intersection where the line to which the sampling pulse from the decoder 24 is supplied and the key common line which is output to the buffer & are arranged in a matrix, and by key operation ◇ The key common data inputted to the buffer B2 by the clock pulse o is inputted to the terminal S of the arithmetic circuit l5 via the gate circuit G, which is opened by the control signal KE outputted from the timing decoder 6 at the time of a data input command. Further, the data is written from the terminal D of the arithmetic circuit 15 to a predetermined area via the input terminal IN of the RAM 3. If the key common data of the buffer 8 exists within this predetermined area, the counting operation of the count digits is stopped, and the operation key is determined based on the count value at this time and the data in the buffer &. If it is a calendar number key, the numerical data corresponding to that key is input to the display register A, and if it is a function key, the address code Na of ROMI is sent to the ROM address section 2 via the address conversion circuit 14 based on the judgment result. After that, microinstructions for performing predetermined processing are sequentially output. In the above configuration, linear regression calculation is
Calendar number key 26a of key input section 26, x data input key
By operating the Xo, y data input key Yo, input the x, y data x,, y,, average, y2...xn, yn, and from these data n, Zx as shown in Figure 3. ,2×2
, Zy, 2〆, and Zxy are stored in registers M, , N, etc., M3, M4, M5, and M6 of RAM3, respectively,
Furthermore, by operating the country key, the linear equation y=
It is calculated by comparing the coefficients A and B of A+Bx with A=y-Bx B=n≧vine poison--Kyoyuki Teragata, and calculating that support=sheep and a=climb.

Below, data of x and y has already been input n times, and as a result, n, Zx, 2〆, 2y, Zy2 are stored in registers M, ~M6.
, 2, the numerical values n, d, e, f, g, and h have already been stored as the calculation result data for the two fences, respectively, as shown in FIG. The operation when a and b are input as y data will be described.

As shown in Figure 4, data a and b are stored in the Kokuan plate box.By operating the x data, a is stored in the register C, and the y data, b, is stored in the register 0.
, Zx, Z〆, Zy, Z〆, the process to obtain 2 members is started.

FIG. 5 shows the processing flow. First, in step S, the most significant digit of register A, that is, the row address "0".
↓It sets check operation flag “1” in digits A and 5 specified by column address “15”, and the numerical code “1” is output from output Co from ROMI and control from timing decoder 6. The signal CI becomes "1" and the numerical code "1" is written into the A and 5 of the RAM 3 via the gate circuit 6 and the arithmetic circuit 15. In the next step S2, n is calculated, that is, the number of data inputs is calculated, and a flowchart of this calculation is shown in FIG. 6a. In Step S of Fig. 6a, display the contents n of the n memory register M up to the previous time in the register A.
RA when the timing signal t is output.
The contents n of the register M, read from M3 are stored in the latch circuit 22 via the gate circuit ○, 2, and are further stored in the RAM 3 via the gate circuit 8 whose gate is opened when the timing signal t3 is output, and the arithmetic circuit 15. is written to register A of Then, in step S2b, the numerical code "1" from the output Co of ROMI is input to the lowest digit Bo of the register B.
” in the same manner as in step S, and further,
In step S2c, an operation of A+B, that is, an operation of n+1, is performed and written to the register A. In this step S2c, first, when the timing signal t is output, the column address "0", that is, the contents of the lowest digit, of the register B is stored in the latch circuit 22, and when the timing signal t2 is output, the contents of the column address "0", that is, the lowest digit, of the register A, that is, the contents of the lowest digit, are stored in the latch circuit 22. The contents of the column address "0" are stored in the latch circuit 23, and the respective stored values are stored in gate circuits G7 and G whose gates are opened when the timing signal t3 is output.
8 to the arithmetic circuit 15 to perform arithmetic operations, and write the result of the arithmetic operation to the lowest digit of register A. Then,
The column addresses of registers A and B are set to "1" and the general contents are sent to the arithmetic circuit 15 in the same way, and the result of the arithmetic operation is sent to register A.
The storage state of registers A, B, C, and D in this case is shown in FIG. 7a. Note that the above step S2c and the calculation steps described later always detect the presence or absence of an overflow, and if an overflow occurs in these calculation steps, that is, if there is an output from the AND circuit 20, the processing step is immediately terminated. This protects the contents of each register that have been previously input. Figure 5 Step S3
This is to detect whether "1" is present in the most significant digit A, 3 of the register A, that is, whether the check operation is in progress or the calculation operation is in progress. At the same time as sending the numerical code "1", the timing decoder 6 outputs the signal SB to perform subtraction, and the calculation result is "
If it is "0", it is determined that the contents of A,5 are equal to "1" and the process proceeds to the next step given from the output Na of ROMI. If the calculation result is not "0", an output signal is obtained from the AND circuits 18 and 19 whose gates are opened by the judgment signal Ju, and is added to the aforementioned Na in the address conversion circuit 14, and the process proceeds to another step. . At this point, since "1" has been written in A,5 in step S, the process advances to step S4. It should be noted that data transfer, calculation, judgment, etc. are performed by operations that are delegated. Therefore, detailed explanations of these steps will be omitted in subsequent steps. Therefore, the process S4 is to calculate 2x, and as shown in FIG. 6b, the process S4 first transfers the x data a stored in the register C in step S4a to the register A. In S4b, data d of Z[x up to the previous time stored in the register location is transferred to register B.

Then, in step S4c, d+a is calculated and written to register A. Note that if an overflow is detected in step S4c during this process, the process ends; however, when no overflow is detected in step S4c, the storage state of each register A, B, C, 0 is shown in FIG. 7b.
As shown. Step S5 is to detect whether "1" is present in A and 5, similarly to step S3.
The next process S6 is to perform a 2×2 operation, and as shown in FIG. The calculation result a2 is multiplied by the square, and the calculation result a2 is written in register A. Furthermore, in step S6c, the previous Z data e stored in register M3 is transferred to register B, and finally, in step S6d, registers A and B are The addition of the contents stored in , that is, the calculation of e1a2 is performed and written to register A. If an overflow is detected in steps S6b and S4 during this process, the process ends, but when no overflow is detected in each step S6b and S6d, the storage state of each register is as shown in FIG. 7c. . Next, in step S7, as in steps S3 and S5 above, it is detected whether or not A and 5 are "1", but in this case, since A and 5 are "1", the process advances to step S8.

This process S8 is to calculate Zy, and as shown in FIG. 6d, in step S8a, y data b stored in register D is transferred to register A, and in step S8b, it is stored in register M4. The data f of 2y up to the previous time is transferred to register B, and in the next step S8c, the contents of registers A and B are added, ie, an operation of f+b is performed, and the result of the operation is written to register A. be. During this process as well, overflow detection is performed in step S8c of each processing machine, but when there is no overflow, the storage state of each register A, B, C, and D is the seventh
As shown in Figure d. In step S9, as in steps S3, 5, and 7 above, it is detected whether A,5 is "1" or not, but since A,5=1 now, it is determined as YES, and then processing S,o In this process S, o, the calculation of Z〆 is performed.

This process S,o is as shown in FIG. 6e, steps S,
At oa, the contents of register ○ are transferred to register A. At step S, ob, the data b of y stored in register A is squared and written to register A. At step S, oc, the contents of y are stored in register M5. Transfer the data g of the previous 2〆 to register B, and finally, in step S, od, add the stored contents of registers A and B, that is, execute g + b2 and write to register A. It performs calculations. During this process, steps S and o are similar to the above process.
The presence or absence of overflow is detected in b, S, and od, and the storage state of each register when there is no overflow is as shown in FIG. 7e. Next, step S, . Then, as in steps S3, 5 and 9 above, it is determined whether A,5 is "1" or not, and since A,3=1 now, the process proceeds to step S,2.

This process S,2 is as shown in FIG.
2a, S, 2b, S, 2c to find the neck a and b of x data a and y data b, write the result to register A, and in steps S, 2d and S, 2e, calculate Z×y up to the previous time.
Performs an operation to add a and b to data h of register A.
Write in to find 2xy. Although the presence or absence of overflow is detected in steps S, 2c, S, and S, FIG. 7f shows the storage state of each register when there is no overflow. In this way, step S,2
When the process is completed, in step S, 3, the above step S3 is performed.
, 5 , 7 , 9. 、． Similarly, it is determined whether A and 5 are "1". However, at this point A. 5 becomes “1”
”, so proceed to step S, 4, and this step S,
In step 4, change A,5 to its previous value "1" and set it to "0". That is, in each process shown in FIG. 5, when A,5=1, the calculation result is not written to each register M,, M2...M6, and a check is performed to detect whether an overflow occurs. operation, step S. 4 means that it has been determined that no overflow will occur during this series of calculations, and "Next, execute the calculation while actually writing the calculation results to each register M, M2...M6. The arithmetic operation begins. Therefore, when steps S and 4 are completed, the process returns to the above-mentioned process S2 and the arithmetic operation of n is performed again.As a result, the registers A, B, C, and D are filled with the values shown in FIG. 7 as before. The data shown in a is stored.In step S3, it is determined whether A, 5 is "1" or not, but since A, 5 is "0" in step S, 4, step S ．． Proceed to step 5. This step S, 5
The contents of register A, that is, n obtained in step S2
data n+1 is written into the n storage register M. Then, when steps S and 5 are completed, process S4
The process advances to step M, where Zx is calculated and the result of the 2x calculation d0a is stored in register A, as shown in FIG. Then, in steps S and 6, the calculation result d+a is written into the 2× storage register location. Thereafter, steps S6, S8,
Zx2,2y stored in register A with S,o,S,2
, 2〆, 2xy are processed in steps S, 7, and S, respectively.
,8,S,9,S registers M3, M4, M5, M6 with illusion
The processing flow ends when the processing flow is completed. Figure 8 shows the registers M, , M2, M4, and M4 when the processing flow ends.
, pigeon, M6 register storage state. Thus, in the embodiment described above, with n, 2×, Z, 2y
, 2y2, 2x〆, etc., without immediately writing them into the husband's calculation result storage registers M, , M2, M3, M4, M6, and M6, first perform each calculation so that overflow does not occur. After confirming that the calculation is correct, the calculation is performed again and the calculation result is stored in each storage register, so if an overflow occurs during the calculation, the contents of each storage register will be the same as the previous data. This prevents incorrect data from being stored.

In the above embodiment, the case where an overflow occurs has been described, but the present invention can be applied not only to an overflow, but also to any case where some kind of error occurs, such as an underflow or an inoperable operation.

Furthermore, the calculation can be applied not only to linear regression calculations, but also to regression calculations such as logarithms, exponents, exponents, etc., and can be widely and generally used in ordinary calculations.

As explained in detail above, the method for preventing malicious operations according to the present invention detects whether or not an error occurs in a series of operations before storing the operation result in each register where it is to be written, and prevents the error from occurring. By confirming that the predetermined calculation result is stored in each register, even if an error occurs, the previously calculated result will be retained and the calculation process can be performed accurately. In addition, it has various advantages, such as being able to correct only the data inputted inadvertently and performing the calculation again following the previous calculation, and shortening the processing time.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a small electronic calculator showing an embodiment of the present invention, FIG. 2 is a time chart of clock pulses and timing signals output from the timing signal generation circuit of FIG. 1, and FIG. FIG. 4 is a diagram showing the register storage state of the RAM in FIG. 1, FIG. 5 and FIGS. Figures a to f are diagrams illustrating the storage state of the registers A, 8, C, and D, and FIG. 8 is a diagram showing the storage state of the registers M, M3, M5, and M6. 1...・ROM (read only memory), 3
...RAM (random access memory), 5.
...Timing signal generation circuit, 6...Timing decoder, 15...Arithmetic circuit, 25...
...display section, 26...key input section, Xo...x data input key, Yo...y data input key. Figure 2 Ship Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8

Claims (1)

[Claims] 1. Results obtained by calculations based on input data in a small electronic calculator that executes predetermined calculations based on input data and stores the results in a prescribed storage means. and an error detection means for detecting whether or not an error has occurred as a result of the calculation executed under the control of the control means. A method for preventing erroneous calculations, characterized in that when no error is detected by the detection means, the calculation based on the input data is executed again, and the calculation result is stored in the predetermined storage means.