JPS6032227B2 - Constant storage control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a constant storage control method for storing constants for constant calculation in a small electronic computer having a parenthesis computer library or the like.

Conventionally, for small electronic calculators, for example, B x A
If the multiplier A (or multiplicand) is the same, as in =, C×A=, D×A=,..., memorize the above prime number A (from now on, it will be searched when the constant is locked) and calculate only the multiplicands B, C, and D. It has a so-called constant calculation function that allows you to perform the above multiplication simply by inputting a calendar number.

And as a means to lock the constant, for example,
As shown in Figure 4, a computer has been put into practical use in which the constant A is locked by operating the same function key twice in succession. Incidentally, recently, in addition to the above-mentioned constant function, computers have been put into practical use that have a so-called parenthesis calculation function that performs mathematical parenthesis calculations by pressing keys according to the formula.

For example, when calculating ``50 (3 x 4 x 516)'', a computer with such a parenthesis computer library operates keys such as ``Sonoda Blood Diagram■Zu Sonoda Domachi'', and then calculates ``51 "(3x")
The numerical data and function data such as Sequential calculations are executed according to the function data. However, when a parenthesis calculation function was added to the constant lock type calculator as described above, when the operator tried to calculate the parentheses in the above calculation formula, the operator mistakenly made the following error message: If you operate the same function twice in a row in the calculation formula in parentheses like ``3
×” is stored in the stack memory in such a way that it is treated as a constant. In such a case, when the computer becomes capable of calculation, even if it attempts to read out the data stored in the stack memory and process the data sequentially, it will produce erroneous results and become unable to continue the calculation. For example, in the above case, the computer first calculates "3 x 4 (=12)" and then tries to subtract the multiplier "5" from this result, but "3" is already stored as a constant. Because of this, the computer cannot perform calculations, resulting in an error result. However, the operator has the inconvenience of not knowing where the error occurred because the key-input data is simply stored in the stack memory at the key operation stage. This invention has been made in view of the above circumstances, and only when a constant lock is established mathematically, continuous operation of the same function key is accepted as a constant lock operation. An object of the present invention is to provide a constant storage control method that determines a function key correction operation.

An embodiment of the present invention will be described below with reference to the drawings.

In the figure, 1 is a ROM (read only memory), and this ROMI stores microinstructions for executing various operations of this computer. Outputs various micro instructions.

One microinstruction is Su, Fu, SL, FL, C
It consists of o, 0p, and Na, each of which has a fixed binary code.

Su and Fu are RAM (Random Access
Su is input to the terminal UA of the RAM 3 via the gate circuit G, and Fu is input to the terminal UA of the RAM 3 via the gate circuit G2. The gate circuit G is opened when a timing signal tl is periodically outputted from a timing signal generation circuit (not shown), and the timing signal tl is connected to the gate circuit G2.
Since the timing signal tl is applied via the timing signal tl, it is opened at times other than when the timing signal tl is output. Furthermore, the timing signal output from the above timing signal generation circuit? ,,Ma2,tl,t
2, t3, and Jo are shown in FIG. Timing signals tl, t2, t3 are sequentially and periodically output in synchronization with clock pulsers, , ◇2. and timing signal t
A clock pulse is generated every cycle of l~shio. =The J,
is output. Among the above micro instructions, S and FL
designates the column address of the RAM 3 or stack RAM 5, and normally SL is paired with the row address designated by Su, and FL is paired with the row address designated by Fu. SL is input to the terminal LA of the RAM3 via the gate circuit ○3 which is opened when the timing signal tb is output, and FL is input to the terminal LA of the RAM3 via the gate circuit G4 which is opened when the timing signal tb is output. be done. The timing signals ta and tb are normally obtained from the logical formula ta=M·ST+M·tl, ratio=M·tl. The details of the control signals M and ST will be described later, but when one microinstruction is an instruction that ends in one digit period, the control signal M outputs "1" during the output period (one digit period) of this microinstruction. Signal ST outputs "1" for the first digit period of each microinstruction. Therefore, if M=1, ne=t1
, tb=tl=Z+de, and the address of the RAM 3 during the timing signal tl output period is specified by the row address Su and column address SL, and the timing signal Z~t
The address of RAM3 during the 3 output period is the row address Fu.
and address FL. When one microinstruction requires a plurality of digit periods, M=0, and in this case, i=ST and tb=“0”.

That is, during the first digit period, SL is connected to gate circuit G3.
The address is outputted via the RAM3 column address. Furthermore, this value of SL is input to a counter 6 which performs a counting operation in synchronization with d=JD·M using a clock pulse. This counter 6 performs a down or up counting operation depending on the presence or absence of a DN signal, which will be described later. From the second digit of the microinstruction consisting of multiple digits, the gate circuit opens when the timing signal tc=M・ST is output.○5
The value of the counter 6 is input to the RAM 3 via
This becomes the column address of RAM3. At the same time, the value of the counter 6 is fed back to the counter 6 again via the gate circuit C5 to be counted down or counted up, and is input to one input device of the matching circuit 7. In the above microinstruction consisting of multiple digits, the gate circuit ○
4 is closed, and the FL output from ROMI is input to the other input terminal of the matching circuit 7. When the value of the counter 6 becomes equal to FL, a coincidence detection signal is output from the coincidence circuit 7, and the microinstruction consisting of a plurality of digits is terminated, as will be described later. That is, in a microinstruction consisting of multiple digits, R specified by Su or Fu
The processing start digit of the storage area (hereinafter referred to as a register) in AM3 is specified by SL, and the processing end digit is specified by FL. Note that when the microinstruction is a left shift or right shift instruction for the register of RAM3, the above timing signals are ta=tl, ratio=“0”, wide=tl・
Becomes ST. The operation at this time will be described later. Also, among the above microinstructions, Co outputs a binary code,
This value is the gate circuit G that is opened when the control signal CI is output.
, 4 to the arithmetic circuit 8 or the RAM 3 as data. Among the microinstructions, ○p outputs instruction codes for addition, subtraction, left shift, right shift, transfer, judgment, display, key sampling, etc., and this instruction code is sent to the operation decoder 9.
The operation decoder 9 decodes the instruction code 0p and outputs the control signals OS, OF, KE, ID, CI, SI.
, S○, SB, DN, M, etc., as well as a display and key sampling command ○p, a stack RAM input/output command ○p2, a left shift or right shift command 0p3, etc. OS is a control signal for the gate circuits G, 2, and when the control signal OS is ``1'', the gate circuits G, 2 are opened. OF, KB, ID, CI, SI are the control signals for the gate circuits G, . , ○, 5, G, 3, G, 4, G, o, and when these signals are "1", the corresponding gate circuits are opened. Also, SO is the control signal for gate circuits G6 and G7. This signal is directly input to the gate circuit G6 and input to the gate circuit G7 via the inverter 10. Therefore, for example, when the control signal SO is "1", the gate circuit G6 is opened and the gate circuit G6 is inputted directly to the gate circuit G6. Circuit G7 is closed.The control signal SB represents a subtraction command, and this SB
is input to the arithmetic circuit 8, the arithmetic circuit 8 executes a subtraction operation. As mentioned above, DN' is a control signal sent to the counter 6 to cause it to perform a down-count operation. The control signals 0p, ○p2, 0p3 are the timing signal tl mentioned above.
, t2, and the clock pulse ◇ are input to the timing decoder 1. timing decoder 11
receives each of the above signals and outputs timing signals ne, ratio, tc,
A meeting clock? a, 0b, dc'0d, further read/
Write signals R/W, , R/W2 are output respectively. R
/W,,R/W2 are RAM3 and stack RAM respectively
This is the issue/write control signal of No. 5. Also, if the conference clocks a, gb, ◇c, 0d are expressed by a logical formula, ○
a=○.

・〇p. ○b=t2・01・〇p. JC=〆・de,・〇p2 Gud=○.・M・〇p30.・0p3 discussion clock ◇a,? b and Jc are input to buffer 12, buffer 3, and buffer 4, respectively.

The control signal M is input to the inverter 15, inverted to M, and then input to the matching circuit 7 as an enable signal. Further, the control signal M is inputted to a D-type flip-flop 17 via an OR circuit 16, and is also inputted to an AND circuit 18. The coincidence signal output from the coincidence circuit 7 is input to a D-type flip-flop 17 via an OR circuit 16, and also to an AND circuit 19. The output of the flip-flop 17, which takes the control signal M or the coincidence signal of the coincidence circuit 7 as an input signal, is the signal S.
It is called T and is input to the timing decoder 1 mentioned above. Is there a clock pulse in flip-flop 17? . is given, the signal ST becomes a signal that is output during the first cycle of each step instruction. AND circuit I
8 and 19 are timing signals. is input, and the outputs of the AND circuits 18 and 19 are sent as a signal ◇ via the OR circuit 20.
Output as e. In this signal, e is the logic clock of the address section register 21, and is expressed by the following logical equation. ◇e=OD・M+0.

・[Output of matching circuit 5] Of the microinstructions, Na is R
This is a next address designation instruction that specifies the address of the next step microinstruction of the microinstruction currently being executed by OMI, and is input into the address section register 21.
Further, a clock pulse G2 is input to the address register 21 as a data logical output clock. As a result, the address section register 21 stores the signal Na and the outputs of AND circuits 22 and 23, which will be described later, in synchronization with the read clock 0e, and also transfers data to the ROM address to provide the next step address Na when the clock pulse 2 is output. It is designed to be output to section 2. Next, RAM3 and stack RAM5 controlled by these microinstructions
The configuration will be explained below.

As mentioned above, RAM3 is addressed by the row address Su and the F stop column addresses SL and FL, and is read/outputable.
When the write signal R/W, is “0”, the data within the specified digit is output from the output terminal OUT, and R/W, is “0”.
1", data is written from the input terminal IN into the specified digit. Figure 3 shows a configuration diagram of RAM3. When the column address is 0 to 15, it is specified by the row address 0, 1, 2. The areas are called the x register, the Y register, and the Z register, respectively.The numeric digits V in which numeric data is stored are 0 to 14 specified by the column addresses 0 to 14 of each register.
In T, the 13th row specified by column address 15 is
This is a flag digit F that stores a function flag. However, the 19th line of the Z register is a count digit for display operation, which will be described later, and is referred to as F. The × register stores the operand, the Y register stores the operational number, and the Z register receives display data and data in the middle of the calculation. On the other hand, the area specified by row address 3 and column addresses 0 to 15 is called the A register, and the 19th row is a storage level counter C that stores the data storage level, which will be described later, and the 1st stitch row is this storage level counter C. This is the transfer digit P to which the contents of are transferred. Since the gate circuits ○, , G3, 09 are synchronized with the timing signal KAWA, the data in RAM 3 specified by Su, SL is read out from the output terminal OUT at the timing t1, and the timing signal tl.
The signal is stored in the latch 24 via the gate circuit G9, which is opened at the gate. In addition, since the gate circuits G2, G4, and G8 are normally synchronized by the timing signal tl (=t2 tenze), the data in RAM3 designated by Fu and FL is extracted at the timing of Azusa, and the timing signal Ze・0
, is stored in the latch 25 via the gate circuit GB which is opened at . The data stored in the latch 24 and the latch 25 are respectively sent to the arithmetic circuit 8 when the control signals OS and OF are output, and addition (subtraction designation signal SB=0) or subtraction (SB=1) is executed. When SO is "1", the calculation result of the calculation circuit 8 is applied to the input terminal IM via the gate circuit G7, and is written into the RAM 3 designated by Fu and FL at timing t8. Also, the arithmetic circuit 8
The data resulting from the calculation is inputted to one input terminal of the AND circuit 22 via the OR circuit 26, and the carry or borrow data is inputted to one input terminal of the AND circuit 23.
The other input terminals of these fund circuits 22 and 23 receive a judge instruction J output from the operation decoder 9.
U is being input, and at this time the address part register 21
Now, the next address designation instruction Na and the AND rotation iso 22,
23 is executed, and data indicating the next address of ROMI is calculated and sent to the ROM address section 2. The arithmetic circuit 8 stores data based on the binary code Co built in the ROM 1 and the latch 2.
In some cases, the output data of No. 5 is input and the calculation is executed, and the processing at this time is the same as described above. Further, FIG. 4 shows a configuration diagram of the stack RAM 5. Column address is 0-15
The areas designated by row addresses 1, 2, 3, . The row address specifying the stack registers SI to Sn is given by the contents of the transfer digit P of the A register in the RAM 3. For example, when the content of the P digit is "3", this value is read out and the gate circuit G9 and latch 2
4. Provided to the buffer 14 via the gate circuit G. In the buffer 14, in synchronization with the clock pulse Jc,
3" is read, and thereafter the value "3" in the buffer 14 becomes the row address of the stack RAM II. The column address of each stack register S, -Sn is given by the contents of the counter 6 whose start and end are specified by S and FL. The stack RAM 5 also has a signal R/W2 that specifies reading or writing of the data.
is given. When R/W2=0, the data in the stack RAM5 addressed as above is read out and sent to the input terminal IN of the RAM3 via the gate circuit ○6.
'This is given. When R/W2=1, the data output from the output terminal OUT of RAM3 is sent to gate circuit C8, latch 25, gate circuit G, . , through the gate circuits G,o, writes this data into the stack RAM 5 addressed as above. stack R
The 0th to IN lines of each stack register S, ~Sn of AM5 are VT, and the 15th digit is a flag digit F in which a function flag is stored.
The contents of the x register in RAM3 are written in n. In addition, the F digit (count digit) of the Z register in the RAM 3 is displayed in the arithmetic circuit 8 during display and key sampling.
It is counted up through. The count value of this count digit is given to the buffer 13 via the gate circuit G9, latch 24, and gate circuit C,2. buffer 1
3, the value of the count digit is read in synchronization with the clock pulse Jb. The value read into the buffer 3 is output via the decoder 27 as a digit signal on the display section 28 and as a key sampling pulse on the key input section 29. Also, the area outside the Z register is used as a display register. When displaying data, the value of the count digit is first read out, and this value becomes the column address of the RAM 3 via the gate circuit G9, latch 24, and gate circuits G and 3. At this time, the row address specifies the Z register, so data in a predetermined digit of the Z register corresponding to the value of the count digit is read out, and this data is sent to gate circuit G8, latch 25, gate circuit G, . is applied to buffer 12 via. The buffer 12 reads the applied data in synchronization with the clock pulse a, and further sends it to the display section 28 via the decoder 30. As mentioned above, since the corresponding digit signal is sent from the decoder 27 to the display section 28, as a result, among the digits on the display section 28, the digit indicated by the contents of the count digit is written in the Z register. The contents of the same digit are displayed. In addition, the key input section 29 has a line to which the key sampling signal is supplied and a key common line to be output to the buffer 31 arranged in a matrix,
A key is provided at the intersection of each line, and when a key common date is detected in the buffer 31 by key operation,
The counting operation of the count digit is stopped, and the operation key is determined based on the count value at this time and the data in the buffer 31. If it is a calendar number key, the numerical data corresponding to the key is input to the display register (Z register), and if it is a function key, Na of ROMI is changed in the address register 21 according to the judgment result, and predetermined processing is performed. To do this, the first address of the ROM address is specified. Next, according to FIG. 5, ROM1, ROM
Details of the address section 2, operation decoder 9, and address section register 21 will be explained.

Note that FIG. 5 shows steps g,
Only i, h, and d are shown, and other parts are omitted. The address part register 21 has, for example, a 4-bit configuration, and each bit receives the 4-bit next address Na output from the ROMI. In this case, the outputs of the AND circuits 22 and 23 are input to the first and second bits of the address register 21 via the OR circuits 21 and 212 together with the next address Na. Each bit output of the address section register 21 is sent directly and via an inverter to the ROM address section 2, where it is decoded and specifies the address of the ROMI. The ROMI outputs microinstructions consisting of, for example, Su, Fu, SL, FL, Co, 0p, Na, etc. according to the address designation from the ROM address section 2. The operation decoder 9 decodes the operation code ○p output from the ROMI and outputs SB, JU, CI, OF as shown in Table 1.
, 06, etc. are output. Part I In this embodiment configured as described above, the data storage level (hereinafter simply referred to as storage level) stored in the storage level counter C in the RAM 3 is changed every time a function key is operated. At the same time, the order of operations is determined, and the operations with higher order of operation are executed first.

For example, when executing the calculation formula "50 (3 x 4) =", the above storage level before execution of the operation is "0", but after operating the numeric key "5", the function key "
When ``11'' is operated, the storage level becomes ``2'', and the data ``511'' becomes the storage level ``2'' of the stack RAM 5.
” and is stored in the area corresponding to “. Next, press the open parenthesis key "(1," numeric key "3" function key "x"
are operated one after another, the calculation is not yet executed at this point, the storage level becomes "4", and the data becomes "(3x
" is sent to the area of the stack RAM 5 corresponding to the storage level "4". Next, when up to "4ha") is operated, the calculation level of this "3x4" multiplication becomes "50 (3x4").
)", the value inside the parentheses becomes operable. Therefore, the data "(3×") stored in the stack RAM 5 is read out, and the calculation in the parentheses "(3× 4)" is executed. With this calculation, the above storage level becomes "2". Next, when the "=" key is operated, the above data "511" is extracted and the above calculation result is "12". are added, and the answer "17" is calculated, and the storage level becomes "0" and the operation ends.Here, constant locking is possible arithmetically only when the storage level is "2". is the above “50 (3
This is clear from the explanation of ×4×516)''. Therefore,
If the same function key is operated twice in succession when the storage level is "2", a constant lock is applied and the storage level is set to "3". That is, in this embodiment, each time the calculation level increases by one level such as 0, 1, 2, 3, etc., the storage level increases by two levels such as 0, 2, 4, 6, etc. If a constant lock is applied when the storage level is "2", the storage level becomes "3", and thereafter increases as high as 3, 5, 7, and so on.

Therefore, with reference to FIGS. 5 and 6, the operation of this embodiment will be explained by taking the following calculation as an example.

5xx (34) = ■ (7-1) = ■ Before entering the key input operation of formula ■, each of the above registers X,
The contents of Y, Z, A, S, ~Sn are all “0” (
Figure 7 1).

First, in FIG. 7 2, press the numeric key "5" on the key input section 28.
is manipulated, due to the key sampling behavior described above,
Data "5" is written to the VT of the × register of the RAM 3 via the gate circuit G,5, the arithmetic circuit 8, and the gate circuit 07.

Next, when the function key "x" is operated, flow a in Figure 6 is executed, the code "x" is written to the F digit of the x register, and "2" is written to the storage level counter C of the A register. will be added. Next, the process proceeds to step b, where it is determined whether the function key is the function key after the calendar number or the function key after the function key. Since this is a function key after the calendar number, the process advances to step c. In step c, it is determined whether the function key is a function key after the first calendar number. In this case, since it is a function key after the first calendar number, the process advances to step d. In step d, the contents of the storage level counter C are transferred to the transfer digit P in the same A register. The storage level counter C (hereinafter simply referred to as C digit) specifies the register of the stack RAM 5 as shown in Table 2 according to its internal register. Table 2 Therefore, after transferring the contents of the C digit to the transfer digit P (hereinafter simply referred to as the P digit), in flow e, the 4-bit P
Only the upper three bits of the digit are extracted, and the value of those three bits is used as the row address of the stack RAM 5.

In this case, since "2" or "0010" is stored in the P digit, the upper 3 bits are "001" or "0010".
1" becomes the row address of the stack RAM I, and the stack register S. is specified. The contents of the x register are transferred to the stack register S (FIG. 3). Next, when the multiplication key "xJ" is operated successively, the process goes through steps a and b and goes to step f.In step f, the function key "x" operated this time is checked to see if it is the same as the function key operated last time. In this case, since they are the same, the process proceeds to step g. In step g, by subtracting ``3J'' from the contents of digit C,
It is determined whether the content of the digit is 2, 3, or 4 or more.
That is, if the C digit is "2", the constant lock can be accepted, and the process proceeds to the constant lock operation. Also, the C digit is “3”
'', this indicates that the constant lock state has already been reached, and the same function key has been operated, so the process proceeds to the constant lock release operation. Furthermore, C
If the digit is 4 or more, the process proceeds to a function correction operation. Since the content of the C digit here is "2", the process advances to step h, where "1" is added to the C digit to become "3", and the multiplier stored in the S register of the stack RAM 5 is "5× ” is locked (FIG. 4). Next, when the open parenthesis key "(1" is operated, the flag of this key "(1" is written to an area not shown in the RAM 3). At this time, the contents of each register shown in FIG. 7 do not change ( Figure 5
). Next, when you operate the numeric key "3", this data "
3" is input to the × register and stored in its VT (
Figure 6). Next, ``If you operate the 11th key, step a
, b, and c to step i. Here, since this "Eleven key" is the first function key after pressing the ")J key, proceed to step d. Then, by the same operation as above, "2" is added to the content "3" of the C digit, The customer in C digit becomes "5". Therefore, in flow 8, the content of the P digit is “0”.
10'' (IG Hayabusa number ``2''), therefore, in this flow e, the contents of the X register ``13'' are input to the register S2 of the stack RAM 5 (FIG. 7). Next, number key "4"
When , the data "4" is input to the VT of the x register (FIG. 8). Next, when the closing parenthesis key ")" is operated, the process goes through flow a, steps b, c, and i to step j. Here, it is determined that the operation order cannot be higher than the previous function "11" (that is, the calculation level is higher), and at the same time, the open parenthesis flag is detected, and the operation inside the parentheses is performed in flow h. As a result, the content of digit C is lowered by one calculation level to become "3". In this operation,
The data "31" in the stack register S2 is transferred to the Y register, and the data "30J" in the Y register and the data "4" in the x register are calculated. Then, the calculation result "7" is input into the x register (FIG. 9).
Next, when you operate the total key "=", the above calculation result is "7"
and the locked constant "5x" are calculated, and the result of the calculation, "35", is written into the x register. At this time,
Since the constant ``5×'' remains locked, neither the contents of stack register S nor the contents of digit C change (see Figure 1).
0). Next, enter the operation of the expression. When you operate the open parenthesis key "(1," the flag for "(1" will be set to R.
It is written in an area not shown in AM3 (FIG. 11).

Next, when "7" is converted into a calendar number, this data "7" is written to the X register (FIG. 12). Next, when you operate the subtraction key "1", the "1" flag is input to the F digit of the X register, and the previous content of the C digit "3" is changed to "2".
is added, and the content of digit C becomes "5". Furthermore, flow a
, steps b, c, d and flow e are executed, and in flow e, "010" (IQ Hayabusa number "2") is obtained in the P digit, so the contents of the × register "7-" are stored in the stack register S.
Transferred to 2. (Figure 13). Subsequently, when the subtraction key "1" is operated as a constant lock operation, flow a, steps b and f are executed, and step g is entered. Since the content of the C digit is "5", steps g and d are executed, and in flow e, data "7-" is written again to the stack register S2 which already stores data "7-". In other words, the constant "5x" is already locked in the computer,
Since the data storage level is not "2" which allows constant locking, even if a key input operation "--" which is the same as a constant lock operation is executed, this key input operation is not considered as a constant lock operation, but is simply a function correction. That is why (Figure 14). Next, when the numerical key "1" is operated, this data "1" is input into the X register (15 in the same figure).
. Next, when you operate the closing parenthesis key “)”, “
(7-1)" is executed. As a result, the contents of stack register S2 are cleared, and the contents of digit C are set to 1.
It goes down by the calculation level and becomes "3". At the same time, the calculation result "6" is written to the x register (FIG. 16). Finally, when you operate the total key =, the locked ``5''
×” and data “6” are calculated, and the calculation result is “30”
is input to the X register. Furthermore, the constant "5x" and the contents of the C digit "3" remain retained (FIG. 17). Although it was not in the calculation example above, the content of the C digit is "3", which means that a certain function key (for example, "xJ" is not used consecutively even though the constant lock calculation function has already been set on the calculator). If the same function key is operated for the third time, flow a, steps b, f, g, 1
is executed.

That is, for example, when inputting the key in the above formula (■), "5×××
”, the flow a, steps b and f are executed, and step g is entered. In step g, the above-mentioned operations are executed, and it is determined that the content of digit C is “3”. Enter Stepto. In the step, "1" is subtracted from the content "3" of the C digit to obtain "2", thereby returning the state to the state before the constant lock operation. In other words, the constant lock release operation has now been performed. Next, the operations of steps g, d, h, and 1 of the flowchart will be explained in detail using FIG.

Note that each of the four steps shown here is specified by a single digit, and although the control signal is not shown, it is always output. Assume that the address of step g is address 3, and the addresses of steps d, h, ] are addresses 7, 5, and 4, respectively. At address 3, the C digit of the A register of RAM 3 is designated by Fu=3 and FL=15.

The operation code ○p is "1111", and control signals SB, JU, CI, and OF are output. At different timings, the code "3" is supplied to the other input terminal of the arithmetic circuit 8 via the gate circuits G and 4 which are opened by the control signal CI. Since there is a subtraction instruction SB, "3" is subtracted from the contents of digit C, and the resulting data is sent to OR circuit 2.
6 to the AND circuit 22. Further, the borrow is sent to the AND circuit 23. Since there is a judge instruction JU, this data is supplied to the first bit of the address register 21 via the AND circuit 22 and the OR circuit 21. Bo again. 1 via the AND circuit 23;
Furthermore, it is supplied to the second bit of the address section register 21 via the OR circuit 212. N as the next address after address 3
a is set to "01000", and the first bit and second bit are OR-added to data, borrow, and each other.

That is, if the content of the C digit is "3", the result of "C digit - 3" is "0", and since there is no data or borrow, the process directly advances to the next address, address 4. Further, if the content of the C digit is "2", there is data and there is no borrow, so only the first bit of Na is ORed and the next data becomes address 7. At address 4, the C digit is designated as above, and the control signals SB, C
I, OF are output, and Co=1 is further output.

Then, "1" is subtracted from the C digit, a write command R/W, is output at timing t3, and the result is written to the C digit via the gate circuit 7. At address 5, the C digit is similarly designated, and control signals CI, OF and Co=1 are output.

Since there is no subtraction instruction SB, the contents of the C digit and the code "1" are added, and the result is written to the C digit. At address 7, the C digit is specified by Su=3, SL=15, and Fu=
3. P digit is designated by FL=14.

Then, the control command OS is output, and at the timing tl, C
The P digit is read out at the timing of the last digit, but since OF is not output, the gate circuits G, . is closed. Therefore, at the timing t3, the contents of the C digit are written directly to the P digit. In addition, Na of 4th and 5th places is 1 stolen land and 7
The address Na is number 8. In the above embodiment, the data storage level increases by 2 each time the calculation level increases by one level, and when a constant lock is applied, the data storage level increases by one level. The level setting method is not limited.

As detailed above, according to the present invention, the constant is accepted and locked only when the constant lock operation is performed at an appropriate time according to the arithmetic rules within the computer, and even if the constant lock operation ignores the arithmetic rules. For example, by simply treating it as a function key correction operation, the previously input data and data storage level will not be destroyed.
Since it is reliably protected, the operating method is clear and it is extremely convenient to use.

[Brief explanation of drawings]

The drawings show an embodiment of the present invention; FIG. 1 is an overall circuit configuration diagram of the same example, FIG. 2 is a time chart for explaining the basic operation of the same example, and FIG. 3 is a diagram of the RAM 3 of the same example. Diagram,
FIG. 4 is a configuration diagram of the stack RAMI I of the same example, FIG. 5 is a configuration diagram of the main parts of the ROM 1, ROM address section 2, operation decoder 6, and address section register 21 of the same example, and FIG. 6 is a configuration diagram of the main parts of the same example. FIG. 7 is a flowchart for explaining the operation, and a state diagram showing the contents of the x register, stack register S, stack register S2, and storage level counter C for explaining the operation of the same example. 1...ROM 2...ROM address section, 3...RAM, 5...Stack RAM,
8...Arithmetic circuit, 9...Operation decoder, 11...Timing decoder, 21...Address section register. Figure 2 of the rudder. Figure 3 Figure 4 Figure 5 Figure 6 Figure 7

Claims (1)

[Claims] 1 Memorize constants by operating the same function key twice in succession, perform constant calculations, and operate numerical keys and function keys having a predetermined calculation order according to the formula, and this function key is operated. The above calculation order is determined each time the calculation is performed, and based on this determination result,
A function in a small electronic calculator that counts up or down a data storage level to specify the data storage area of the stack memory, and stores the calculated data in the area in the stack memory specified by this data storage level. A determination means is provided for determining whether or not the data storage level is at a level at which constant storage is possible during a key operation, and only when the determination means determines that constant storage is possible, the stack memory designated by the data storage level is A constant storage control method characterized by storing constants in an area.