JPS6032229B2 - Clear control method for small electronic calculators - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a clear control method in a small electronic calculator.

Small electronic calculators, such as electronic desktop calculators, are equipped with an all-clear key (AC key) that clears all data, including input data and calculation results, and a clear key (CE key) that clears only the latest numerical data. .

Therefore, when performing arithmetic operations on a general relatively short calculator, if the above two clear keys are provided,
Even if an incorrect arithmetic operation is performed, it does not cause much of a problem. However, in the above-mentioned subordinate calculator, when the function key for the calculation content command is operated, it is impossible to correct the previous numerical data and all input data must be cleared. In so-called all-formula calculation calculators that allow you to perform various complex operations by operating keys, for example, if you operate the wrong function key when performing a long calculation including parenthesis calculations, All input data had to be cleared using the all clear key and the input operation had to be performed again from the beginning, which was extremely troublesome. The present invention has been made in view of the above points, and it is an object of the present invention to provide a clear control method for a small electronic calculator that allows correction of previously input data even after a function key is operated.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit block diagram showing one embodiment of the present invention.
11 in the figure is a ROM in which various microinstructions are stored.
It is.

Then, from the ROMI I, a signal [SU] that specifies the row address of the register storing the operands of the RAM 12, which is a memory for calculations described later, and a signal [SU] specifying the row address of the register storing the operands are sent. signal [FU] that specifies the column address of the register that stores the operand or the processing start column address [SL], and the signal that specifies the column address of the register that stores the operand or the processing end column address. Operation code [OP] such as signal [FL], arithmetic instruction, several layer code signal C0, transfer instruction, etc.
] Signals [Na] specifying the next address of the device are output in parallel via bus lines a to g, respectively. The signal [Na] output via the bus line g is temporarily stored in the address register 3. The output of the address register 3 is input to the ROM address section 14. The ROM address section 14 specifies the address of the ROM II in accordance with a signal input from the address register 13. Further, the operation code [OP] is supplied to the operation decoder 15 via the bus line f. This operation decoder 15 decodes the operation code [OP] and, for example, specifies the row designation address F.
Data output command OF for the register specified by U, data output command OS for the register specified by line specification address SU, key input instruction KE, indirect address output command ID, code input command CI, stack input command SI , stack output command S○, subtraction command SB, down count command DN, specified digit length mode M, judge command J
Outputs various control commands such as U. Further, a control command is sent from the operation decoder 15 to the timing decoder 16. This timing decoder 16 follows the control command from the operation decoder 15, the specified digit length mode M, and the clock pulses LOW, LOW2, and timing pulses t, to t3 shown in FIG. 2 given from a timing pulse generator (not shown). Various timing signals ◇a
~◇d, ta~tC, issue/write command R/W1,R
/W2 etc. is output. Each of the above timing signals is a=ra・〇.・〇P. ○b: Ra・〇.・〇P. Naka Ci et al. 〇.・〇P2 d=ra・J,. M Neni M・ST+M・t, Ratio=M・t, Wide M・ST.

In addition, in Fig. 2, t, ~t3 is one digit, and RAM1
When reading data from 2, the contents of the register addressed by Su are read out at timing t., and the contents of the register addressed by Fu are read out at timing. Furthermore, in writing, data is written at the timing of the registers addressed by the FU. Also, the above timing signal OP, 'ma operation decoder 1
When display and key sampling commands are output from 5,
OP2 is stack-in SI or stack-out command SO
ST is a start command that is given to the timing decoder 16 from the flip-flop 17 at the beginning of the instruction step. In addition, the specified digit length mode M is RA
“1” if M12 designation is 1 digit, “0” if 2 or more digits
”. Therefore, the row designation addresses [SU] and [FU] output from the ROMI 1 are applied to the gate circuits G, , G2 via the bus lines a, b, respectively, and the gate circuits G, , G2 are The output of G2 is input to the row designation address input terminal [RAU] of the RAM 12 via the bus line h.The gate circuit G is directly supplied with a timing signal L output from a timing signal generator (not shown). , the gate circuit ○2 receives a timing signal t,
is supplied via the inverter 18 to control the opening and closing of the gate. Also, the RAM output from ROMII
12 column address or processing start column specified address [S
L] and column address or processing end column specified address [
FL] are applied to gate circuits ○3 and G4 via bus lines c and d, respectively. The gate circuits G3 and G4 are respectively gate-controlled by the ratio of timing signals output from the timing decoder 16. The outputs of the gate circuits ○3 and G4 are outputted to the input/output bus line i, inputted to the column address input terminal RAL of the RAM12, and also inputted to the column address input terminal RAL of the stack RAMI9. Further, the output of the gate circuit G3 is supplied to the counter 20. This counter 2 rivers,
It performs counting operation using timing signal Jd.
Normally, each time the timing signal) d is input, the count is incremented by 1, but when the down-count command DN is given from the operation decoder 15, the timing signal d? Count down by 1 each time d is input.
The output of the counter 20 is applied to the column address input terminal RAL of the RAM 12 and the stack RAMI 9 via the gate circuit G5, and is also applied to one input terminal of the matching circuit 21. The other input terminal of this matching circuit 21 is given a processing end column designation address FU outputted from ROM II to bus line d. The specified digit length mode M output from the operation decoder 15 is applied to this matching circuit 21 via an inverter 22, and when the output of this inverter 22 is "1", the matching circuit 21 is activated. ing. The coincidence output of this coincidence circuit 21 is applied to an AND circuit 23 and is inputted to a flip-flop 17 via an OR circuit 24. Furthermore, the specified digit length mode M output from the operation decoder 15 is applied to the flip-flop 17 via an OR circuit 24. This flip-flop 17 inputs an input signal in synchronization with the timing signal etc. and outputs the start command ST described above. - Also, the designated digit length mode M output from the operation decoder 15 is applied to the AND circuit 25. A timing signal t3.g is input to the AND circuits 23 and 25, and its output signal is sent to the address register 3 as a logic signal via an OR circuit 26. On the other hand, the RAM 12, which is the above-mentioned calculation memory, has X, Y, and Z accumulator registers and a stack pointer SP that specifies the row address of the stack RAMI 9 arranged in the row direction, as shown in FIG. Each of the above registers has a numerical data storage digit V.
T (0 to 1 stitch row), and function memory digit F (15
line).

Note that the registers X, Y, and Z each contain (0) to (
2) address numbers are assigned, and each of the above registers is addressed when a code corresponding to the above address number is output from the row designation address FU or SU. Furthermore, the digits of each of the above registers are designated by the column designation address FL or SL, and reading and writing are designated by the logical start/write command R/WI output from the timing decoder 6. Further, the stack pointer SP is addressed when the row designation address is "11" (3) and the column designation address is "1111" (15). Therefore, the operands and operands addressed by the above row and column addresses, or the data output for transfer, etc., are output as parallel 4-bit data from the output terminal OUT, and the timing signal is output. latch circuit 27 via gate circuit G6 which is gate controlled by
It is also sent to the latch circuit 28 via the gate circuit G7 which is gate-controlled by the timing signals et al. The output of the latch circuit 27 is transferred to the RAM 1 via a gate circuit C8 controlled by an indirect address provision command m output from the operation decoder 15.
It is input to the column address input terminal RAL of No. 2. Furthermore, the output of the latch circuit 27 is supplied to the input terminal a of the arithmetic circuit 31 and sent to the buffer 32 via a gate circuit G9 controlled by the data output command OS output from the operation decoder 15. This buffer 32 reads input signals in accordance with the timing signal Jc, and its output is sent to the row address input terminal RA of the stack RAMI9.
Added to U. The stack RAMI9, which is this temporary storage memory, has a plurality of registers M, .
Mn are stacked, and each of these registers M, ~
Data for calculation is stored in each Mn. These registers M, -Mn have the same structure as the accumulator registers X, Y, and Z. The output of the latch circuit 28 is connected to the input/output terminal A of the stack RAMI 9, and the gate circuits G, ○, . Input via . The gate circuits C, . is controlled by stack input command SI. Further, the stack RAMI9 is designated with a read/write mode by the read/write command R/W2 output from the timing decoder 16, and the data read from the input/output terminal A is transferred to the RAM via the gate circuit G,2.
1 to 2 data input terminals IN. The gate circuits G and 2 are controlled by the stack output command SO output from the operation decoder 15. Further, the data outputted from the latch circuit 28 via the gate circuits ◯ and o is sent to the input end b of the arithmetic circuit 31 and also to the buffer 33. Is this buffer 33 a timing signal? The output is sent to the display section 35 via the decoder 34 and displayed. Therefore, the arithmetic circuit 31 has an arithmetic data output line j
and a carry output line k, and the data output from line i is sent to RAM1 via gate circuit G,3.
The signal is input to the input terminal IN of No. 2. The above gate circuit G,3
is controlled by a stack output command SO input via an inverter 36. Data outputted from the arithmetic circuit 31 to line j is applied to an AND circuit 38 via an OR circuit 37, and a carry IJ- or pollo signal outputted to line k is applied to an AND circuit 39. The AND circuits 38 and 39 are operated by the operation decoder 15.
The outputs of the AND circuits 38 and 39 are input to the address register 13 as address data. Furthermore, data output from the latch circuit 27 via the gate circuit G9 is input to a buffer 40 that operates in synchronization with the timing signal 0b. The output of this buffer 40 is sent via a decoder 41 to a key input section 42 as a key sampling signal, and also to a display section 35 as a digit signal. The key input data output from the key input section 42 is stored in a buffer 43 that operates in synchronization with the timing signal et al. , 4 to the input terminal a of the arithmetic circuit 31. In addition, the numerical code Co output from ROMI I to line e is connected to the gate circuit G at this input terminal a.
, 5. This gate circuit ○, 5',
It is controlled by the code input command CI output from the operation decoder 15. Next, according to FIG. 4, the address register 13, ROM address section 14, ROMI
1. Details of the operation decoder 5 and timing decoder 6 will be explained.

Note that FIG. 4 shows only the parts related to the processing when the CE key is operated for each of the above-mentioned circuit parts, and other parts are omitted. The address register 13 has, for example, a 4-bit configuration, and each bit has a ROMII
The 4-bit next address Na output from the 4-bit address is input. In this case, the outputs of the AND circuits 38 and 39 are inputted to the first and second bits of the address register 13 via the OR circuits 51 and 52 together with the next address Na. Each bit output of the address register 13 is sent directly or via an inverter to the ROM address section 14, where it is decoded to designate the address of the ROMII. R.O.
The MII is specified by the address from the ROM address section 14, for example, SU, FU, SL, FL, Co, 0p, N.
Outputs signals such as a. In this case, the row specification address SU,
Only FU is output as a 2-bit code, and other signals are output as a 4-bit code. Operation decoder 15 is
Operation code OP output from ROMI I
For example, SB, S0, JU, M, OS, C
Outputs control commands such as I and OF. The timing decoder 16 outputs control signals such as 0c, R/W1, and R/W2 in synchronization with the timing signal in response to the control signal output from the operation decoder 5. That is, the timing signal c is output in synchronization with the timing signals et.
I is output in synchronization with timing signal t3 when something such as subtraction command SB, stack output command S○, code input command CI, etc. is output. Further, the issue/write command R/W2 is output in synchronization with the timing signal t3 when the operation code OP of "0010" is output from the ROMI I. FIG. 5 shows the relationship between the operation code OP for the main operations and the control signal output at that time. Next, the operation of the present invention configured as described above will be explained. Although not disclosed in the RAM 12, a control counter for obtaining a display digit control signal and a key sampling signal is provided, and this control counter is incremented by 1 at regular intervals by the arithmetic circuit 31 according to instructions from the ROM II. There is. The contents of the above control counter are displayed on the display section 35.
When the highest digit reaches the specified value, it is set and the count-up operation starts again. The contents of the above control counter are changed to the gate circuits G6 and G9 each time the counter counts up.
This is discussed through the buffer 4 rivers. The contents output from this buffer are decoded by a decoder 41, and sent to the key input section 42 as a key sampling signal, and also sent to the display section 35 as a digit signal.
In this manner, key sampling signals and digit signals are supplied to the key input section 42 and the display section 35 according to the contents of the control counter. Further, the contents of the control counter are applied to the column address input terminal RAL of the RAM12 through the gate circuit G6, and the digits of the display register are addressed sequentially from the lower digits to the upper digits according to the count contents of the counter. . The contents of the digits of the display register which are sequentially addressed by the contents of this control counter are the gate circuits G7, G. o, it is decoded by a decoder 34 via a buffer 33 and displayed on a display unit 35 in synchronization with the digit signal. In this way, a normal display operation is performed. In this state, when a key operation is performed, a code signal corresponding to the operated key is outputted from the key input section 42 and stored in the buffer 43. Further, at this time, the count-up operation of the control counter in the RAM 12 is prohibited by a signal output from the key input section 42 in synchronization with the key sampling signal. Next, a key input command KE is output from the operation decoder 15 in accordance with the operation code 0p from the ROMI 1, and the buffer 43
The key input data stored in is read out via the gate circuit C, 4 and sent to the RAM 12 via the arithmetic circuit 31 and the gate circuit G, 3. And this RAM1
The operation key is determined based on the input data stored in 2 and the contents of the control counter at this time. That is, the key sampling signal output from the decoder 41 is commonly given to a plurality of keys, and the same code signal is output for each predetermined key group, so that the key input code The operation key is determined based on the key sampling signal at that time. Then, according to this determination result, the input code corresponding to the operation key is stored in the RAM 12.
and then restart the operation of the control counter.
The RAM 12 when the calendar number operation is performed as shown in Figure 6 below.
The data writing operation will be explained. As shown in FIG. 6, when the calendar number operation A is performed on the key input unit 42, the operation decoder 15 outputs a judge command JU according to the operation code ○p from the ROMII, and as shown in step B, the Z in the RAM 12 is output. The contents of function storage digit ZF of the register is “0”
Determine whether or not. That is, in step B, it is determined whether the input data is the first layer number data.
If the content of ZF above is "0", the input data is the first calendar number data, and the process proceeds to step C, where the contents of the lectern data storage digit x vT and function storage digit x F of the x register shown in Figure 3 are stored. clear. Next, as shown in step D, "1" is written in the ZF digit of the Z register to remember that the first counterfeit has been performed. In addition, if it is determined NO in step B, that is, if the calendar number has already been converted and the current input data is the second calendar number or later, proceed to step E and change the contents of the calendar number data input digit of the X register to one digit. Carry up. When step D or step E is completed, the input data En is stored in the lowest digit x vT (LSD) of the X register as shown in step F, and then the contents of XvT of the X register are stored as shown in step G. Z of Z register
Transfer to vT. The contents stored in this Z register are displayed on the display section 35 as shown on the step date. Thus, when accessing the upper end AM12, the ROM II outputs row designation addresses Su, FU, processing start column designation address SL, and end column designation address FL depending on the processing content.

Further, the ROM II gives the operation code 0p to the operation decoder 15 according to the processing content at that time, and as a result, various control commands are output from the operation decoder 15 to execute predetermined processing. For example, when executing step B in FIG. 6, the Z register is designated by the row designation address FU, and the column designation address F
Function storage digit F is designated by L. That is, the function storage digit ZF of the Z register is specified by the address of Fu and F. Then, the contents of this addressed ZF are outputted to the arithmetic circuit 31 via gate circuits G7, G, and o, and the next address of the ROMII for step C or step E is specified according to the contents of ZF. In this case, since one digit is specified, the specified digit length mode M output from the operation decoder 15 is ``1'', and the output of the inverter 22 becomes ``0'', inhibiting the operation of the matching circuit 21. In addition, when executing step C in FIG. 6, the x register is specified by the row specification address FU, and the column specification address SL
, FL specify the processing start column and the processing end column, that is, the least significant digit and the most significant digit in this case. Further, in this case, the specified digit length mode M output from the operation decoder 15 becomes "0", and the read/write command R/WI output from the timing decoder 16 becomes "1".
” and gives a write command to RAM12. Therefore, the row designation address FU output from ROMII is
It is input to the row address input terminal RAU of the RAM 12 via the gate circuit G2 at a timing other than t-row.
Then, according to the operation code ○p outputted from the ROM 11, a timing signal ○p is first outputted from the timing decoder 16 and given to the gate circuit ○3. As a result, the gate of gate circuit ○3 is opened and the ROM
I The processing start column address SL output from I is in RAM1.
2 column address input terminal RAL and the counter 20. At this time, the specified digit length mode M is "0" and the timing signal Jd is output from the timing decoder 16, so the processing start column address SL is the timing signal dd.
is set in the counter 20 in synchronization with. Then, by the row designation address FU and column designation address SL,
Specifies the least significant digit of the register. Furthermore, when executing step C, a write command is given to the RAM 12 and data "0" is given to the input terminal of the RAM 12, so that "0" is written to the lowest digit of the X register. Next, the timing signal d is output from the timing decoder 16, and the contents of the counter 20 are incremented by 11. When the specified digit length mode M is "0" and the start signal ST is not output from the flip-flop 17, the timing decoder 16 outputs the timing signal tc.
is output, and the gate of gate circuit 05 is opened.
Therefore, the output of the counter 20 is inputted to the column designation address input terminal RAL of the RAM 12 via the gate circuit ○5, and designates the digit of the X register. The counter 20 is sequentially incremented by the timing signal gd, and the X register is sequentially designated from the lower digit to the upper digit. By specifying the digits of this counter 201, the
” is written. Furthermore, the contents of the counter 20 are input to the coincidence circuit 21 via the gate circuit ○5, and
It is constantly compared to see if it matches the processed column designation address FL output from I. When the counter 20 counts up and its contents reach the processing end column designation address FL, the match circuit 21 outputs a "1" signal and the flip-flop 17 is set. As a result, Free. A start command ST is output from the flip-flop 17 and input to the timing decoder 16. As a result, the timing signal that had been output from the timing decoder 16 until then becomes "0", the gate of the gate circuit G5 is closed, and input of the column designation address to the RAM 12 is prohibited. Further, the coincidence output of the coincidence circuit 21 is applied to an AND circuit 23, which opens its gate. For this reason, the AND circuit 23 outputs timing signals et.J, and is sent to the address register 13 as an input signal via the OR circuit 26. In response to the signal applied via this OR circuit 26, the address register 13 reads the next address data and inputs it to the ROM address section 14. Therefore R
The OMII is designated with the next address and starts the next processing operation. In this way, the process of step C is completed, but
Processing is performed in the same manner in other steps in FIG. The operation when a function key is operated will be explained with reference to FIG. 7 below. In FIG. 7, when a function key is operated, the first step is step 1.
Function key input processing is performed as shown in .
That is, the function data input from the key input section 42 is temporarily stored in the buffer 43, and then output via the gate circuits G, 4 according to the key input command KE, and then outputted via the arithmetic circuit 31 and the gate circuits G, 3. RAM1
2. The function data input to the RAM 12 is written into the function storage digit xF of the x register by addressing from the ROMI I. Next, proceed to step J, and after writing "0" to the function storage digit ZF of the Z register, as shown in step K, the podium data is transferred from the register, for example, M, in the stack RAMI9 addressed by the stack pointer SP. After the function data is stored in the Y register, it is determined in step L whether or not an operation is to be executed. In other words, when performing continuous calculations such as parentheses calculations, the function data for addition, subtraction, multiplication, and division is weighted.
The weights of the function data input last time and the function data input this time are compared, and it is determined whether the calculation should be executed or not based on the comparison result. For example, "x"
If you set the weight of "÷" to be greater than "11",
The previous input function data was “×” or “÷”
If the current input function data is "11" or "1" and is small, it is determined that the calculation is to be executed, and the calculation process is performed according to the previous input function data. If the weight of the previous input function data is smaller than the weight of the current input function data, it is determined that the calculation is not performed. In step L, the contents of function data storage digit xF and YF are compared to determine whether or not an operation is to be executed. If it is determined in this step L that the operation is not performed (NO), the process proceeds to step M, and the contents of the stack pointer SP in the RAM 12 are incremented by 11. Then step N
, the contents of the above stack pointer SP are added to the stack R.
Set in address buffer 32 of AM19. Then, in step 0, the numerical data and function data stored in xvT and XF of the X register in the RAM 12 are transferred to the register, for example, M2 in the stack RAMI 9, which is addressed by the buffer 32. Then, as shown in step P,
The calendar data stored in vT is stored in ZvT of Z register.
At the same time, as shown in step Q, the several layer data transferred to the Z register is displayed on the display section 35. If the determination result in step L is to execute the operation (YES), the process proceeds to step R, where the contents of XvT of the × register and YvT of the Y register are read out to the arithmetic circuit 31, and the function data stored in the Y register is read out. A predetermined arithmetic process is performed according to the following, and the result of the arithmetic operation is stored in the X register. After the above calculation is completed, proceed to step S and decrement the contents of the stack pointer SP by 1. If the result is other than "10", the contents of the stack pointer SP decremented by 1 in step T are set in the address buffer 32 of the stack RAMI 9. do. Note that if the value is "0", the process advances to step P. However, when the operation of step T is completed, step K is again performed.
Return to , and repeat the above operations. Step (1) in Figure 8
) ~ (7), Changes in the memory contents of each register ×, Z, SP in RAM 12 and each register M, ~ in stack RAMI 9 when key operations of "203 (45)" are performed First, when the calendar number of "2" is performed, "2" is written to ×vT of the × register of the RAM 12 as shown in step 1 of FIG. 8, and this ×vT
The contents of the ZvT are transferred to the Zvr, and the contents of this ZvT "2" are displayed on the display section 35. Moreover, "1" is written in ZF because the first calendar number has been performed. Next, "When the eleventh function key is operated, step 2 in FIG.
As shown in FIG. The content "2" of xvr and the content "11" of xF are transferred to the function data storage units M and F of M. Also, when the function key is operated, the content of ZF is cleared. Processing is performed in the same way in response to key operations, and when the numeric key "5" is operated, "5" is added to xvT as shown in step 7 in Figure 8.
"1" for ZVT, "3" for Sp, "2" for MI, M, F
"11" is written in M2, "3C" is written in M2F (1, "4" is written in M3, and "11" is written in ground F. Next, the main operation of the present invention is explained using the flowchart in FIG. 9. clear(
A case in which the CE) key is operated will be explained.

Steps 8 to 10 in FIG.
This figure shows the changes in the contents of the RAM 12 and the stack RAMI 9 when the CE key is operated after the ``15'' key operation is performed. The CE key has a clearing function for normal calendar number correction and a function of clearing the latest input function data and numerical data input immediately before this function data for each operation. However, the key input section 4
When the CE key is operated in step 2, it is determined whether the content of the function data storage digit ZF of the Z register is "0" as shown in step U of FIG. In this step U, the ROM address unit 14
Address 1 of I is addressed, and "1110" is output from ROM11 as operation code ○p. This operation code ○p is decoded by the operation decoder 5 whose details are shown in FIG.
U becomes "1". At this time, the row designation address FU output from the ROMII is "10" (2), and the column designation address F
Since "1111" (15) is output for L, the Z register is specified via the gate circuit G2 at the timing of L, and the 13th row is specified via the gate circuit ○4 at the timing of the ratio. 1 of the Z register by the above address specification.
The fifth line, that is, ZP, is specified, its contents are read, and t
It is set in the latch circuit 28 at the timing of 2. At this time, since OF is "1", the contents latched in the latch circuit 28 are transferred to the arithmetic circuit 31 via the gate circuits ○ and o.
is input to. The output of this arithmetic circuit 31 is input to an AND circuit 38 via an OR circuit 37. Also,
At this time, since the AND circuit 38 is given the judge command JU, if the content of the above ZF is "1", the AND circuit 38 outputs a "1" signal, and the input pulse output from the OR circuit 26 causes a "1" signal to be output. The first address register 13
I am humbled by the bit. When M is "1", the input pulse of the address register 13 is output from the AND circuit 25 at timing t3. and is applied to the address register 13 via the OR circuit 26. Furthermore, M is “
1'', the flip-flop 17 is set at the timing t3.◇, and the start command ST is given to the timing decoder 6. Therefore, the start command ST will be output at the beginning of the next processing cycle. Furthermore, when address 1 of the ROMII is specified, the next address Na output from the ROMII is “o
loo” (4), so if ZF is “IJ”, the contents of address register 13 will be “5”, and ZF is “IJ”, the contents of address register 13 will be “5”,
0", the contents of the address register 3 will be "4". Depending on the contents of this address register 3, ROMI
The address of I is specified and the process proceeds to the next step. That is, in the determination at step U, if the content of ZF is "0", "4" is set in the address register 13 and the process proceeds to step V, where the address in the stack RAMI 9 that is indirectly addressed by the content of the stack pointer SP is "0" is written to the register. That is, in step V, the contents of the stack pointer SP are set in the address buffer 32 of the stack RAMI 9 by step N of the function key flow shown in FIG.
``0'' is written to the register in 9. First, in step V, R is set according to the contents of the address register 13.
When address 4 of OMI I is addressed, ROMI
``0010'' is output from the operation code OP of I, and the timing decoder 16 outputs the R/W 2 according to this operation code. At this time, a timing signal ta is output from the timing decoder 16 in response to the start signals ST and M, and the gate of the gate circuit G3 is opened. As a result, the column designation address SL "0000" output from the ROMII is sent to the stack RAMI 9 via the gate circuit ○3 to designate the address for the 0th digit, and at the same time, the counter 20' is set in synchronization with the timing signal ◇d. be done. Also, at this time, since no SI command is output from the operation decoder 15, the gate circuits C, . will not be opened. In this state, the timing decoder 16 outputs the signal R/W2, and the stack RAM
A "0" is written to the 0th digit of the register addressed by the address buffer 32 of I9. On the other hand, at this time, the contents of the counter 20 are read through the gate circuit G5.
0'' is sent to one input side of the matching circuit 21, and the ROMI
The processing end column designation address FL "1111", that is, "15" is input from I to the other input side of the matching circuit 21.
compared to

In this case, since there is no match, no match signal is output from the match circuit 21, and therefore no read pulse is output from the AND circuit 23 and the OR circuit 26, and the contents of the address register 13 remain unchanged. At the same time, the timing signal Jo is applied to the counter 20, and the count value is incremented by one.
Then, when entering the next digit cycle, that is, the cycle of the first digit, "0" is written to the first digit of the register in the same manner as the above-described operation of writing "0" to the 0th digit. Thereafter, from the second digit to the 14th line of the register described above, digits are sequentially designated from the second counter and "0" is written. When the count value of the counter 20 reaches "15J," this count value is supplied to the terminal RAL' of the stack RAMI9 as a column address signal via the gate circuit G5, and the 15th digit of the transfer register is set to "15J" as described above. 0" is written.
At this time, the count value "15" is passed through the gate circuit ○5.
" is applied to one input terminal of the above-mentioned - Atsushi circuit 21, so that the F applied to the other input terminal of the above-mentioned matching circuit 21 is
A match is made with L "1111" (content = 15), a match signal is output from the match circuit 21, and is applied to the AND circuit 23 and sent to the flip-flop 1 via the OR circuit 24.
Added to 7. Therefore, a "1" signal is output from the AND circuit 23 at timing t3.g, and is sent to the address register 13 as a lower panel via the OR circuit 26. The next address "0010" is set in the address register 13 by this lowering pulse, and the process proceeds to the next step W. Further, the output of the coincidence circuit 21 is read into the flip-flop 17 at the above timing 0, and the start command ST for the next step is output from the flip-flop 17. In this manner, the process of step V is completed, but while the contents of the counter 20 are counted up from "0" to "15", the memory 0 to 19 of the memory in the stack RAMI 9 addressed to the buffer 32 is
Rarely, "0" is written. That is, the contents of the register are cleared. Step W is the stack pointer S
In the step of extracting the contents of P and incrementing it by 1 and writing the result to the stack pointer SP, the ROMII sends the row specification address FU "11" and the column specification address FL "1111H".
Code signal Co “0001c Operation code ○
p "1111" and the next address Na "0011" are output.

When the operation code 0p "1111" is output, the operation decoder 15 sends commands SB, M,
CI and OF are output, and the timing decoder 6 outputs a write command R/W1 (“1”). Directive C
By outputting I, the code signal "0001" from ROMII is sent to the arithmetic circuit 3 via the gate circuit G,5.
1 is input. Then, the stack pointer SP of the RAM 12 is addressed by the row designation address FU and the column designation address FL, and is set in the latch circuit 28 at the timing of the contents it2.0. The content set in this latch circuit 28 is the gate circuit G.
, o to the arithmetic circuit 31. At this time, since the subtraction command SB is given to the arithmetic circuit 31, the content of the stack pointer SP input to the arithmetic circuit 31 is -1 due to the code signal Co "0001" (1), and the subtraction result is the gate circuit G. , 3 via the stack pointer SP
written to. Then, when the above calculation is completed, ROM1
The address register 13 becomes "0011" by the next address Na from 1, and the process proceeds to the next step X. This step X transfers the contents of the stack pointer SP to the stack RAMI.
9 is set in address buffer 32, and address 3 of ROMII is first addressed. By specifying the address at address 3, ROMI I outputs "11" as the row specification address SU and "11" as the column specification address SL.
1111", and the operation code ○p is "110".
0c "0110" is output as the next address Na. According to the above operation code 0p, operation decoder 16, timing decoder 16 to 06, M
The command and timing signal C are output. Then, the stack pointer SP in the RAM 12 is designated by the row designation address SU and column designation address SL, and
Its contents are set in the latch circuit 27 via the gate circuit G6 at timing J. This latch circuit 2
The contents of the stack pointer SP set to 7 are outputted via the gate circuit ○9 by the command OS, and set in the buffer 32 in synchronization with the timing signal ◇c. In addition, if the determination result of step U is NO, 5 of ROMII
When the address is specified, the process proceeds to step Y, where "0" is written to ZF of the Z register.

In this step Y, ZF of the Z register is set by the row designation address FU "10" and the column designation address FL "1111".
is specified. In addition, operation code OP “10
01'', the operation decoder 5 outputs M and the timing decoder 6 outputs R/WI. At this time,
Since none of OS, OF, and CI are output from the operation decoder 15, the gate circuits G9, G, and o
, G, 5 are not opened, so "0" is given to the input terminal m of the RAM 12. As a result, "0" is written to ZF by R/WI. However, the above step
Alternatively, after completing the process of Y, the next address Na "01"
10'' specifies address 6 of ROMI I, and the process advances to step Z.

In this step Z, the contents of the register in the stack RAMI 9 addressed by the data set in the address buffer 32 of the stack RAMI 9 are read out and written to ZvT of the Z register. That is, in this step Z, the row designation address FU "10", the processing start column designation address SL "0000", the processing end column designation address FL "1110" are sent from the ROMII to the operation code 0p.
"0101" is output. This operation code 0p "0101" causes the operation decoder 15 to send the S○, and the timing decoder 16 to send the timing signal t.
a, gd write command R/W1g1") is output. First, the row designation address Fu and the processing start column designation address S are output.
The zero digit of the Z register of RAM 12 is addressed by L. Further, the processing start column designation address SL is written to the counter 201 in synchronization with the timing signal gd. The contents of this counter 20 are incremented by the timing signal ◇d, and the Z register is sequentially designated from the 1st to the 14th digit. The data read from the stack RAMI 9 by addressing the buffer 32 at this time is read out from the stack RAMI 9 via the gate circuit G, 2 opened by the command SO.
It is input to AM12 and written to rows 0 to IY of the Z register, that is, ZvT. Then, when the contents of the counter 20 match the processing end column designation address FL "1110", a match signal is outputted from the match circuit 21 and given to the AND circuit 23. Therefore, a "1" signal is output from the AND circuit 23 at the timing of , and the OR circuit 26
is sent to the address register 3 as an interrupt pulse. New address data is read into the address register 13 by the input pulse, and the process proceeds to the next step. That is, the first step of the display and key sampling flow is performed. This allows the contents of Zw to be displayed on display section 3.
Displayed by 5. This completes the process when the CE key is operated. For example, step 1 in Figure 8
As shown in Figure 7, if you notice an erroneous operation and press the CE key after the key operation of "203 (45)" is performed, in this case, the first layer number is finished and the contents of ZF are Since the value is "1", the processing flow advances from step U to step Y in FIG. 9, and after clearing the contents of ZF, the memory M in the stack RAMI9 indicated by the stack pointer SP is
The content "4" of 3 is read out and set in ZvT. As a result, the data displayed as "5" changes to the previous counterfeit count data "4". In this way, the latest calendar number data is erased by the first CE key operation, but if the CE key is further operated in this state, the contents of ZF are cleared and set to "0" at this point, so step U From step V
As shown in step 9 of FIG. 8, the content "4" is cleared in ZvT and the memory M in RAMI
3. Clear the contents "4" and "11" of M3F. Next, set the contents "3" of the stack pointer SP to "1" and set it as "2", and use the contents "2" of this stack pointer SP to clear the RA.
Address the MI9 and write the memory content “3” of the ground to ZvT of the Z register, and display this held data “3” on the display unit 35.
Display at. In this way, by operating the CE key for the second time, the data before the latest input data "up to 411" will be erased.If you operate the CE key in this state further,
As shown in step (10) in FIG. 8, the data "3 (1) before 411" is deleted. That is, each time the CE key is operated, unit data including function data is deleted one after another. Also, the previous data is displayed on the display section.In the above embodiment, the CE for layer number correction is
Although the key is also used as a clear key after key function operation, the present invention is not limited to this, and it may also be used in combination with other function keys, and it goes without saying that a key dedicated to clearing the stack RAM may be provided. . Further, although numerical data and function data are stored in the same register, the present invention is not limited to this, and storage units for each data may be provided independently. As described above, according to the present invention, input data can be corrected after a function key is operated. Furthermore, not only the last input data but also the calendar number data can be sequentially erased in each unit, that is, in units of function data, each time the instruction key for correcting the input data 1 is operated. Therefore, when processing long calculation formulas such as parenthesis calculations, even if you notice an input error after pressing a function key, or even if you find that there is an error in input data several times ago, you can erase all input data. erroneous data can be erased. Therefore, error data can be easily corrected, and actual processing time can be shortened. Moreover, since the data immediately preceding the data to be cleared is displayed each time the instruction key is operated, it is possible to easily determine which data has been cleared, which is effective.

[Brief explanation of the drawing]

The drawings show one embodiment of the present invention; FIG. 1 is a circuit configuration diagram, FIG. 2 is a diagram showing timing pulses used in FIG. 1, and FIG. 3 is a diagram showing the configuration of the RAM in FIG. 1. 4 is a diagram showing an example of the configuration of the ROM and operation decoder part in FIG. 1, FIG. 5 is a diagram showing the correspondence between operation codes and control signals, and FIG. A flowchart showing the process when
Fig. 7 is a flowchart showing the processing when a function key is operated, and Fig. 8 is a flowchart showing the processing when a function key is operated.
FIG. 9 is a flowchart showing the process when the CE key is operated. 1 1...・．． ．． ROM, 1 2...RAM
, 1 4...ROM address section, 15...
...Operation decoder, 16...Timing decoder, 19...Stack RAM, 20...
... Counter, 21 ... Matching circuit, 42.
...Key input section. Figure 2 Figure 3 Sphere Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9

Claims (1)

[Claims] 1 Calculation memory that stores numerical data, various function data weighted according to the calculation, calculation results, etc., and a calculation memory that stores the weight of the function data input at that time each time the function key is operated. a determining means for comparing the weight of the previously inputted function data to determine whether or not the calculation can be executed; a calculation means for performing calculation processing according to the data; and a calculation means for temporarily saving the numerical data and the function data as one unit from the calculation memory according to the determination result of the calculation means in a predetermined order. A temporary storage memory to be stored, and each time an instruction key for correcting the contents of this temporary storage memory is operated, data stored in the temporary storage memory is reversed in the predetermined order and unit by unit. a small electronic calculator comprising means for clearing numerical data in the temporary storage memory and writing the numerical data stored before the cleared data in the display data storage memory in the calculation memory. clear control method.