JPS6145350A - Miniature electronic computer - Google Patents

Abstract

PURPOSE:To improve the operability of a miniature electronic computer by using the input permissible numerical data as the data of a mantissa part regardless of the number of digits and furthermore attaining the input of the data of an exapprox.= ponent part. CONSTITUTION:A ROM1 delivers various microinstructions in response to the address signals delivered from a ROM address 2. A RAM3 stores both numerical data which are supplied in the form of data of the mantissa and exponent parts respectively. The upper (m) digits of the mantissa part data are displayed to the (m) digits of a display part 24 together with the exponent part data displayed to the (m) digits respectively. While the decimal points of the mantissa part data are displayed within all display digits including the display digits for exponent part data.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a small electronic calculator that processes data expressed in exponential form.

[Prior art and its problems]

Recently, when inputting and calculating ordinary numerical data that is not expressed in an exponential format, it is done with (m + n) digits, and when inputting and calculating numerical data that is expressed in an exponential format, the mantissa is m digits, A compact electronic calculator of the so-called index method, in which the exponent part uses three digits, has been developed and put into practical use. Conventionally, in this type of small-sized electronic calculator, the number of digits that can be placed in the mantissa data of numerical data expressed in exponential form and the number of digits that can be operated on are limited to m digits. In other words, when inputting numeric data expressed as an exponent, by operating the last dedicated key, the first input mantissa data is moved to at least the upper n digits, and the exponent part is transferred to the lower n digits. A step is taken to enter data. By the way, the number of digits for the first input data can be up to (m+n) digits.

If the number of digits of this data exceeds m digits, and you want to use this data as mantissa data, the mantissa data will not be carried forward even if you press the special key for inputting exponent data. It is not possible to input exponent data into . In this way, in the conventional small electronic calculator using the exponential method, m
Data exceeding digits cannot be used as mantissa data. Therefore, when inputting numerical data expressed in exponential form, the operator must always take into consideration that the input mantissa data does not exceed m digits. did not become.

[Purpose of the invention]

The present invention was made in view of the above circumstances, and it is possible to use input numerical data that is not expressed as an index.

It can be used as mantissa data regardless of the number of digits.

Furthermore, another object of the present invention is to provide a small-sized electronic calculator that also allows input of exponent data.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to one drawing. F
Figure A3J1 is a circuit configuration diagram of a small electronic calculator of the present invention. In the figure, 1 is ROM (read only memory)
The ROM 1 stores microinstructions for executing various operations of the computer, and outputs various microinstructions in response to address signals output from the ROM address section 2. One microinstruction is *8u
y F U *SL, PL, Co, M, OP, Na
In each case, a predetermined binary code is fixedly installed.

Each binary code of the microphone instruction is output simultaneously and in parallel according to the address designation of the ROM address section 2. Sυ,FU specifies the row address of RAM (random access memory) 3, which will be described later.
8U is inputted to the terminal UA of the RAM3 via the gate circuit G1, and FU is inputted to the terminal UA of the RAM3 via the gate circuit G. Gate circuit G.

is opened when the timing signal t which is periodically output from the timing signal generating circuit 4 is output.

On the other hand, the timing signal t is supplied to the gate circuit G2.

Since it is applied via the inverter circuit 5, it is opened at times other than when the timing signal t1 is output. Similarly, the timing signal output from the timing signal generation circuit 4 is shown in FIG. The timing signal tl#t2tt3 is a clock pulse ψ.

The signals are output sequentially and periodically in synchronization with ψ. Then, every l cycle of the timing signal t1 to t, a clock pulse ψ
D=t, ·ψ is output. Among the above microinstructions,
SL and PL designate the column address of the intestine 13. Normally, SL is paired with the row address designated by SU, and tfcFL is paired with the one row address designated by FU. SL is connected to terminal 1. of the RAI 1143 via a gate circuit q that is opened when a timing signal ta is output from a timing decoder 9, which will be described later. PL is input to terminals 1.A of the RAM 3 via a gate circuit G4 that is opened when the timing signal tb is output from the timing decoder 9. Input to A. The above timing signals t& and tb are normally expressed by the logical formula t
a = Me ST + M @t, .

tb: A signal obtained by Mt. Details of signals M and ST will be described later, but when one microinstruction is an instruction that ends in one digit period, signal M outputs the output period (one digit period) 1 of this microinstruction. Signal sT outputs the first digit period 1 of each microinstruction. Therefore, if %M=1,
ta=t, tb==t, :t2+t, etc.], the address of RAMJ during the timing signal t1 output period is specified by the second row address sU and the column address SL, and the timing signal t, ~t, the address of RAMJ during the output period The address of is specified by a row address FU and a column address FL. If one microinstruction requires multiple digit periods, M=O (#), then t@=BT, J,=
It becomes O. That is, the first digit period is 81. is outputted via gate circuit G, and becomes the column address of RAM3. Furthermore, the value of this sL is determined by the clock pulse ψd=
This counter 6 is input to a counter C which performs a counting operation in synchronization with ψD·M, and this counter 6 performs a down or up counting operation (depending on the presence or absence of a DN signal, which will be described later). From the second digit of the microinstruction consisting of the above-mentioned plural digits, a gate circuit G opens when a timing signal tc==M-8T is output.

The value of the counter 6 is inputted to the terminal LA of RAMJ via , and this becomes the column address of RAMj. At the same time, the value of the counter 6 is again fit-packed to the counter 6 via the gate circuit G1 and is counted down or up, and is input to one side of the matching circuit 7. In the microinstruction consisting of the above multiple digits, the gate circuit G
4 is closed, and PL output from ROMJ is input to the other matching circuit 7. The value of counter 6 is PL
When they become equal, the coincidence circuit 7 outputs a coincidence signal, and as will be described later, this microinstruction consisting of a plurality of digits is terminated. That is, in a microinstruction consisting of multiple digits, the processing start digit of the storage area (hereinafter referred to as a register) in RAM 5 specified by SU or FU is specified by sL, and the processing end digit is specified by PL. Ru. Oka, micro-commands.

At the time of a shift command to shift the register of RAMJ to the left or right, each of the above timing signals is as follows.

ta"tst Lb=0, tB=t1・sT. Also, among the above microinstructions, C0 is also used as a binary code for numerical values, codes, etc., and controls the gate circuit G6, which is opened when the signal CI is output. In addition, M of the above microinstructions is a mode signal that outputs 1 when one microinstruction is completed in one digit.

Among the above micro instructions, Op is addition and subtraction.

It outputs various instruction codes such as transfer, judgment, left shift, right shift, display, and key sampling. After this instruction code Op is decoded by the operation code decoder 8, it is input to the timing decoder 9. This timing decoder 9 receives signals CI, OF, and O according to each of the above instructions.
8, ID, KE.

Selectively outputs SB etc. In addition, the timing signal tl#t, which is outputted by the timing signal generation circuit 4, is
t, and clock pulse ψ1. ψ1. ψD is given as a timing signal to the gate circuits G, , G, , G, etc., and is also input to the timing decoder 9. Therefore, the timing decoder 9 outputs the timing signal &Abttc r td and the signals DN, 几/Wt-selectively. The signals CI, OF, O8
, ID, and l are gate circuits Q@, G@, respectively.
G 1゜＠ (Jll # (JH 1 elevation signals. When these signals are 1, the corresponding gate circuit is opened. This is the signal BBY1 subtraction designation signal, and this signal S
When B is input to the arithmetic circuit 16, the arithmetic circuit 16 decreases n
perform an action. Also, the signal ψa.

ψb and ψC are buffers respectively 7 Bl r Bl t
It is given as a read clock signal of Ba, and expressed as a logical formula, ψa=ψD −OP, , ψb=ψD@O
P,,ψc=t! *ψ・Op, Deoru. However, b Opl.
= Decimal point display data output command 5OP2 = Display data output command, 0P3 = Key sampling data (count digit data) output command. The angle ψd is the same as the operation signal of the counter 6. Expressing it in a logical formula, ψd=ψD-M・OP4+ψ
,・Ops. However, 5OP4 = shift command.

As described above, the signal DN is a signal sent to the counter 6 to designate a down-count operation.

The signal edge is a signal specifying the fourth reading of RAA43. Further, the mode signal M is also input to the timing decoder 9.

This mode signal M is the OR circuit 10. and AND circuit 11
It is also inputted to one of the coincidence circuits 7 through the inverter circuit 12 as a hey enable signal.

The coincidence signal of the coincidence circuit 2 is input to the other of the OR circuits IQ and one of the AND circuits 13. The mode signal M and the coincidence signal are input to the flip-flop circuit 14 via the OR circuit IQ, and the output signal sT is input to the timing decoder 9. The above clip-flop circuit 1
4 because it operates in synchronization with the clock pulse ψD at digit intervals.

The signal sT is a signal output during the first digit period of each microinstruction. A clock pulse ψD is input to the other of the AND circuits 1 and 13, and both of the AND circuits 11 and 13 output the signal ψe as a signal ψe through the OR circuit 1st-, which serves as a read clock for the address conversion circuit 17. N of micro instructions are RO
This is a signal specifying the microinstruction readdress of the next step of the microinstruction currently being executed in M1, and is input to the address conversion circuit 17.

Furthermore, AND circuits 18 and 19 are input to this address conversion circuit 17. The data from the arithmetic circuit 16 is input to one side of the AND circuit 18, and a carry (or borrow) is input to one side of the AND circuit 19.
The other side of the timing decoder 19 receives the signal JU from the timing decoder 9.
is entered. This signal JU is output at the time of a judgment command, and at this time, the address conversion circuit 17 executes the OR addition of the contents of N1 and the output of the AND circuit Is, 19, and calculates the address indicating the next step of the ROMJ. and is sent to the ROM address section 2. Next, the above RAM
The configurations of the RAM J, the arithmetic circuit 16, etc. controlled by the J microinstruction will be explained. RA? l, f j
As mentioned above, the row addresses SU and FU input to the terminal UA and the column address SL input to the terminal LA
, PL is addressed by PL, and the name is RUGA =
The data within the address specified when 0 is the output terminal OU
The data is read out from T as parallel 4-pit data.

Input terminal IN within the address specified when rule = 1
Writes parallel data given by .

Usually, the above signal R/)V is a timing signal t, ~t
, is specified as I (/w=0) to be read at the time of output, and written at the time of output (, R1/
W=1). In addition, the gate circuit G,
, G, are normally synchronized with the timing signal tlK, so the data in the 3rd scale specified by SU, SL is read out from the output terminal OUT when the timing signal t1 is output, and the timing signal 11/ψ1 The signal is stored in the latch 20 via the gate circuit G, which is opened at . Also, gate circuit G2. G4 is normally a timing signal 1, = 1
, +1. Since it is synchronized with FU, Ii'
The data in RAM 5 specified by L is the timing signal t.

is read out at the time of output, and stored in the latch 21 via the gate circuit q which is opened by the timing signals t and .psi.1. The data stored in the latches 20 and 21 are stored in the gate circuit G opened by the signals O8 and OF, respectively.
. , Q, to the input terminal 8. of the arithmetic circuit 16 via. Sent to F.

The arithmetic circuit 16 executes addition or subtraction in parallel based on data applied to input terminals S and F.

The above operation result data for performing the subtraction is outputted from the terminal and applied to the input terminal IN of the RAM 3. Further, the carry (or borrow) data of the arithmetic circuit 16 is outputted to the terminal C in large numbers. The above operation result data given to the input terminal IN of RAM3 is outputted to FU when timing signals t and Q are output.
, F'L is written into the RAM 5 specified by the address. Further, the parallel data of the calculation result of the calculation circuit 16 is inputted to one side of the AND circuit 18 via the terminal-or circuit 22, and the carry (or borrow) of the calculation circuit 16 is input to one side of the AND circuit 19 from the terminal C. is input to. Further, one digit (count digit) of the storage area IZ in the RAM 5 is counted up via the arithmetic circuit 16 at the time of 1 display and key sampling. The count value of this count digit is given to the back 77B via the gate circuit G and the latch 20° gate circuit G1°. The value of the count digit is read in the buffer 7B1 in synchronization with the clock pulse ψC.The value read into the buffer 1B is as follows.
The signal is output via the decoder 23 as a digit signal on the display section 24 and as a key sampling pulse on the key input section 250. Furthermore, two registers in the RAM 5 are used as display registers. When displaying data, the value of the count digit is first read, and this value is sent to the gate circuit q and the latch 20. It becomes the RAM30 column address via the gate circuit G11.

At this time, the row address specifies the Z register, so data in a predetermined digit of the display register zO corresponding to the value of the count digit is read out, and this data is sent to the gate circuit G and the latch 21. The signal is applied to the buffer B via the gate circuit G.

Buffer 7B converts the given data to Clockz (Rus ψ
Read in synchronization with b and further decoder.

26 to the display section 24. As mentioned above, 1
Since the corresponding digit signal is sent to the display section 24 from the decoder 23, the result of the input Q is shown by the content of the count digit among the digits on the display section 24. The contents of the same digit of the two registers are displayed in the digit. Further, )(71B, ) is read in synchronization with the decimal A7''-1't clock pulse ψa, and furthermore, this data is sent to the display unit 24 via the depuder 26 and displayed in the same manner as above. ,
The key input section 25 has a line to which the above-mentioned key sampling signal is supplied and a key common line outputted to the rough IB4 are arranged in a matrix, and has a key at the intersection of each line. The data is input to the terminal S of the arithmetic circuit 16 via the gate circuit G1□, which is opened by the signal KE output at the time of the key sampling command.
Further, from the terminal of this arithmetic circuit 16, the data is written to pRAM s. At this time, when the key common data is detected in the buffer B4, the counting operation of the count digit is stopped, and the operation key is determined based on the count value at this time and the data in the buffer 1B4. If it is a numeric key, the numerical data corresponding to that key is displayed in the display register (
2 register), and if it is a 71-link key, the Na of the ROM J is changed by the address conversion circuit 17 according to the judgment result, and the R is input to perform the Wr constant processing.
The first address of AM addresses is specified.

If the column address input to the RAMJ terminal is 0~
In step 15, the storage area in RAlVis that is designated when row address 0 is input to terminal UA is called register X. J! The 1st column address is 0 to 15, and the row address is 1.
The storage areas in RAMj specified when 2 and 3.4 are input are respectively stored in register Y and register 2. Register A
, is called register B. The storage area of the register X is shown in FIG. 3 (-). Register The answer is stored and the digit Xs K specified by the 1st column address value 11 stores the sign of the data in the digits X0 to X1°, and the digits X P 1 to XP2 specified by the column address values 12 to 13 The digits X0 to X. Data indicating the decimal point position of the data in is stored, and the digit XDP specified by column address value 14 contains a decimal point flag indicating whether or not the decimal point key has been operated. An EXP7 lag indicating whether or not the index key i has been operated is stored in . Register Y stores the arithmetic number or decimal point, and during key sampling and display, * indicates the decimal point display position of register Z, which will be described later.According to the data of digits zp1 to digit P2, a predetermined digit of register Y is used for decimal point display. data is stored.

Register zhti number and display register shown in Figure 3 (
As shown in b), the digits z0 to z1° specified by the 1st column address and the value 0 to 10 contain data for display at the column address value 1.
The digit Zp specified by 1 stores data indicating the number of digits of the display data, and the digits Zp1 to ZP2 specified by the 1st column address values 12 to 13 store data indicating the decimal point display position of the display data. Ru. Registers A and B are temporary storage for calculations and auxiliary registers in which Mi 7 and y are stored.

Next, the operation of the circuit configured as described above will be explained.

FIG. 4 is a flowchart representing a series of microinstructions stored in the ROM J.

Each processing step of the series of microinstructions described above expressed in this 70-chart will be explained below. First, in step (5), the key sampling and register Z samples the data supplied from the key human power section 25.
Display of data within is performed as described above. When it is detected in step (5) that a numeric key for inputting a numerical value such as 0 to 9 has been operated, the process proceeds to step (b), and in step (B) The numerical data obtained is stored in the least significant digit of register Z. Next, the process advances to step (C)K, and in this step (C), it is determined whether or not the key Kokuji for inputting index data has been previously operated based on the presence or absence of the uP flag.

BXP 72 is stored in the 16th digit of register X, so the microinstruction for the judgment operation shown in step 0 is
FU=O, PL=15. C0=EXP flag, M
=1, op=judgment instruction code, jlJa=,X
Outputs the address of step (I). Order of the above judgment;
- code is input to the timing decoder 9 via the operating decoder 8, and from this timing decoder 9,
Signals CI, OF, 8B, JU, tb, B4/W, etc. are output. Therefore, the digit XEXP (see FIG. 3 (&)) of the register X specified by F U * F L above is the gate circuit G? and 2tsuchi 21. The signal is input to the terminal F of the arithmetic circuit 16 via the gate circuit q9. On the other hand, the binary coded =-doco which has stored the EXP7 lag is input to the 8 terminals of the arithmetic circuit 16 via the gate circuit G6. This is because the arithmetic circuit 16 is designated for subtraction by the signal SB.

The data input to the terminal S is subtracted from the data input to the terminal F, and as a result, the terminal new data and the terminal C carry (or borrow) data are output. The above data is inputted to the address conversion circuit 17 via the OR circuit 22 and the AND circuit 18 to which the signal JU is inputted to one of them, and the above-mentioned middle Yari (or borrow) is inputted to the signal JU to one of the AND circuits. The address conversion circuit 12 is inputted to the address conversion circuit 12 via an AND circuit 19. That is, EXP7 to h X1hP? If there is a signal, the data and carry output from the arithmetic circuit 16 are both 0. Therefore, at this time h
The address of step (1) input from Na to the address conversion circuit 17 is not converted and is sent to the first step (
The address for outputting the microinstruction in I) is specified.

On the other hand, when the arithmetic circuit 16 outputs the data or carry, the output address of step (1) is ORed with the data or carry in the address conversion circuit 17 to convert the address. (to) address. In the following 70-, a detailed explanation of the above-mentioned judgment operation will be omitted. In this way, if EXP 7 lag is not detected in step (C), proceed to step (B), and if -10,000 EXP 7 lag is detected, proceed to step (I). It is determined whether the key opening for inputting has been previously operated or not based on the presence or absence of a decimal point flag, and if this flag is detected, the process proceeds to step (g)). Digit Z indicating the decimal point position of display register 2 in step E
pi,! A numerical value of 1 is added to PR. The microinstruction for the operation shown in step (6) is Fg=2.1
)=12*FI,=13tCQ=1,M=O,0p=
Addition of the binary code and the data in RAM 3, Na = address of step.

At this time, the timing decoder 9° rotation signal CI.

OF, ψd*ta is output. For this reason, FU,
zPl of register Z specified by address of SL
The data in the gate circuit G is read out.

and the arithmetic circuit 16 via the latch 21 and gate circuit G.
is input to terminal F of On the other hand, since the value "1" of the binary code of Co is input to the terminal S via the gate circuit G6, the calculation circuit 16 performs zp1+1 and obtains the calculation result.

is register Z+7 specified by FU, 8L -e##-
) written to Zpl. The above operation is performed using the timing signal t.
, ~t, in one cycle. On the other hand, the value 12 of 8I is set to counter 6.

It is counted up to 13 by ψdK, and becomes the column address for the next cycle t, period to t1.

Furthermore, since the M=00 output is given as an enable signal to the matching circuit 7 via the inverter circuit 12, the matching circuit 1 detects a match between the value of the counter 6 and the value of PL.

That is, in the second cycle, data in zpz is read out, and gate circuit G7 and two gates 21. The signal is input to the arithmetic circuit 16 via the gate circuit G and the gate circuit G.

If a carry occurs in the previous addition operation, the carry and the above data are added and written to ZP2 again. At this time, the coincidence signal from the coincidence circuit 7 is input to the AND circuit 13.

The clock signal ψD inputted to the other side of the AND circuit 13 becomes the read clock ψ of the address conversion circuit 17 via an OR circuit. The first step (g) is entered as
Reads the address N& for outputting the microinstruction. Further, the coincidence signal is inputted to the clip-flop circuit 14 via the OR circuit 10, and the 7-rip 70
The K signal sT is output to the timing decoder 9 during the first cycle period (from t to t, at the time of output) of the first step (G) from the turn k14. In the following 70-, the code addition as described above is A detailed explanation of the operation will be omitted.Next, in step α, Zp1s of display register 2 after addition of 1 is
The content of Zp2 is the digit x that indicates the decimal point position of the numeric register
pl # "Transferred to pR. The microinstruction output in this step (g) is Sυ=2s FU" O
v Sl, ” 12 * F l, ” 13 +M=
0. Op=transfer, N8=address of step 0.

That is, when the timing signal t1 of the first cycle is output, the digit zp1 of the register 2 specified by hSU*SL is read out to the 2-channel 20 via the gate circuit G, and when the timing signal t1 is output, the digit zp1 of the register 2 specified by 20 data is sent to h'UtSL via the gate circuit OH and the arithmetic circuit 16.
The timing signal t of the 0th cycle written to the <IXO digit xps is specified by vji,;
The digit Zp2 of the register 2 specified by the counter 6 incremented by U' and ψd is stored in the latch 2oVc via the gate circuit q8, and when the timing signal t is output, the data stored in the latch 2o is Circuit G. and bFU* digit xP of register X specified by counter 6 via arithmetic circuit 16! written to,
At the same time, a coincidence signal is output from the coincidence circuit 7, and this step (g) is completed. In the flow below, as mentioned above,
A detailed explanation of such transfer operation will be omitted. The above steps (
After completion of step (g), proceed to step (q). On the other hand, if the decimal point flag is not detected in the step (to), proceed to step 0. In step 0, the digit where the digit data of the digit and display register 2 is stored. The contents of z0 to 2.. are transferred to digits x0 to x8 of register The numerical value 1 is added to Zp. Then, the process proceeds to step (I). In this step (I), the digit of register 2 is
The decimal point display position of Ple”P2 is detected.
Decimal point data is written to the digit of the Y register indicated by the data in "PIp"pR.

Furthermore, the presence or absence of data 8 indicating that the 1-digit X, K digit data is negative is detected, and if it is negative.

One code is input at the beginning of the register zo position number data.

After this, the process returns to step (A)K again.

Then, in this step (in AJ, the number data and decimal point are displayed and key sampling is performed. For example, -123456789X10" is entered from the key input section 25).

Day, a], m... En, (9) 1 fox to operate the keys. At this time, the operations from step 4 to step (I) described above are performed for each key operation. However, in the process (6) of numeric filling, numeric data up to 10 digits can be input. The storage state of the registers X and Z and the display state of the display section 24 after the above series of key operations are completed are shown in FIG.

That is, since the cause key and the mouth Φ- have not been operated yet,
The operations in steps (E) and (g) are not performed, and the digits zP1#"PI and "PI s" pR indicating the decimal point position are both 0.

Also, Zp that stores the number of digits of IIEE number data is #,
tj! This is because each time you press the L key, you get +1 in step (c).

It is 9. Furthermore, 8 is stored in the digit X for storing the code after one day's key operation, indicating that the set number data is negative. Therefore, the display section 24 displays a decimal point in the first digit, sl.

A minus sign is displayed in the digit.

Then, in step (A), when it is detected that the key factor has been operated, the process proceeds to step (JJ). In step (J), register X O digit x is input.

It is determined whether the O content is 0 or not. That is, it is determined whether the digit data stored in register X represents a negative number or a positive number, and if the content of m'Xa is 8, that is, represents a negative number, the process advances to step (to). Next, in step 4, 1 is added to the contents of digit Zp in register 2 indicating the number of digits to be entered. Then, proceed to step (6). On the other hand, in step (J)
If the contents of , are 0, that is, the contents of register X are numeric data representing a positive number, the process immediately proceeds to step (g).

In other words, if the digit data is negative, the sign between registers 2 and -
ZF+ 1 is performed to treat the data as one digit worth of data. In the above example, the digit data is negative (Xs=8), so x is determined to be '10' in step g), and is incremented by 1 in step (translation).

zy=10. Next, in step (6), 9 is subtracted from the contents of digit zF of register Z, and register Z
The number of digits of the numeric data including the sign inside is detected.

Then, when the number of digits of the above-mentioned number data is 10 digits, the process advances to step), and in this step MVc, the register ZOz,
~z1°Q The memory contents are carried up by one digit. After this, the process advances to step (to), and in step (to), 1 is added to the contents of the digits "Pi" and "P2" indicating the decimal point position, and after the step, the process advances to step leap. On the other hand, if the number of digits of the numeric data is 9 digits in step (g), proceed to step (q).

At the third step (Q, the contents of register ZQ are incremented by one digit. Then, the process proceeds to step (g), and in this step (g), the digit is further incremented by one digit. After this, the process proceeds to step Q, and the contents of register ZQ are incremented by one digit. (In Q, 2 is added to the contents of the digit "Pie" P2 indicating the decimal point position, and the process then advances to step leap.

Further, in step (g), when the number of digits of the digit data in register Z is 8 or less, k proceeds to step (g), and in step (5), the digit data is incremented by one digit. After this, proceed to steps (S) and (T), and in each step, the digit data is incremented by one digit, and then
Proceed to step 0. “PI” in step (goods) *
``3 is added to the contents of p2, and the process then proceeds to step (to).The above step (goods), (0).

(P), (6), (S), (The carry operation microinstruction at T5 is FU=2, 8L=10.Fl, =O,
M=0. OF=carry shift command, N=address of next step. Further, the timing decoder 9 outputs the signal OF and tl"tl ttC=tl・8t, ψd=ψttDPJ=ts+ta. That is, the first cycle (timing signal t, ~t, operation at the time of output) is 5L=l when the timing signal t1 is output.
O is read into the counter 6 which counts down at ψd=(t,+t,)·ψ, and when the timing signal t is output, the counter 6 outputs the signal to the gate circuit G.

The count value 9 is input to the terminal of the RIAM 3 via the counter 6, and is fed back to the counter 6 again. At this time, the register ZOZ specified by the address of FU=2 and the count value 9 of the counter 6 is read out and stored in the latch 2 via the gate circuit G.
At this time, the counter 6 counts up by ψd = tt ``ψ1 and reaches 10 when outputting the primary timing signal t1.

The value 10 of the counter 6 is outputted to the gate circuit G.

The signal is inputted to the terminal LA of the RAM 5 via the terminal LA. At this time, the data stored in the latch 2111C is.

2 of the register Z specified by the address of sFU 2 and the count value 1o of the counter 6 via the gate circuit G and the arithmetic circuit 16. . written to. In the above one cycle, the 07'-data in register ZOzg is one digit higher than i□. written to. In the next cycle, the value of the counter 6 becomes 8 when the timing signal t is output, and the value of the counter 6 becomes 9 when the timing signal t is output. Therefore, the data in z is 2.
written to. Thereafter, the carry is carried up by one digit in each cycle in the same manner until the counter 6.degree. value becomes 0 and the coincidence circuit 1 detects a coincidence signal with the FL value 0. A detailed explanation of the above-mentioned carry operation will be omitted in the following section. In an embodiment of the invention, the steps
Since zp=io in step (g), proceed from step (g) to step -, and after z0 to z1° are carried up by one digit, zpz, zpt = 1. becomes.

Next, in step (g), the digit of register 2 is set to "0pz".
1 The contents of 0 are cleared in the next step (g).
Next, proceed to step (BA), and in this step (BA), the third digit of register 2, ZJ K
Blanking;-do is memorized and after this step (I)
After the decimal point display position of "Plt" pl and the sign of Xl are detected in step (I), they are displayed in step 4. The states of the registers X, Z and the display section 24 at this time are shown in FIG.

In this way, the mantissa part of the digit data is r-1 in the mantissa display part.
As in 234567J, the upper eight digits including the "-" display are displayed, and the decimal point is displayed at the second digit in the instruction display section.

As a result, the operator.

Although the last two digits of the number "89" cannot be visually recognized, the display of the decimal point makes it easier to recognize that the e number data is 9 digits. At this time, no index data has been input into the index section yet.

Next, when data ``12'' of the exponent part is entered into the key input section 25, registers 1 to 1 of register 2 are
EXP 7 lag is detected in the 5th step C) inputted in the second digit, and the process immediately proceeds to process (I). This process (I)
After that, it will be displayed as a processed prisoner.

The states of the registers x, z and the display section 24 at this time are shown in FIG. That is, the mantissa part is 9 digits.

The upper seven digits are "-12,34567J" and the exponent part is "12".

Next, when it is detected that the 777 comb key for performing four arithmetic operations etc. has been operated in the step mentioned above, the process proceeds to step (BB). In this step (BB), from the contents of digit J and $6 of register 2, digit Xpl of register X,
Xp212) The content is subtracted from the digit z of register 2.
,,z6 K is transferred. In this case h ”PZ
= O or PI et al. The value of zlzo is 12. Next, Ste, Tsubu (
BC), and in this step (BC), the contents of digit Zxe Z@ of display register 2 are the same as digit
Transferred to PI *Xp2. Therefore x p 2
x p 1 '' 12.Next, the process advances to step (BD), and in this step (BD), various calculations corresponding to the 777 comb key are executed.

The result of this operation is stored in register X. In the above-mentioned embodiment, since the number can be set by one operation of the 7-key key immediately after setting the number, no calculation is performed and the process proceeds to the first step (BE). In this step (BE), the contents of register X are transferred to register 2. Next, proceed to step (BF).

In this step (BF), the digit of register 2 “Pj
*” 11 for the number of displayed digits is added to the contents of PZ and Nil
ZIN=22. Then, proceed to step (BG). In this step (BG), digit z of register 2
It is determined whether 10 is O or not, that is, whether there is numerical data in the digit z1°. If it is determined in this step (BG) that there is no numerical data in digit z1°, the process proceeds to the next step (BH), and in this step (DH), z0 to "10" of register 2 is incremented by one digit. .After this, proceed to step (BI), and in this step (BI), 1 is calculated from the contents of digit Zp1 *zp2 of display register Z.
is subtracted and the process returns to step (BG) again.

On the other hand, in step (BG), digit 2. . If it is determined that there is data, the process proceeds to the next step (BJ). In the above embodiment, z0 to 2. . is carried up by two digits and h
ZP2 ZP1=20. This step (BJ)
Then, Vr20J of digit zpt ZP2 of register 2 is transferred to digit "le"O.

The process advances to (BK), and in this step (BK), the contents of digit Zp of register 2 are referred to and it is determined whether the set number data stored in register ZK is a positive number or a negative number. Then, when the content of digit 7) zy is 0, that is, it is a positive number, the process advances to step (BL), and in this step (BL), digit zPI of register 2, "PZ" is set to 1.
0 is transferred. After this, the process proceeds to step (BN). As in the above embodiment, in the step (BL)
When the content of , is 8, that is, when the set number data stored in register Z is a negative number, the process proceeds to step (BM). In this step (BM), the digit "pl" of register Z
9 is transferred to p”pl. And after this step (
BN) & X kP r X DP t Z F
In the first step (BA) where 2. is cleared. The blanking code is input to ZP2 t in the next process (I).
Data "9" in zp1 and data "8" in x8 are detected.

During the process, a decimal point is displayed in the 10th digit of the display section 24, and a - is displayed in the most significant digit. The state at this time is shown in FIG.

〔Effect of the invention〕

As explained above, according to the present invention, numerical data that can be input can be used as mantissa data regardless of the number of digits, and it is also possible to input exponent data. When inputting data, there is no need to consider the number of digits of the mantissa data, and operability can be improved. In particular, the decimal point related to mantissa data is displayed within all display digits, including the display digits that display exponent data, making it easier to check the place value of numbers that cannot be seen beyond the number of mantissa digits. There are advantages.

[Brief explanation of drawings]

FIG. 1 is a circuit configuration diagram showing an embodiment of a small electronic calculator of the present invention. ! Figure 2 is a time chart, Figure 3 (&)
(b) is a storage state diagram of register X and register Z, respectively;
FIG. 4 is a 70-chart representing microinstructions stored in ROM J, and FIG. 5 is a state diagram for explaining each of the above embodiments. DESCRIPTION OF SYMBOLS 1...ROM, J...RAM, l6-...Arithmetic circuit, 24...Display part, 25...Key manual part. Applicant's agent Patent attorney Takehiko Suzue Figure 2 φ0

Claims (1)

[Claims] It has a display digit capacity of at least m + n digits, and when displaying data expressed in exponential form, it has a display section that separately displays m digits of mantissa data and n digits of exponent data, and at least m + n digits of numerical data can be input. In a small electronic calculator having an input section and capable of calculating data expressed in exponential form, a first section for storing numerical data inputted as mantissa data;
a second storage means for storing numerical data input as exponent part data; and displaying the upper m digits of the mantissa part data in the first storage means in m digits of the display part; and display means for displaying the exponent part data in the second storage means on n digits of the display section, and a display for displaying the exponent data by the decimal point of the mantissa data stored in the first storage means. A small electronic calculator characterized by comprising means for displaying within all display digits including digits.