JPS6229912B2 - - Google Patents
Info
- Publication number
- JPS6229912B2 JPS6229912B2 JP56196489A JP19648981A JPS6229912B2 JP S6229912 B2 JPS6229912 B2 JP S6229912B2 JP 56196489 A JP56196489 A JP 56196489A JP 19648981 A JP19648981 A JP 19648981A JP S6229912 B2 JPS6229912 B2 JP S6229912B2
- Authority
- JP
- Japan
- Prior art keywords
- insulating layer
- type
- forming
- semiconductor
- polycrystalline silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 10
- 238000004519 manufacturing process Methods 0.000 claims description 9
- 239000000758 substrate Substances 0.000 claims description 5
- 239000012535 impurity Substances 0.000 claims description 4
- 230000003647 oxidation Effects 0.000 claims 2
- 238000007254 oxidation reaction Methods 0.000 claims 2
- 238000000151 deposition Methods 0.000 claims 1
- 239000002184 metal Substances 0.000 claims 1
- 150000004767 nitrides Chemical class 0.000 description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 10
- 238000000034 method Methods 0.000 description 5
- 229910052796 boron Inorganic materials 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8222—Bipolar technology
- H01L21/8226—Bipolar technology comprising merged transistor logic or integrated injection logic
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Bipolar Integrated Circuits (AREA)
Description
【発明の詳細な説明】
本発明はセルフアラインを用いた半導体装置の
製造方法に関し、特に集積注入論理回路素子（以
下、I2Lとする）の製造方法に関するものであ
る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device using self-alignment, and more particularly to a method of manufacturing an integrated injection logic circuit element (hereinafter referred to as I 2 L).
第１図に従来のセルフアラインによるI2Lの製
造プロセスを示す。従来の方法では、半導体基板
１を選択的に２〜３μ程度酸化を行つて酸化膜
２，２′を形成し、さらに全面酸化を行い、それ
によつて形成された酸化膜３をフオトレジスト等
を用いて選択的にエツチングし、ボロン等のＰ型
不純物を拡散することによりインジエクタ領域
４′を形成する（同図ａ）。 FIG. 1 shows a conventional self-aligned I 2 L manufacturing process. In the conventional method, the semiconductor substrate 1 is selectively oxidized by about 2 to 3 μm to form oxide films 2 and 2', and then the entire surface is oxidized, and the oxide film 3 thus formed is coated with a photoresist or the like. The injector region 4' is formed by selectively etching the wafer and diffusing a P-type impurity such as boron (FIG. 4A).
次にn+形にドープされた多結晶シリコンを形
成し、さらに酸化膜および窒化膜を形成し、フオ
トエツチングにより選択的に窒化膜７を残し、こ
の窒化膜７をマスクにして窒化膜６、多結晶シリ
コン５をエツチング法を用いて形成する（同図
ｂ）。 Next, an n + type doped polycrystalline silicon is formed, and then an oxide film and a nitride film are formed, and the nitride film 7 is selectively left by photo-etching. Using this nitride film 7 as a mask, the nitride film 6, Polycrystalline silicon 5 is formed using an etching method (FIG. 2b).
次に全面酸化を行い、窒化膜７をマスクにして
酸化膜８，８′が残るように選択的にエツチング
を行う。この時、n+形多結晶シリコン５からベ
ース領域４′に不純物が拡散してn+形のコレクタ
領域９が形成される（同図ｃ）。 Next, the entire surface is oxidized, and using the nitride film 7 as a mask, selective etching is performed so that the oxide films 8 and 8' remain. At this time, impurities are diffused from the n + -type polycrystalline silicon 5 into the base region 4', forming an n + -type collector region 9 (FIG. 3(c)).
この工程において、ベース抵抗を下げ、さらに
インジエクタ４の注入効率を上げるために領域
４，４′にボロン等を拡散する方法もある。 In this step, there is also a method of diffusing boron or the like into the regions 4 and 4' in order to lower the base resistance and further increase the injection efficiency of the injector 4.
次に、窒化膜７を除去した後、Al層１０，１
０′を形成する（同図ｄ）。 Next, after removing the nitride film 7, the Al layers 10, 1
0' (d in the same figure).
以上の従来の方法では、Al層１０，１０′とn+
形コレクタ領域９の間隔Ａ，A′は、多結晶シリ
コン５の側面の酸化膜８，８′とn+形コレクタ領
域９の横拡がりで決定されるため、酸化膜８，
８′の厚さのバラツキおよびn+形コレクタ領域９
の横拡がりのバラツキにより、コレクターベース
間耐圧が非常にバラツキ、わるくすると、n+形
コレクタ領域９とAl層１０，１０′がシヨートす
ることもある。 In the above conventional method, Al layers 10, 10' and n +
The spacing A, A' between the oxide films 8, 8' on the side surfaces of the polycrystalline silicon 5 and the lateral spread of the n + type collector region 9 determines the distances A, A' between the oxide films 8,
8′ thickness variation and n + type collector region 9
Due to variations in the lateral spread of the collector base, the withstand voltage between the collector bases becomes extremely variable and deteriorates, which may cause the n + -type collector region 9 and the Al layers 10 and 10' to be shot.
本発明は以上のような従来の欠点をなくし、そ
の目的はコレクターベース間耐圧をコントロール
よく形成する製造方法を提供するものである。 The present invention eliminates the above-mentioned conventional drawbacks, and its purpose is to provide a manufacturing method that can control the breakdown voltage between collector bases.
本発明による製造方法を第２図により詳細に説
明する。第２図ａは従来による方法（第１図ａ）
とまつたく同じ方法で形成する。次に全面に厚さ
1000〜2000Åの窒化膜１１および厚さ5000Å程度
の酸化膜１２を順次形成する（同図ｂ）。この
後、コレクタを形成する領域をつくるために、フ
オトレジスト等を用いて酸化膜１２を選択的にエ
ツチングして孔１３を形成する。さらに、酸化膜
１２をマスクして窒化膜１１をエツチングする。
この時、孔１３より２〜３μ程度大きめにエツチ
ングを行い、空隙１４，１４′を形成する。この
空隙は、コレクターベース間耐圧等の条件により
適当な条件を設定する（同図ｃ）。 The manufacturing method according to the present invention will be explained in detail with reference to FIG. Figure 2 a is the conventional method (Figure 1 a)
Form in exactly the same way. Next, the thickness on the entire surface
A nitride film 11 with a thickness of 1000 to 2000 Å and an oxide film 12 with a thickness of about 5000 Å are successively formed (FIG. 2B). Thereafter, in order to create a region where a collector will be formed, the oxide film 12 is selectively etched using a photoresist or the like to form a hole 13. Furthermore, the nitride film 11 is etched while masking the oxide film 12.
At this time, etching is performed approximately 2 to 3 microns larger than the hole 13 to form voids 14 and 14'. Appropriate conditions for this gap are set depending on conditions such as the pressure resistance between the collector bases (FIG. 3(c)).
次にn+形多結晶シリコンを5000Å〜10000Å程
度の厚さに形成し、選択的にエツチングを行い、
コレクタ領域形成のためのn+形多結晶シリコン
１５を形成する。このn+形多結晶シリコン１５
はコレクタ電極ともなる（同図ｄ）。次に、酸化
膜１２を除去する（同図ｅ）。 Next, N + type polycrystalline silicon is formed to a thickness of about 5000 Å to 10000 Å, selectively etched,
N + type polycrystalline silicon 15 for forming a collector region is formed. This n + type polycrystalline silicon 15
also serves as a collector electrode (d in the same figure). Next, the oxide film 12 is removed (e in the same figure).
さらに、全面酸化を行つて5000Å程度の酸化膜
１６を形成する。この時、酸化膜１６は、多結晶
シリコン１５の上面と側面、およびベース領域
４′上の空隙１４，１４′の所のみ酸化されるた
め、この部分にのみ形成される。この時、n+形
多結晶シリコン１５からベース領域４′に不純物
が拡散され、n+形コレクタ領域９が形成される
（同図ｆ）。 Further, the entire surface is oxidized to form an oxide film 16 of about 5000 Å. At this time, the oxide film 16 is oxidized only at the upper surface and side surfaces of the polycrystalline silicon 15 and at the voids 14, 14' above the base region 4', and is therefore formed only at these portions. At this time, impurities are diffused from the n + -type polycrystalline silicon 15 into the base region 4', forming the n + -type collector region 9 (FIG. 4(f)).
次に、窒化膜１１を除去する。この時、ベース
層抵抗を下げること及びインジエクタの注入効率
を上げることを目的とし、領域４，４′にボロン
等を拡散してもよい（同図ｇ）。そして、最後に
Al層１０，１０′を形成する（同図ｈ）。 Next, nitride film 11 is removed. At this time, boron or the like may be diffused into the regions 4 and 4' for the purpose of lowering the base layer resistance and increasing the injection efficiency of the injector (see g in the figure). And finally
Al layers 10 and 10' are formed (h in the figure).
以上の本発明による方法を用いることにより、
Al層１０，１０′とn+形コレクタ領域９の間隔
Ｂ，B′は、従来の方法とは異なり自由にコントロ
ールが可能なため、コレクターベース間耐圧とし
て希望通りの値が得られる。また、製造方法は
I2Lについてのみ述べたが、通常のバイポーラト
ランジスタのエミツタ・ベース形成においても、
同様にできることはいうまでもない。 By using the above method according to the present invention,
Unlike conventional methods, the distances B and B' between the Al layers 10 and 10' and the n + type collector region 9 can be freely controlled, so that a desired value can be obtained as the collector-base breakdown voltage. Also, the manufacturing method is
Although I have only mentioned I 2 L, in the emitter-base formation of a normal bipolar transistor,
It goes without saying that you can do the same.
第１図ａ〜ｄは従来の方法による製造方法の工
程断面図、第２図ａ〜ｈは本発明の一実施例によ
る製造方法の工程断面図である。
１……半導体基板、２，２′，３，６，８，
８′，１２，１６……酸化膜、４，４′……Ｐ形拡
散領域、５，１５……n+形多結晶シリコン、
７，１１……窒化膜、９……n+形拡散層、１
０，１０′……Al配線。
1A to 1D are process cross-sectional views of a conventional manufacturing method, and FIGS. 2A to 2H are process cross-sectional views of a manufacturing method according to an embodiment of the present invention. 1...Semiconductor substrate, 2, 2', 3, 6, 8,
8', 12, 16...Oxide film, 4,4'...P type diffusion region, 5,15...n + type polycrystalline silicon,
7, 11...Nitride film, 9...n + type diffusion layer, 1
0,10'...Al wiring.
Claims (1)
成し、該第１の絶縁層上に第２の絶縁層を形成
し、該第２の絶縁層の所定部に第１の開孔を施
し、第２の絶縁層をマスクとして上記第１の開孔
よりも大きな第２の開孔を上記第１の絶縁層に形
成し、上記第１の開孔によつて露出した上記半導
体基体の部分上に不純物を有する半導体層を形成
し、上記第２の絶縁層を除去して酸化処理を行な
つて該半導体層の表面を酸化し、該第１の絶縁層
を除去し、金属を被着して前記基体上に前記半導
体層をまたいでベース電極を形成することを特徴
とする半導体装置の製造方法。1. Forming an oxidation-resistant first insulating layer on a semiconductor substrate, forming a second insulating layer on the first insulating layer, and forming a first opening in a predetermined portion of the second insulating layer. a second opening larger than the first opening is formed in the first insulating layer using the second insulating layer as a mask, and the semiconductor substrate exposed by the first opening is A semiconductor layer containing impurities is formed on the portion, the second insulating layer is removed and an oxidation treatment is performed to oxidize the surface of the semiconductor layer, the first insulating layer is removed, and the metal is A method of manufacturing a semiconductor device, comprising the step of forming a base electrode on the substrate by depositing the semiconductor layer across the semiconductor layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56196489A JPS5897858A (en) | 1981-12-07 | 1981-12-07 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56196489A JPS5897858A (en) | 1981-12-07 | 1981-12-07 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5897858A JPS5897858A (en) | 1983-06-10 |
| JPS6229912B2 true JPS6229912B2 (en) | 1987-06-29 |
Family
ID=16358624
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56196489A Granted JPS5897858A (en) | 1981-12-07 | 1981-12-07 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5897858A (en) |
-
1981
- 1981-12-07 JP JP56196489A patent/JPS5897858A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5897858A (en) | 1983-06-10 |
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