JPS62293933A - Input protection circuit - Google Patents
Input protection circuitInfo
- Publication number
- JPS62293933A JPS62293933A JP13520286A JP13520286A JPS62293933A JP S62293933 A JPS62293933 A JP S62293933A JP 13520286 A JP13520286 A JP 13520286A JP 13520286 A JP13520286 A JP 13520286A JP S62293933 A JPS62293933 A JP S62293933A
- Authority
- JP
- Japan
- Prior art keywords
- polycrystalline silicon
- protection circuit
- input protection
- wiring
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 17
- 230000005669 field effect Effects 0.000 claims description 6
- 239000010410 layer Substances 0.000 description 17
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 239000002356 single layer Substances 0.000 description 3
- 230000020169 heat generation Effects 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
３、発明の詳細な説明
〔産業上の利用分野〕
この発明は、半導体装置の入力保護回路に関し、特に電
界効果形トランジスタ回路から成るものに関するもので
ある。[Detailed Description of the Invention] 3. Detailed Description of the Invention [Field of Industrial Application] The present invention relates to an input protection circuit for a semiconductor device, and particularly to one consisting of a field effect transistor circuit.
第３図は従来の入力保護回路を示す回路図である。図に
おいて、３はサージ電圧放出用の電界効果形トランジス
タを示し、破線で囲まれた部分Ａには多結晶シリコン５
が配線として一層構造で用いられていた。FIG. 3 is a circuit diagram showing a conventional input protection circuit. In the figure, numeral 3 indicates a field-effect transistor for emitting surge voltage, and a polycrystalline silicon 5
was used as wiring in a single layer structure.
次に、動作について説明する。図における電界効果形ト
ランジスタ３は、非常に高いしきい値電位を有するため
、通常の入力信号ｆｉｎに対してはトランジスタ３はＯ
Ｎする事なく、内部回路Ｂにそのまま入力信号が伝達さ
れる。ところが、外部から非常に大きなサージ電圧が印
加された場合、トランジスタがＯＮ状態となり、電流を
基板へ流出する事によって、サージ電圧が内部まで伝達
される事を防ぐ。Next, the operation will be explained. Since the field effect transistor 3 in the figure has a very high threshold potential, the transistor 3 is 0 for the normal input signal fin.
The input signal is transmitted to internal circuit B as is without any N. However, when a very large surge voltage is applied from the outside, the transistor turns on and current flows to the substrate, thereby preventing the surge voltage from being transmitted to the inside.
従来の入力保護回路は以上のように多結晶シリコンの配
線が一層のみ使用されているため、非常に高いサージ電
圧が印加された場合、多結晶シリコン配′４ｆＡ５が溶
断するという可能性があり、それを防ぐために配線を太
くしなければならず、配線部分の占める面積が増大する
という問題点があった。As described above, conventional input protection circuits use only one layer of polycrystalline silicon wiring, so if a very high surge voltage is applied, there is a possibility that the polycrystalline silicon wiring 4fA5 will melt. In order to prevent this, the wiring must be made thicker, which poses a problem in that the area occupied by the wiring portion increases.
この発明は上記のような問題点を解消するためになされ
たもので、配線部分の占める面積を増大することなく、
配線の溶断を防ぐことのできる入力保護回路を得ること
を目的とする。This invention was made to solve the above-mentioned problems, and without increasing the area occupied by the wiring part,
The purpose of this invention is to obtain an input protection circuit that can prevent wiring from melting.
この発明に係る入力保護回路は、入力バッドと内部回路
間の配線を多結晶シリコンの二層構造にするとともに、
第一層目の多結晶シリコン配線と第二層目の多結晶シリ
コン配線の間にコンタクトを設けたものである。In the input protection circuit according to the present invention, the wiring between the input pad and the internal circuit has a two-layer structure of polycrystalline silicon, and
A contact is provided between the first layer of polycrystalline silicon wiring and the second layer of polycrystalline silicon wiring.
この発明における入力保護回路は、入力バッドと内部回
路間の多結晶シリコン配線を二層構造とし、その二層の
間にコンタクトを設けるように構成したので、一層構造
の場合より抵抗を低くする。In the input protection circuit according to the present invention, the polycrystalline silicon wiring between the input pad and the internal circuit has a two-layer structure, and a contact is provided between the two layers, so that the resistance is lower than that of a single-layer structure.
以下、この発明の一実施例を図について説明する。第１
図は本発明の一実施例による入力保護回路を示し、本実
施例では図示破線部分Ａは第２図に示すように、二層構
造の多結晶シリコン配線とし、その二層構造を形成する
第一層１と第二層２間にコンタクト４を設ける。An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure shows an input protection circuit according to an embodiment of the present invention. In this embodiment, the dashed line portion A in the figure is a polycrystalline silicon wiring with a two-layer structure, as shown in FIG. A contact 4 is provided between the first layer 1 and the second layer 2.
次に動作について説明する。第１図において電界効果形
トランジスタ３は非常に高いしきい値電位を有するので
、通常の入力信号Ｉｉｎが印加された場合、トランジス
タ３はＯＦＦの状態で、入力信号Ｉｉｎはそのまま内部
回路Ｂへ伝達される。ところが、非常に大きなサージ電
圧が印加された場合、トランジスタ３はＯＮ状態となり
サージ電流を基板に流出させることにより内部回路Ｂま
で伝達することを防ぐ。このとき従来の回路のように、
破線部分Ａが多結晶シリコン配線５の一層構造のみから
成る場合、抵抗が大きいことによる非常に大きな発熱か
ら多結晶シリコン配線５が溶断するという可能性がある
。しかし、この回路のように多結晶シリコン配線を二層
構造にし、さらにその第一層１と第二層２をコンタクト
することにより抵抗を小さくすることが可能となり、発
熱を少なくし配線の溶断を防ぐことが可能となる。Next, the operation will be explained. In FIG. 1, the field effect transistor 3 has a very high threshold potential, so when a normal input signal Iin is applied, the transistor 3 is in an OFF state and the input signal Iin is directly transmitted to the internal circuit B. be done. However, when a very large surge voltage is applied, the transistor 3 is turned on and the surge current is prevented from being transmitted to the internal circuit B by flowing out to the substrate. At this time, like the conventional circuit,
If the broken line portion A consists of only a single layer structure of the polycrystalline silicon wiring 5, there is a possibility that the polycrystalline silicon wiring 5 will melt due to the extremely large amount of heat generated due to the large resistance. However, by making the polycrystalline silicon wiring into a two-layer structure as in this circuit, and by contacting the first layer 1 and the second layer 2, it is possible to reduce the resistance, reduce heat generation, and prevent the wiring from fusing. It is possible to prevent this.
以上のように、この発明によれば、入力パッドと内部回
路間の多結晶シリコン配線を二層構造とし第一層と第二
層をコンタクトしたので、配線の占める面積を増大させ
ることなく、発熱による溶断を防ぐという効果がある。As described above, according to the present invention, the polycrystalline silicon wiring between the input pad and the internal circuit has a two-layer structure, and the first layer and the second layer are in contact, so that heat generation can be achieved without increasing the area occupied by the wiring. This has the effect of preventing fusing due to
第１図は本発明の一実施例による入力保護回路を示す回
路図、第２図はこの発明の入力保護回路の構造を示す図
、第３図は従来の入力保護回路を示す回路図である。
１・・・第一層多結晶シリコン、２・・・第二層多結晶
シリコン、３・・・電界効果形トランジスタ、４・・・
コンタクト、５・・・多結晶シリコン。FIG. 1 is a circuit diagram showing an input protection circuit according to an embodiment of the present invention, FIG. 2 is a diagram showing the structure of the input protection circuit of the present invention, and FIG. 3 is a circuit diagram showing a conventional input protection circuit. . DESCRIPTION OF SYMBOLS 1... First layer polycrystalline silicon, 2... Second layer polycrystalline silicon, 3... Field effect transistor, 4...
Contact, 5...polycrystalline silicon.
Claims (1)
の電界効果形トランジスタが設けられ、上記入力パッド
と上記内部回路との間に多結晶シリコン配線が用いられ
ている入力保護回路において、該多結晶シリコン配線を
二層構造としたことを特徴とする入力保護回路。(1) In an input protection circuit in which a field effect transistor for surge voltage release is provided between an input pad and an internal circuit, and a polycrystalline silicon wiring is used between the input pad and the internal circuit, An input protection circuit characterized in that the polycrystalline silicon wiring has a two-layer structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61135202A JP2780972B2 (en) | 1986-06-10 | 1986-06-10 | Input protection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61135202A JP2780972B2 (en) | 1986-06-10 | 1986-06-10 | Input protection circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62293933A true JPS62293933A (en) | 1987-12-21 |
| JP2780972B2 JP2780972B2 (en) | 1998-07-30 |
Family
ID=15146238
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61135202A Expired - Fee Related JP2780972B2 (en) | 1986-06-10 | 1986-06-10 | Input protection circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2780972B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011044812A (en) * | 2009-08-19 | 2011-03-03 | Toshiba Corp | High-frequency power amplifier |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58123768A (en) * | 1982-01-18 | 1983-07-23 | Toshiba Corp | Protective device for input |
| JPS58173867A (en) * | 1982-04-07 | 1983-10-12 | Toshiba Corp | Input protective circuit of mos type semiconductor device |
| JPS58219825A (en) * | 1982-06-14 | 1983-12-21 | Toshiba Corp | Protecting circuit of input |
-
1986
- 1986-06-10 JP JP61135202A patent/JP2780972B2/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58123768A (en) * | 1982-01-18 | 1983-07-23 | Toshiba Corp | Protective device for input |
| JPS58173867A (en) * | 1982-04-07 | 1983-10-12 | Toshiba Corp | Input protective circuit of mos type semiconductor device |
| JPS58219825A (en) * | 1982-06-14 | 1983-12-21 | Toshiba Corp | Protecting circuit of input |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011044812A (en) * | 2009-08-19 | 2011-03-03 | Toshiba Corp | High-frequency power amplifier |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2780972B2 (en) | 1998-07-30 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313111 |
|
| R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
| LAPS | Cancellation because of no payment of annual fees |