JPS58123768A - Protective device for input - Google Patents

Protective device for input

Info

Publication number
JPS58123768A
JPS58123768A JP57005678A JP567882A JPS58123768A JP S58123768 A JPS58123768 A JP S58123768A JP 57005678 A JP57005678 A JP 57005678A JP 567882 A JP567882 A JP 567882A JP S58123768 A JPS58123768 A JP S58123768A
Authority
JP
Japan
Prior art keywords
input
resistors
resistor
input protection
diode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57005678A
Other languages
Japanese (ja)
Inventor
Hiroshi Iwahashi
岩橋　弘
Masamichi Asano
正通 浅野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP57005678A priority Critical patent/JPS58123768A/en
Publication of JPS58123768A publication Critical patent/JPS58123768A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Protection Of Static Devices (AREA)
  • Amplifiers (AREA)

Abstract

PURPOSE:To use a plurality of input protective resistors at a number of times by connecting each one end of a plurality of the input protective resistors to the input terminals of the input protective device for a MOS type integrated circuit and connecting the other ends to grounding potential points through several diode. CONSTITUTION:The input protective resistors R1, R2, R3 are all constituted similarly, and the formula of R1>R2>R3 is set. A polysilicon layer 13 formed into an insulating layer 12 formed onto a semiconductor substrate 11 is used as a resistor. Electric wiring 14, 15 are extracted from both end sections of the polysilicon layer 13, and formed by aluminum, etc. When positive polarity surge voltage is applied to an input terminal In, maximum currents flow through the resistor R3, thus resulting in the breakdown of the diode D3. Even when the resistor R3 is fused at that time, the device can be used even by surge voltage twice in total because the two resistors R1, R2 remain. The number of resistors R can be increased.

Description

【発明の詳細な説明】 発明の技術分ｉ この発明はたとえばＭＤｓ形集積回路における入力トラ
ンジスタのｒ−）の破壊を防止する入力保護装置に関す
る。DETAILED DESCRIPTION OF THE INVENTION Technical Portion i of the Invention The present invention relates to an input protection device for preventing destruction of an input transistor (r-) in an MDs type integrated circuit, for example.

発１ｊ１１の技術的背景 一般にＭＯＪＩＦＷ’ｒの？−）は、七〇？−）耐圧以
上の電圧が印加されると破壊される。極めて注意深く作
られ九ＭＯ８ＦＸ’ｒ　ｆ）ｒ　−）絶縁膜たとえばシ
リコン酸化層（Ｓ１０□）は、１０’　Ｖ／ＩＬ程度の
電界が加えられて４破壊されない、７ｔとえば１０００
ムの？−）絶縁膜厚を持ツＭＯ８ＦｇＴは、デートに１
００Ｖ＠度の電圧が印加されても破壊されない、ところ
がこれ以上の電圧、たとえば静電気等のサージ電圧が印
加された場合に鉱、上記ｒ−）膜厚を持つＭＯ８ＦＩＣ
Ｔは破壊されてしまう、したがって、このようなサージ
電圧による破壊を防止するために、ＭＯ！ｉ形集積形路
積回路力保護装置が設けられる− 第１図は従来の入力保護装置の構成を示す回路図である
０図においてディプレッジｌンモードのＭＯａＦＥＴ’
　ＱＤト工ンハンスメントモードのＭＯＳＦＥＴ　Ｑｌ
とはＭｏＢ形集積回路の入力段のインバータを構成し、
このうちＭＯ８ＦＩＣＴ　Ｑ、の？−）には入力端子Ｉ
、の信号が与えられるようになっている。上記入力端子
１つには入力保護装置を構成する抵抗凡の一端が接続さ
れ、仁の抵抗Ｒの他端拡開じく入力保護装置を構成する
ダイオードＤのカソードと上記１＆）ＩＩＦ酊ｑ、の？
−）に接続される。上記ダイオードＤ、のアノードは接
地電位点（基準電位点）Ｋｌｌ続□される。すなわち、
第１図の回路では入力端子Ｉｌｌと入力段のＭＯ８ＦＫ
ＴＱヨのゲートとの間に、各１個の抵抗Ｒと！イオード
Ｄとからなる入力保護装置が挿入されている・ 上記従来装置において、入力端子！。にサージ電圧が印
加されると、ダイオードＤがブレークダウンを起むして
ＭＯ８ＦＥ’ｒ　Ｑｌｔ）　ｒ−）にはこのブレークダ
ウン電圧以上の電圧線印加されない。Technical background of 1j11 MOJIFW'r in general? -) Is it seventy? -) Destroyed when a voltage higher than the withstand voltage is applied. A very carefully made 9MO8FX'r f)r -) insulating film, such as a silicon oxide layer (S10□), will not be destroyed when an electric field of about 10' V/IL is applied, 7t, for example 1000
Mu's? -) MO8FgT with an insulating film thickness is 1 on the date.
MO8FIC with the above r-) film thickness will not be destroyed even if a voltage of 00V@ degree is applied, but if a voltage higher than this, for example a surge voltage such as static electricity, is applied, it will not be destroyed.
T will be destroyed, therefore, to prevent destruction due to such surge voltage, MO! An i-type integrated circuit power protection device is provided. FIG. 1 is a circuit diagram showing the configuration of a conventional input protection device.
MOSFET Ql in QD enhancement mode
constitutes an inverter at the input stage of a MoB type integrated circuit,
Of these, MO8FICT Q. -) is the input terminal I.
, the signal is given. One end of the resistor R constituting the input protection device is connected to one of the input terminals, and the other end of the resistor R is connected to the cathode of the diode D constituting the input protection device and the of?
-) is connected to The anode of the diode D is connected to the ground potential point (reference potential point) Kll. That is,
In the circuit shown in Figure 1, input terminal Ill and input stage MO8FK
One resistor R is connected between the gate of TQ and ! In the conventional device described above, an input protection device consisting of an diodes D is inserted. . When a surge voltage is applied to the diode D, a breakdown occurs, and a voltage line higher than this breakdown voltage is not applied to the MO8FE'rQlt)r-).

したがって、ＭＯ８Ｆ］ｉ：Ｔ　Ｑｌは破壊から保護さ
れる。Therefore, MO8F]i:T Ql is protected from destruction.

まえ、上記抵抗Ｒは、ブレークダウン時、ダイオードＤ
Ｋ流れる電流を制限する機能を有し、過電流によりダイ
オードＤが破壊されることを防止するとともに、サージ
電圧印加時にダイオードＤのカソードに加えられる電圧
の立ち上りをゆるやかにする機能も有し、この機能によ
ってダイオードＤのブレークダウンのスイッチングがＭ
Ｏ８ＦＩＴ　Ｑ、０ｆ−）に高電圧が印加される前に起
こるようＫしている。Before, the above-mentioned resistor R is a diode D at the time of breakdown.
It has the function of limiting the current flowing through K, preventing diode D from being destroyed by overcurrent, and also has the function of slowing the rise of the voltage applied to the cathode of diode D when a surge voltage is applied. Depending on the function, the breakdown switching of diode D is
K occurs before a high voltage is applied to O8FIT Q, 0f-).

背景技術の問題点 ：） ところが、上記従来の装置にあっては、入力端子１つに
印加されるサージ電圧によシ、ＭＯ８ＦＥＴＱ、のｒ−
）が破壊される前に抵抗Ｒが溶断（〜てしまう不良が多
く発生し北、すなわち、ダイオードＤがブレークダウン
を起ζすことによシＭＯ８ＦＥＴ　Ｑ、０ｒ−）には破
壊に至る電圧は印加されない、しかしながら入力端子Ｉ
、には高電圧が印加されるため、Ｉリシリコン等によっ
て形成される抵抗ＲＫ流れる電流の電流密度が大きくな
シ、このとき発生するジュール熱によって抵抗Ｒが溶断
してしまう、この場合、その後入力端子！、に印加され
る電圧はＭＯ８ＰＩＣ’ｒ　ＱＩＫは伝えられず、この
集積回路祉二度と使用できなくなる。Problems with the Background Art:) However, in the conventional device described above, the r-
) is destroyed before the resistor R is blown out (~). In other words, when the diode D causes a breakdown, the voltage that leads to the breakdown of the MO8FET Q, 0r-) is Not applied, however, input terminal I
Since a high voltage is applied to , the current density of the current flowing through the resistor RK made of silicon or the like is high, and the Joule heat generated at this time causes the resistor R to melt. Terminal! , the voltage applied to the MO8PIC'r QIK will not be transmitted and this integrated circuit will no longer be usable.

このように従来の入力保護装置は、抵抗８が破壊される
と二度と使用出来なくなるという不都合がある。As described above, the conventional input protection device has the disadvantage that once the resistor 8 is destroyed, it cannot be used again.

発明の目的 したがって、この発明の目的は入力保膜用の抵抗がサー
ジ電圧によって何回か破壊されても再び使用することが
可能な入力保護装置を提供することにある。OBJECTS OF THE INVENTION Accordingly, an object of the present invention is to provide an input protection device that can be used again even if the input film protection resistor is destroyed several times by surge voltage.

発明の概要 この発明による入力保護装置ａ、入力端子に複数の入力
保護装置の各一端を共通接続し、さらにこれらの入力保
護装置の他端を個々のダイオードを介しであるいは１個
のダイオードを共通に介して接地電位点に結合するよう
にしたものである。Summary of the Invention An input protection device a according to the present invention has one end of each of a plurality of input protection devices commonly connected to an input terminal, and the other ends of these input protection devices are connected through individual diodes or one diode in common. It is designed to be coupled to the ground potential point via.

発明の実施例 以下図面を参照してこの発明の一実施例を収明する。第
２図はこの発明に係る入力保護装置の一実施例の構成を
示す回路図である≧この実施例の入力保護装置では入力
端子Ｉ、に複数のたとえば３個の入力保膜用の抵抗Ｒ１
ｅ　Ｒ１ｍ　Ｒ１の各一端を共通接続し、さらにこれら
各抵抗Ｒ１ｍ　Ｒ１Ｂ　ｍｓの他端を３個の入力保農用
の各ダイオードＤｌ　ｅ　ＤＩ　ａ　Ｄｍのカソードに
それぞれ接続するようにした４のである。そして上記３
個のダイオードＤＩ　ｓ　Ｄ曹＃　ＤＩのアノードはす
べて接地電位点（基準電位点）に接続されてｂる。した
がって各抵抗Ｒ１ｅ　Ｒ１ｓ　Ｒ１の他端は個々のダイ
オードＤＩ　Ｉ　ｎ、　ｅ　ＤＩ　ｋ介して基準電位点
に導びかれている。また、上記抵抗Ｒ１ａ　Ｒ１ｅ　Ｒ
ｍはＲ１よＪ）　Ｒｓ　、ｍ　ｓよりはＲｓというよう
に順次溶断され易いように構成されていて、たとえばＲ
１＞Ｒｍ　＞Ｒ２Ｏ様に各抵抗値が異なるように設定さ
れている。Embodiment of the Invention An embodiment of the invention will be described below with reference to the drawings. FIG. 2 is a circuit diagram showing the configuration of an embodiment of the input protection device according to the present invention. In the input protection device of this embodiment, a plurality of, for example, three input film protection resistors R1 are connected to the input terminal I.
One end of each of the resistors R1m, R1B, and R1 is connected in common, and the other end of each of the resistors R1m, R1B, and ms is connected to the cathodes of three input protection diodes Dl, DI, and Dm, respectively. And above 3
The anodes of all the diodes DI are connected to the ground potential point (reference potential point). The other end of each resistor R1e, R1s, R1 is therefore led to a reference potential point via an individual diode DIIn, eDIk. In addition, the above resistor R1a R1e R
m is R1, J) Rs, and m is constructed so that it is easy to melt down sequentially, such as Rs rather than s. For example, R
Each resistance value is set to be different such that 1>Rm>R2O.

そして上記最も抵抗値が高く設定されている抵抗Ｒ１の
他端に、前記ＭＯａ形集積回路の入力段のインバータを
構成するＭＱＢｔＭＴ　Ｑ、のｒ−）が接続されている
。The other end of the resistor R1 having the highest resistance value is connected to the MQBtMT Q, r-, which constitutes the input stage inverter of the MOa type integrated circuit.

第３図は上記各抵抗Ｒ１＃　Ｒ１ｅ　ｉｓの構成を示す
断藺図である。これらの抵抗Ｒ＊　＊　Ｒ１ａｌｌはす
べて同様の構成になっていて、半導体基体ｌｌ上に設け
られた絶縁層ｌｚ内に設けられた／　１７シリコン層１
３を抵抗として用いている。なお第３図において、１４
．ＩＳは上記Ｉリシリコン層ＩＪの両端部から取シ出さ
れる電極配線であシ、たとえばアル１＝ウム等で形成さ
れている。FIG. 3 is a schematic diagram showing the structure of each of the resistors R1#R1e is. These resistors R* * R1all all have the same structure, and are provided within the insulating layer lz provided on the semiconductor substrate ll./17 Silicon layer 1
3 is used as a resistor. In addition, in Figure 3, 14
．． IS is an electrode wiring taken out from both ends of the silicon layer IJ, and is made of, for example, aluminum or the like.

このような構成でなる入力保護装置において、いま入力
端子！、に正極性のサージ電圧、すなわち各ダイオード
ＤＩ　ｅ　ＤＩ　＊　ＤＩ　Ｋ対して逆バイアス状態と
なるような電圧が印加されると、最も抵抗値が低く設定
されている抵抗Ｒｓを介して最も大きな電流が流れ、こ
れによりてダイオードＤ、がブレークダウンを起こす、
このときに上記抵抗ａＳがたとえ溶断したとしてもあと
２個の抵抗’ＬｌｓＲ１が残っているので、この後、こ
の入力保護装置は抵抗Ｒｓ、Ｒ１が溶断するような電流
が流れるサージ電圧が合計２回印加される書で祉使用す
ることができる。また抵抗翼の数を増加する程上記回数
は増加する。In an input protection device with such a configuration, now is the input terminal! , when a positive surge voltage, that is, a voltage that puts each diode DI e DI * DI K in a reverse bias state, is applied, the largest current flows through the resistor Rs whose resistance value is set to the lowest. flows, which causes diode D to break down.
At this time, even if the resistor aS blows out, there are still two resistors 'LlsR1 left, so after this, this input protection device will receive a total of 2 surge voltages through which a current flows that will blow out the resistors Rs and R1. It can be used in a book that is applied once. Further, as the number of resistance blades increases, the above number of times increases.

第４図はこの発明の他の実施例の回路図である。この実
施例では前記３個の抵抗Ｒ１＊　Ｒ１ａＲｍの他端を個
々のダイオードを介して基準電位点に導び〈代シに、抵
抗Ｒ１、Ｒｇ　、　Ｒｓ　Ｏ他端をｌｌｌ０／イオード
Ｄ・のカンードに共通接続し、さらに仁のダイオードＤ
・のアノード；′１ を接地電位点（基準電□位点）に接続して、抵抗Ｒ１ｍ
　Ｉｌｌ　ｅ　Ｒ１の他端を共通のダイオードＤ・を介
して基準電位点に導びくようにしたものである。そして
上記抵抗ｊｌｌ　ｅ　１ｍ　ｅ　Ｒ１は上記実施例と同
様に各抵抗値がＲ１＞ａｍ　＞Ｒｓを満足するように設
定され％Ｒ１よｆｉａ＝、ｇ＝よシはＲ，というように
順次溶断され易いように構成されている。FIG. 4 is a circuit diagram of another embodiment of the invention. In this embodiment, the other ends of the three resistors R1*R1aRm are led to the reference potential point via individual diodes. , and further connect the diode D
・Connect the anode;'1 to the ground potential point (reference potential point), and connect the resistor R1m.
The other end of Ille R1 is led to a reference potential point via a common diode D. The above resistors R1 are set so that each resistance value satisfies R1>am>Rs as in the above embodiment, and are sequentially fused so that %R1 is fia=, g=yoshi is R, and so on. It is configured to be easy.

この実権側装置においても、入力端子１．　　Ｋ正極性
のす−ゾ電圧、すなわちＩイオードＤ・に対して逆バイ
アス状態となるような電圧が印加されると、最も抵抗値
が低く設定されている抵抗Ｒｓを介して最も大きな電流
が流れ、これによってダイオードＤ・がブレークダウン
を起こす、したがって上記す−ジ電圧による破壊に対し
てＭＯ８ＦＩＣＴ　Ｑ、は保護される。このときに上記
抵抗ｍｓがたとえ溶断したとしてもめと２個の抵抗１１
＊Ｒ１が残っているので、上記実施例と同様にこの入力
保護装置は抵抗］！１１ｓＲ１が溶断するような電流が
流れるサージ電圧が合計２回印加されるまで杜使用する
ことができる。In this device on the real power side, input terminal 1. When a positive polarity K voltage, that is, a voltage that causes a reverse bias state to the I ion D, is applied, the largest current flows through the resistor Rs, which has the lowest resistance value. , which causes diode D to break down, thus protecting MO8FICT Q from being destroyed by the above-mentioned voltage. At this time, even if the resistance ms is fused, the two resistors 11
*Since R1 remains, this input protection device is a resistor as in the above embodiment]! It can be used until a surge voltage that causes a current to flow that causes 11sR1 to melt is applied twice in total.

さらに上記実施例と同様に、抵抗！の数を増加する程上
記回数は増加する。Furthermore, as in the above embodiment, resistance! The above number increases as the number increases.

普通、集積回路に紘上記のように入力保膜用の抵抗翼が
溶断する糧のサージ電圧が印加されることははとんどな
い、しかし、従来の装置では仁のようなサージ電圧が一
度印加されるだけで二縦と使用することができなくなっ
てしまうが、上記各実施例の装置では抵抗Ｒが溶断する
程のサージ電圧が複数回印加されても再び使用すること
ができ、はとんど半永久的に使用することができる。ま
た、従来のように１個の人力保薩用Ｏ抵抗を用いた時と
くらべて、溶断し易い抵抗がよ）早く溶断するため、従
来装置の抵抗と上記実施例装置における最も溶断し難い
抵抗との溶断のし易さが同程度であれば、上記各実施例
装置の方が同じサージ電圧に対して従来よりも強固とな
る。Normally, it is rare for integrated circuits to receive a surge voltage that would cause the input membrane resistance blades to melt as described above. However, in the devices of each of the above embodiments, even if a surge voltage that melts the resistor R is applied multiple times, it can be used again. It can be used semi-permanently. In addition, compared to the conventional case where one O-resistance for manual maintenance is used, the resistance that is easy to blow out is faster), so the resistance of the conventional device and the resistance that is the hardest to blow out in the above example device are the same. If the ease of fusing is the same, the devices of the above embodiments will be stronger than the conventional devices against the same surge voltage.

なお、この発明は上記の実施例に限定されるものではな
く、たとえば上記実施例でれ各抵抗Ｒ１、Ｒ寥、　Ｉｓ
　Ｋｓｉ−ける溶断され易さを異ならせるために抵抗値
を互いに異なるように設定する場合について説明し走が
、これは［５図（ａ）ないしく・）に示すように、前記
ｆリシリコンにょって形成される各抵抗Ｒ１，Ｒｓ、Ｒ
ａｏＡターン形状における幅ｗｌ　、ｗｌ　、Ｗｓを異
ならせることによって、溶断され易さの程度を変えるこ
とができる。なお、第５図（荀ないしく＠）に示す抵抗
Ｒ１ａ　Ｒ１ｅ　Ｒ１を同一抵抗値に設定するとすれば
、その長さＬＳ　ｅ　Ｌｍ　ｅ　Ｉｌｌの間にはＬｌ＞
Ｌｍ＞Ｌｓなる関係が成立する。Note that the present invention is not limited to the above-mentioned embodiments; for example, in the above-mentioned embodiments, each of the resistors R1, Rx, Is
We will explain the case where the resistance values are set to be different from each other in order to vary the ease with which Ksi is blown out. Each resistor R1, Rs, R
By varying the widths wl, wl, and Ws of the aoA turn shape, the degree of susceptibility to melting can be changed. Note that if the resistors R1a, R1e, and R1 shown in FIG.
The relationship Lm>Ls holds true.

発明の効果 このようにこの発明によれば、入力像映用の抵抗がサー
ジ電圧によって何回か破壊されても再び使用することが
可能な入力保−装置を提供することができる。Effects of the Invention As described above, according to the present invention, it is possible to provide an input protection device that can be used again even if the input image resistor is destroyed several times by surge voltage.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来の入力像映装置の構成を示す回路図、第２
図はこの発明の一実施例の構成を示す回路図、第３図は
その一部分の構成を示す断面図、鯖４図はこの発明の仲
？実施例の回路図、第５図（ａ）ないしく、）はこの発
明の変形例のΔターン図である。 ＱＩ）＝ｆ”イア’Ｌ／１Ｆ　／ｗ　ン％−）”のＭＯ
８ＦＩ’ｒ、　Ｑ。 ・・・エンハンスメントモー）’　（Ｄ　ＭＯａＦＷＴ
％　１１・・・入力端子、”１　ｍ　Ｒ曹ｅ　Ｒ１・・
・入力像映用の抵抗、Ｄ　１　ｅ　ＤＩ　ｇ　ＤＩ　ｓ
　Ｄ・・・・入力保膜用のダイオード、１１・・・半導
体基体、１１・・・絶縁層、１３・・・Ｉリシリコン層
、１４，１１１・・・電極配線・出願人代理人　　弁理
士　鈴　江　武　彦□、、。 Ｒ１１園 Ｒ３１１ 第５図 （暑）　　（ｂ）　（ｃ）Figure 1 is a circuit diagram showing the configuration of a conventional input video device;
The figure is a circuit diagram showing the configuration of an embodiment of this invention, FIG. The circuit diagram of the embodiment, FIGS. 5(a) to 5), is a Δ turn diagram of a modification of the present invention. QI) = f"I'L/1F/w %-)" MO
8FI'r, Q. ...Enhancement Mo)' (D MOaFWT
% 11...Input terminal, 1 m R1...
・Resistance for input image, D 1 e DI g DI s
D...Diode for input film retention, 11...Semiconductor substrate, 11...Insulating layer, 13...I silicon layer, 14,111...Electrode wiring/Applicant's agent Patent attorney Suzu Takehiko E□,,. R11 Garden R311 Figure 5 (hot) (b) (c)

Claims (1)

【特許請求の範囲】 （１）入力端子と、この入力端子に各一端が共通嫉続さ
れる複数の入力保護抵抗と、上記入力端子に与えられる
信号に対して逆・寸イアス状゛態となるようなＰＮ接合
手段を介して上記各入力保護抵抗め他端を基準電位点に
導びく第１手段とを具備したことを特徴とする入力保護
装置。 （２前記第１手段は複数のＰＮ接合手段を有し前記複数
の各入力保護装置の他端紘個々のＰＮ接合手段を介して
前記基準電位点に導びかれている特許請求の範囲第１項
に記載の人力保護装置。 （３前記第１手段は１個のＰＮ接合手段を有し、前記複
数の入力゛像映抵抗の他端はこのＰＮ接合手段を共通に
介して前記基準電位点に導びかれている特許請求の範囲
第１項に記載の入力保１装蓋。 （４）　　前記複数の入力保−抵抗状抵抗値が互いに異
なるように設定されている特許請求の範囲第１項に記載
の人力保護装置。 （荀　前記複数の入力保護抵抗はぼりシリコンｉによっ
て形成されかつその・リーン形状の大きさが互ｈＫ異な
るように形成されている特許請求の範ｌ！第１項に記載
の入力保護装置。[Claims] (1) An input terminal, a plurality of input protection resistors each having one end commonly connected to the input terminal, and an inverse/biased state with respect to a signal applied to the input terminal. and a first means for guiding the other end of each of the input protection resistors to a reference potential point via a PN junction means as follows. (2) The first means has a plurality of PN junction means, and the other end of each of the plurality of input protection devices is led to the reference potential point via the individual PN junction means. (3) The first means has one PN junction means, and the other ends of the plurality of input video resistors are connected to the reference potential point through the PN junction means in common. (4) The input protection cover according to claim 1, which is guided by the following: (4) Claim 1, wherein the plurality of input protection resistance values are set to be different from each other. (1) The plurality of input protection resistors are formed of protruding silicon, and the sizes of the lean shapes thereof are different from each other by hK!Claim 1. Input protection device as described in .
JP57005678A 1982-01-18 1982-01-18 Protective device for input Pending JPS58123768A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57005678A JPS58123768A (en) 1982-01-18 1982-01-18 Protective device for input

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57005678A JPS58123768A (en) 1982-01-18 1982-01-18 Protective device for input

Publications (1)

Publication Number Publication Date
JPS58123768A true JPS58123768A (en) 1983-07-23

Family

ID=11617748

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57005678A Pending JPS58123768A (en) 1982-01-18 1982-01-18 Protective device for input

Country Status (1)

Country Link
JP (1) JPS58123768A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4710791A (en) * 1984-08-09 1987-12-01 Fujitsu Limited Protection device in an integrated circuit
JPS62293933A (en) * 1986-06-10 1987-12-21 三菱電機株式会社 Input protection circuit
US4763184A (en) * 1985-04-30 1988-08-09 Waferscale Integration, Inc. Input circuit for protecting against damage caused by electrostatic discharge
US4922316A (en) * 1985-05-17 1990-05-01 Nec Corporation Infant protection device
US5019883A (en) * 1987-01-28 1991-05-28 Mitsubishi Denki Kabushiki Kaisha Input protective apparatus of semiconductor device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4710791A (en) * 1984-08-09 1987-12-01 Fujitsu Limited Protection device in an integrated circuit
US4763184A (en) * 1985-04-30 1988-08-09 Waferscale Integration, Inc. Input circuit for protecting against damage caused by electrostatic discharge
US4922316A (en) * 1985-05-17 1990-05-01 Nec Corporation Infant protection device
JPS62293933A (en) * 1986-06-10 1987-12-21 三菱電機株式会社 Input protection circuit
US5019883A (en) * 1987-01-28 1991-05-28 Mitsubishi Denki Kabushiki Kaisha Input protective apparatus of semiconductor device

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