JPS6229178A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To improve the reverse current characteristics by removing the oxide film used for the first implantation diffusion when forming the N<+> region of a hyper abrupt junction variable capacitance diode, and thereafter newly forming an oxide film for the second implantation diffusion, thereby eliminating the damage of the vicinity of the N<+> region's surface due to the implantations. CONSTITUTION:In the opening of the field oxide film 103 on an N-type epitaxial layer 102 formed on an N-type silicon substrate 101, a first thin oxide film 11 is formed by thermal oxidation. Then, the first implantation diffusion is applied through the oxide film 11 to form a first N<+> region 12 in part of the N-type epitaxial layer 102. Next, the oxide film is removed by, e.g., hydrofluoric acid. Then, a thin oxide film 21 for the second implantation is formed by thermal oxidation. Subsequently, the second implantation diffusion is applied through the oxide film 21 to form a second N<+> layer 22 in part of the N-type epitaxial layer 102. Then, etching is applied via photoetching to the reserved area for forming a P<+> region to make an opening therein, a BSG film 106 is coated, and boron is diffused to form a P<+> region 107, completing a diode chip.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and is particularly used for a hyperstep junction variable capacitance diode (hereinafter referred to as a varicap diode).

[Technical background of the invention]

Varicap diodes used in television tuners and the like are desired to have a linear capacitance-voltage curve (CV curve) and high ratio characteristics, and double diffusion using implantation is applied to form the N+ region.

The formation of an N+ region in a conventional varicap diode will be explained with reference to FIG. First, an N-type epitaxial layer 102 of approximately N5=4×10" is formed on one main surface of a highly doped N-type silicon substrate ioi, and this is subjected to thermal oxidation to form a field oxide film 103. An opening is made in the area where the N+ region is to be formed by photolithography,
A thin oxide film (approximately 1,000 layers thick) is formed here using a thermal oxidation method.
104 is formed. Next.

A first ion implant (hereinafter referred to as implant) is performed through the oxide film 104 and then heated to diffuse a first N+ region 105 into a part of the N type epitaxial layer 102 (FIG. a).

Next, a second implantation and diffusion are performed to form the first N+ region 1.
A second N+ region 115 is formed in a part of 05 (FIG. b).

Next, the oxide film in the area where the P+ region is to be formed is etched by photolithography to open a hole, and a BSG film (Boron 5
A diode chip is completed by depositing glass 106 and diffusing boron to form a pin region 107.

[Problems with background technology]

According to the above conventional method, one
Since implantation is performed twice at an accelerating voltage of 00 KeV or more, damage from the implantation remains near the surface of the N+ region, resulting in IR (reverse current), which is an important characteristic of electrical properties.
There was a serious problem in that the characteristics deteriorated.

[Purpose of the invention]

In view of the above-mentioned problems in the background art, the present invention provides a manufacturing method for forming an N+ region of a super-step junction variable capacitance diode.

[Summary of the invention]

In the method for manufacturing a semiconductor device according to the present invention, in forming the N+ region of a super-step junction variable capacitance diode, after removing the oxide film used for the first implant diffusion, a new oxide film for the second implant diffusion is formed. It is characterized by the formation of

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to FIG. In addition, in the description, parts that are the same as in the prior art are indicated by the same reference numerals as in the prior art in the drawings, and the description thereof will be omitted.

First, a first thin oxide film (approximately 1,000 layers thick) is formed by thermal oxidation into the opening of the field oxide film 103 on the N-type epitaxial layer 102 formed on the N-type silicon substrate 101.
11 is formed. Next, a first implant diffusion is performed through the first thin oxide film 11 to form an N-type epitaxial layer 1.
A first N'' region 12 is formed in a part of 02 (Figure a).

Next, the first thin oxide film 11 is removed using, for example, hydrofluoric acid (FIG. b).

Next, after removing the oxide film 11 by a thermal oxidation method, a thin oxide film (film thickness of approximately 1000 mm) 21 for the second implant is removed.
form. Next, a second implant diffusion is performed through the thin oxide film 21 to form a second N+ region 22 in a part of the N type epitaxial layer 102 (FIG. C).

Next, the oxide film in the area where the P+ region is to be formed is etched by photolithography to open a hole, a BSG film 106 is deposited, and boron is diffused to form the P'' region 107, completing the diode chip (Fig. d).

〔Effect of the invention〕

According to this invention, damage accumulated on the first thin oxide film by implantation is completely removed. In addition, the silicon portions that have crystal defects, etc. that occur on the silicon surface near this area are oxidized by the formation of a second thin oxide film.
The damage is replaced by a thin oxide film and disappears. As a result I
The R level was significantly improved. This is shown in Figure 3.
In terms of distribution, this invention (A) is smaller than the conventional (B).

The average value (x) of this invention is 2nA, and the conventional x
It can be confirmed that (B) is sufficiently small at 7nA, and this quality improvement and manufacturing yield (good product rate) are also 10 to 2.
I saw an improvement of 0%.

[Brief explanation of drawings]

FIGS. 1a to 1d are cross-sectional views showing essential parts of a method for manufacturing a diode chip according to an embodiment of the present invention in the order of steps;
2A to 2C are cross-sectional views showing the main parts of the conventional manufacturing method in the order of steps, and FIG. 3 is a diagram showing the IR distribution for explaining the present invention in detail. 11 First thin oxide film 21 Second thin oxide film 12 First N+ region 22 Second N+ region 101 N-type silicon substrate 102 N-type epitaxial layer

Claims (1)

[Claims] In forming the N^+ region of the super-step junction variable capacitance diode, after removing the oxide film used for the first ion implantation diffusion, a new oxide film for the second ion implantation diffusion is formed. A method for manufacturing a semiconductor device.