JPS59165456A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To accelerate the velocity and to enhance the accuracy of a semiconductor device by forming regions to become active base and emitter by implanting impurity ions from the same window, and connecting a region to become an inactive region and the region to become the active region by diffusing an impurity. CONSTITUTION:An SiO2 insulating film 102 and a hole 103 are formed on an n type Si substrate 101, and an Si3N4 film 104 is accumulated. After the film 104 is etched with a resist 106 as a mask, B ions are implanted, thereby forming an inactive base 107. At this time, a defective layer becomes as designated by a broken line 108. Then, the resist 106 is removed, with the film 104 as a mask, a thermally oxidized film 111 is formed, B ions are implanted, and a heat treatment is executed, thereby forming an active base region 112 and an emitter region 113. The defective layer becomes as designated by a broken line 114, and becomes a structure isolated from the layer 108. Subsequently, the film 104 is removed, a contacting window is opened on the region 107, and an emitter electrode 115 and a base electrode 116 are then formed.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor device, and particularly to a method for manufacturing a semiconductor device with high density, high speed, and high precision.

Conventional configurations and their problems In recent years, semiconductor devices have become increasingly faster and more dense, and self-alignment has been introduced.- hFE (current increase rate)
There is a growing need for transistors with less variation in In order to meet this requirement, there is a method in which the emitter section is made into a cellulose diamide using an oxidation-resistant film, and the emitter, emitter, and base are formed by ion implantation. Figure 1 shows a cross-sectional view of each step of this method. show. Approximately 4,000 5102 films 2 are formed on the main surface of a CN type Si substrate 1, which will be explained below with reference to FIG. 1, by, for example, an oxidation method, and an opening is provided in a portion that will become a base region (FIG. 1A).

Next, 20008 layers of polysilicon 3 are deposited and 13
Acceleration energy of 0KnV + 7×1015ions/7
Under the conditions for ion-implanting As, As is ion-implanted into the polysilicon 3 (FIG. 1B).

After this, about 600 Si3N4 films 4 are deposited (FIG. 1C).

Then, a resist 6 is formed on the emitter formation portion, and the 5i3N4° polysilicon 3 is removed using the resist 5 as a mask, and the surface of the substrate 1 is etched by about 0.2 μm using the resist 5 and the oxide film 2 as a mask. At this time, since the polysilicon 3 containing As has a high etching speed, the polysilicon under the Si3N4 film 4 is obliquely etched (D4 in FIG. 1) Next, the resist 5 is removed and the Si
Oxidation is performed using the 2N4 film 4 as a mask, and the oxide film 6 is approximately 15
Form 008. At this time, no oxide film is formed on the boundary between the Si3N4 film 4 and the polysilicon 3. This mausoleum has an acceleration energy of 60 KeV, an acceleration energy of 1.2×101
Boron ions were implanted at a rate of 5i0ns/7, and heat treatment was performed at 90°C.
The active base 7 and the graft base 8 are formed by carrying out the process for about 0'C3o minutes. Due to this heat treatment.

As in the polysilicon 3 is diffused, an n-type emitter region 9 is also formed in the substrate 1 (FIG. 1E).

At this time, defects induced by the boron ion implantation occur in the region of the substrate 1 and polysilicon 3 shown by the broken line 1o. Thereafter, the Si3N4 film 4 is removed and a hole is opened in a part of the graft base 8, and the emitter electrode 11. A base electrode 12 is formed (FIG. 1F).

The transistor fabricated in this way has the following advantages.

(1) High density emitter and emitter contact with self-line.

(2nd high frequency... There is no pnn branch on the side of the emitter, and the curved surface mounting effect (if the base and emitter are in curved surface contact, the effect that the base travel time becomes longer) is no longer possible.

(3) Base resistance is small because the active base is connected to the highest concentration of the graft base.

However, in the above example, the polysilicon 3 contains As impurities, and when the polysilicon 3 and the substrate 1 are etched, the lower part of the Si3N4 film 4 becomes oblique as shown in the first diagram. Therefore, if boron ions are implanted after the oxide film 6 is formed, defects due to the ion implantation will occur as shown in the broken line 1o.
As shown in Figure 2, a leakage current occurs between the emitters because the defect crosses the emitter-base junction. Due to this leakage current, hFE varies and a highly accurate transistor cannot be obtained.

Purpose of the Invention In view of these conventional problems, the present invention not only improves speed, but also
An object of the present invention is to provide a method for manufacturing a semiconductor device suitable for high precision.

Structure of the Invention The present invention involves forming a region that will become an emitter and a region that will become an emitter contact by selective oxidation, for example, and forming a region that will become an active base and an emitter by ion implantation, as well as forming a region that will become a highly concentrated inactive base by ion implantation. same area
By forming the impurity ion implantation through the window and connecting the region that will become the inactive base and the region that will become the active base by diffusion of impurities, it is possible to manufacture high-precision devices with low current and little variation in hFE. be.

DESCRIPTION OF EMBODIMENTS FIG. 2 shows cross-sectional views of each process in the first embodiment of the present invention. This will be explained below with reference to FIG. n-type silicon substrate 1
8102 insulation film 1 is formed on the main surface of 01 by, for example, an oxidation method.
Approximately 4,000 holes 103 are formed in the base area.
(Figure 2A).

Next, S z s N4 film (nitride film) 1o4 about 1500
People accumulate (Figure 2B).

After that, a resist 106 is formed in the opening 103 to serve as a mask film, and the resist 106 is used as a mask to form a mask 513.
The N4 film 104 is etched. At this time, resist 106
Side etching is performed on the S 13N 4 film 104 so that a canopy is formed.

Further, using the resist) 106 and Si○2 insulating film 102 as a mask, apply boron at 80KeV at 1×101510nS/cd.
An inert base 107 is formed by ion implantation.

At this time, the defect layer excited by ion implantation is indicated by the broken line 108.
(Figure 2C). Next, the resist 106 is removed, and the thermal oxide film 111 is formed using the Si3N3 film 104 as a mask.
(Fig. 2D).

Next, using the oxide film 111 and the Si○2 insulating film 102 as a mask, B ions are irradiated 3×101 at an accelerating voltage of 40 KeV.
4 ions Anj and 7×10 15 ions Ai of As ions are implanted at an acceleration voltage of 180 Kev. Thereafter, heat treatment is performed for about 60 minutes in an N2 atmosphere at a temperature of about 1000'C, whereby the implanted ions B and 88 are diffused to form an active base region 112 and an emitter region 113.

At this time, the defect layer induced by ion implantation is indicated by the broken line 114.
As shown in FIG. 2, the structure is separated from the defect layer 108 (FIG. 2E).

Next, the S 13N 4 film 104 above the emitter region 113
After removing and forming a contact window on the inactive base region 107, an emitter electrode 115° and a base electrode 116 are formed (FIG. 2F).

In the method shown in FIG. 2, the active base 112 and the inactive base 1 are simultaneously
07 are brought into contact and electrically connected, and defects 108 and 114 due to ion implantation are caused by emitter 113 and base 1.
12 pnn junctions are not crossed. Further, it is desirable that the p-type diffusion region 110 for connection be formed to be equal to or shallower than the active base 112. By doing this, the dependence of E on h on the emitter area is reduced.

Next, FIG. 3 shows sectional views of each process in the second embodiment of the present invention. This will be explained below with reference to FIG.

Approximately 4,000 Si2 insulating films 102 are formed on the main surface of an n-type silicon substrate 101 by, for example, an oxidation method, and openings 1o3 are provided in the base region (FIG. 3A).

Next, approximately 150 layers of Si3N4 film 104 is deposited (third layer).
Figure B). Thereafter, a resist IC) 6 is formed in the opening IQ3, and using this resist 1o6 as a mask, the Si3N4 film 1
Etching 04. At this time, side etching is performed so that an eave is formed on the resist 106. Further, using the resist 106 and the 3102 insulating film 102 as a mask, boron ions are implanted at 80 KeV to about I x 10 1 ons//Ci to form an inert base (graft base) 107. At this time, the defect layer u excited by ion implantation
10 seconds (Figure 3C).

Next, the resist 106 is removed, and the oxide film 10 containing boron is removed.
A p-type impurity region 110 is formed using 9 as a diffusion source (FIG. 3D). The oxide film 109 containing boron is removed, and a thermal oxide film 111 is formed using the SlaN4 film 104 as a mask.

Next, using the oxide film 111 and the 5102 insulating film 102 as masks, B ions were added at an acceleration voltage of 40 KeV at 3×10 t.
OnsA4 + As ions are implanted at an acceleration voltage of 180 KeV at a rate of -r x 1o 1ons/cJ. Thereafter, heat treatment is performed for about 60 minutes in an N2 atmosphere at a temperature of about 1000° C., whereby the implanted B and As ions are diffused to form an active base region 112 and an emitter region 113.

At this time, the defect layer induced by ion implantation is indicated by the broken line 114.
It becomes as shown in (Fig. 3E). Next, emitter 9 area 111
After removing the upper Si3N4 film 1.04 and opening a contact window on the inactive base region 1oγ, the emitter electrode 116. A base electrode 116 is formed (FIG. 3F).

In the method shown in FIG. 3, the p-type impurity region 110 is formed by diffusion.
The active base 112 and the inactive base 107 are electrically connected to each other, and the defects 10 excited by ion implantation are
7 and 114 cross the pn junction between the emitter 13 and the base 112, and the inactive base 107 and the active base 112 can be reliably connected without being affected by heat treatment different from the first embodiment.

Further, FIG. 4 shows cross-sectional views of each process in the third embodiment of the present invention. This will be explained below with reference to FIG.

On the main surface of the n-type silicon substrate 101, an 8102 insulating film 102 having a thickness of approximately 400 nm is formed by, for example, an oxidation method.

An opening 103 is provided in the base region (FIG. 4A).

Next, about 500 people applied 513N4 membrane 104 to CvD'Sio.
2 films 105 are deposited by about 2,000 people (FIG. 4B). After that, a resist 106 is formed in the opening 103, and a CV D S 102 film IQ5 is formed using this resist 106 as a mask.
etching. At this time, side etching is performed so that a canopy is formed in the resist 106.

Furthermore, boron is applied at 1X at 80 KeV through the 5laN4 film using the resist) 106 and Sio2 insulating film 102 as a mask.
An inert base 107 is formed by implanting ions of about 1015 ionsAi. At this time, the defect layer excited by the ion implantation becomes like 108 (FIG. 4C).

Next, remove the resist 106' CV D S i02
Using the film 105 as a mask, the S l s N 4 film 104 is removed, and a p-type impurity region 110 is formed using the oxide film 109 containing boron as a diffusion source (FIG. 4D). The oxide film 109 containing boron and the CVD S 102105 are removed, and a thermal oxide film 111 is formed using the Si3N4 film 104 as a mask.

Next, using the oxide film 111 and the SiO2 insulating film 103 as masks, B ions are irradiated with 3×10 B ions at an acceleration voltage of 40 KeV.
14ions,/cm, A s ions at 180Ke
Ion implantation is performed at an acceleration voltage of V at 7×10 15 ion fl/cm. Thereafter, heat treatment is performed for about 60 minutes in an N2 atmosphere at a temperature of about 1000''C, whereby the implanted B and A8 ions are diffused to form an active base region 112 and an emitter region 113.

At this time, the defect layer induced by ion implantation is indicated by the broken line 114.
It becomes as shown in (Fig. 4E). Next, the emitter area 111
After removing the upper Si3N4 film 104 and opening a contact window on the inactive base region 107, the emitter electrode 115. Forming the base electrode 116 (FIG. 4F)
).

Similarly to the second embodiment, in the method shown in FIG. 4, defects excited by ion implantation do not cross the pn junction. Furthermore, since ions are implanted through the Si3N4 film 104 when forming the inert base 10-7, there is less contamination.

It should be noted that although the above description refers to npn transistors, the present invention is also applicable to pnl)) transistors.

Moreover, various kinds of impurities can be used.

Effect of the invention Based on the above, the present invention has the following features.

(1) Form an oxide film around the region that will become the emitter.

By implanting ions into the active base emitter from the same window, defects induced by the ion implantation are incorporated into the sloped wall that becomes the emitter, thereby reducing leakage current at the pn junction.

(2) High frequency and low noise...The inert base is formed by ion implantation, and the maximum concentration region can be formed inside the semiconductor substrate, so the sheet resistance can be kept low in the subsequent oxidation process, and the base resistance can be made small and can achieve high frequency and low noise.

(3) To form an inert base by ion implantation.

The junction depth can be made shallow, allowing for higher density.

As described above, the present invention contributes to providing a high-speed, high-density, and high-precision semiconductor device.

[Brief explanation of drawings]

FIGS. 1A-F are cross-sectional views of the manufacturing process of a conventional npn transistor, and FIGS. 2A-F are cross-sectional views of the manufacturing process of an npn transistor using double ion implantation according to an embodiment of the present invention.
3A-3F and FIGS. 4A-4F are cross-sectional views showing the manufacturing process of a transistor according to another embodiment of the present invention. 101...Silicon substrate, 102...
S102 membrane. 1o4...Nitride film, 105...CvD
SiO2, 106...Resist mask, 107...
... Inert base, 109 ... Oxide film containing boron, 110 ... Diffusion region, 112 ...
...Active base, 113...mark/emitter region. Name of agent Patent attorney Toshi Nakao Haga 1 Figure 1 Figure 2 I03 (Q'l Iυdo-12 Figure 3 fO'l fOtJ Figure 3 1f2 10'/ @Figure 4 03 tθ7 tuσ @4 diagram

Claims (2)

[Claims] (1) A step of forming an insulating film on a semiconductor substrate of one conductivity type and removing the insulating film in a desired region, forming an oxidation-resistant film, and forming a masking film in a part of the desired region. , using the above film as a mask. a step of removing the oxidation-resistant film so that the film is formed in a 7-shape shape; using the film and the insulating film as a mask, ions are implanted onto the semiconductor substrate of the other conductivity type; a step of removing the coating film and forming a thermal oxide film using the oxidation-resistant film as a mask; a second region of the other conductivity type using the thermal oxide film and the insulating film as a mask; and a method for manufacturing a semiconductor device, including the steps of forming a third region of one conductivity type in the second region and electrically connecting the second region and the first region. (2) After forming the first region of the other conductivity type, a fourth region of the other conductivity type in contact with the first region is formed by diffusion using the oxidation-resistant film and the insulating film as masks. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the fourth region is electrically connected to the second region of the other conductivity type. @) Claim 2, characterized in that the junction depth of the fourth region is equal to or shallower than the junction depth of the second region.
0 (4) Forming an oxide film between the film and the oxidation-resistant film, forming a first region by implanting ions through the oxidation-resistant film, and removing the film, removing the oxide film. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the oxidation-resistant film is removed as a mask.