JPS6068646A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enable to form an accurate semiconductor device with less irregularity of side etching and current amplification factor by reducing the number of oxidizing steps, thereby enabling to flattening simultaneously upon forming of a thin oxidized film. CONSTITUTION:After N type buried regions 2a, 2b, N type epitaxial layer 3, an Si3N4 film, an oxidized film 7, an N type high density collector region 8 are formed on an N type silicon substrate 1, the Si3N4 film is removed, the Si3N4 films 109a-109c are again formed, diffused with a BSG film, and a region 110 to become a graft base and high resistance diffused region 111 are formed. With the resist 112 as a mask boron ions are implanted to form a high resistance layer 113, the resist 112 and the Si3N4 films 109a, 109c are removed, with the film 109b as a mask an oxidized film 114 is selectively formed, boron is further implanted to form an active base 115, and an emitter 116. A contacting hole is opened, and the film 109b is removed, thereby forming electrodes 117-119 of the base and emitter, and electrodes 120, 120' of high resistance portions.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor device, and particularly to a method for manufacturing a semiconductor device with high density, high speed, and high precision.

, Conventional configurations and their problems In recent years, semiconductor devices have become faster and more dense, and there is a trend towards lower power consumption. ), and to satisfy this demand, the emitter part is selectively oxidized using an oxidation-resistant film, and the active base and emitter are selectively oxidized using this selective oxide film as a mask. There is a method of forming by ion implantation and also forming a high resistance part by ion implantation, and FIG. 1 shows cross-sectional views at each step of this method. This will be explained below with reference to FIG.

An n-type buried region 2 a is formed on the main surface of the P-type Si substrate 1 .

2b and the n-type epitaxial layer 3 at 0.69-α
After forming the S 13Na film 4 with a thickness of approximately 2 μm, the thickness of the S 13Na film 4 is approximately 1 μm.
After 500 resists are deposited, resist 6 is deposited using a photorin process.
8. Then, using the resist 6 as a mask, the Si3N4 film 4 and a part of the epitaxial layer 3 are etched. While removing the resist 5, a Si3N4 film is deposited on the entire surface by low pressure CVD or the like, and an Si3N4 film 6 is formed on the side surfaces by anisotropic etching using dry etching or the like). Using the Si3N4 films 4 and 6 as masks, a thick oxide film T is formed by high pressure oxidation or the like. At this time, the S 13N a film on the side surfaces suppresses oxidation in the lateral direction, and as a result, bird's beaks do not occur and high density can be achieved. After that, 513N4 of the island region where the transistor is formed
A part of the film 4 is removed and an n-type high concentration collector region 8 is formed q. The Si3N4 films 4 and 6 are removed, a thermal oxide film 9 is formed, a portion of which is removed, and a 513N4 film 10 is deposited approximately 5 times in the region that will become the emitter of the transistor island region.
Formed 00 people.

Using the thermal oxide film 9 and the SlSN4 film 10 as a mask, a BSG film (boron-containing
(film) p) Performs fc diffusion to form a region 11 that will become a graft base and a high resistance contact diffusion region 12.

Using the Si3N4 film 1o as a mask, the selective oxide film 13 is
This selective oxide film 13 is used as a mask to form a film of 40 KeV I X 10'' (yB-2
, As was ion-implanted to the order of 7 x 1015□-2.
After heat treatment at 000℃ for about 16 minutes, active base 14
．． Emitter 16 is formed. At this time, since the active base and emitter ions are implanted from the same window, the ion implantation-induced defects are incorporated into the trench Z'7, as shown by the broken line 16 in the figure, and do not cross the base-emitter junction.

After this, using resist 1 as a mask, oxide moon mo 9 and 1
At the same time, using the resist 1 as a mask, boron ions are implanted at 60 KeV and about 1.5×10 3 Crn-2 to form a high resistance layer 18 (E).

Thermal oxidation is performed using the SiN film 10 as a mask to form an oxidized film.
Approximately 2,000 S13N holes were formed, and contacts for the collector, base and high resistance parts were formed, and then S13N was formed.
4 Remove film 1o, collector and base.

Emitter electrodes 20, 21, 22 and high resistance part electrode 23
．． 23' (F). Note that in step B, the Si3N4 films 4 and 6 are formed directly on the epitaxial layer 3, but S s O2 is formed between the epitaxial layer and the Si3N4 film.
A film may also be formed.

The semiconductor device formed in this manner has the following advantages.

(1) High density and high speed with self-aligned contacts (2) High precision (a) Less variation in current amplification factor...The active base and emitter are formed by ion implantation.

(b) Low leakage current: Defects excited during ion implantation are trapped within the emitter, as indicated by the dotted line 16 in FIG. 1E, and do not cross the base-emitter junction.

However, the oxide film 9 whose oxide film formation process is a step,
The steps shown in Figure 3, including the oxide film 13 in step E and the oxide film 19 in step F, are required, but as the difference (L comes), the oxide film 9
This results in a thick oxide film. As a result, there are the following drawbacks.

(1) Accuracy of high resistance decreases... Oxide film 9 force; Due to the thickness, side etching and sore amount increase 11 during etching.
Therefore, (2) it is difficult to form contact holes...Due to the thick oxide film, the amount of etching and drilling required when forming contact holes increases, making side etching more likely to occur.

OBJECTS OF THE INVENTION In view of these conventional problems, it is an object of the present invention to provide a method for manufacturing a semiconductor device with high precision, high speed, and suitable for high precision.

Structure of the Invention The present invention involves forming a graft base region and a high-resistance contact diffusion region by diffusion using an oxidation-resistant film as a mask, and then forming a high-resistance layer through the oxidation-resistant film using a resist as a mask. The oxidation-resistant film in areas other than the emitter area is removed, a selective oxide film is formed using the oxidation-resistant film in the emitter area as a mask, and the active base film is formed using this selective oxide film as a mask.
By forming the emitter by ion implantation, the number of oxidation steps can be reduced, thereby making it possible to form a thin oxide film and flatten it at the same time.

Description of examples FIG. 2 shows cross-sectional views of each process in an embodiment of the present invention.

This will be explained below with reference to FIG.

Conventional example As shown in steps A, B, and C in Fig. 1, an n-type silicon substrate 1
On top are n-type buried regions 2a, 2b and an n-type epitaxial layer 3.
After forming the Si3N4 films 4 and 6, the oxide film 7, and the n-type high concentration collector region 8, the Si3N4 films 4 and 6 are removed, and the Si3N4 film 109a is formed again.

109b and 109C are formed, and a Si3N4 film 109a is formed.

Using 109b and 109c as masks, diffusion is performed using a BSG film (CVD S 102 film containing boron) to form a region 110 that will become a graft base and a high-resistance contact diffusion region 111 (A). Using the resist 112 as a mask, holon ions are implanted at 80 KeV and about 1.5 x 1016 cm-2 through the Si3N4 film 109C to form a high-resistance layer 113). The resist 112 is removed and the Si3N4 film 109a is formed.

At the same time as removing the 109C, using the Si3N4 film 109b as a mask, approximately 3000 oxide films 114 are selectively formed.
40 KeV I Xl 0”cm-
2°A, B are ion-implanted at a rate of about 7×1015α-2, and heat treatment is performed at 1000°C for about 30 minutes in a nitrogen atmosphere to form an active base 115 and an emitter 116q0
Collector, base, and high-resistance contacts are opened and the Si3N4 film 109b is removed to form collector, base, and emitter electrodes 117°, 118, and 119, and high-resistance portion electrodes 120 and 120'. In this case, the respective oxide film thicknesses on collector 8, graft base 110, high resistance contact diffusion region 111, and high resistance 113 are equal.

From the above, the method of the present invention has the following features.

(1) High accuracy of high resistance. ... Since the high-resistance pattern is formed with resist, there is no problem with side etching.

(c) Easy contact opening: Since a thin and uniform oxide film is etched, the present invention has the following advantages: (3) There is little variation in current amplification factor. ...Since there is no need for an oxidation process after ion implantation of the active base/emitter, there is little variation in current amplification factor. Figure 3 shows the variation in current amplification factor.

FIG. 3A shows a case formed by a conventional method, and FIG. 3B shows a case formed according to the present invention. It can be seen from this figure that the current amplification factor is clearly smaller.

(4) Less short circuit between electrodes・Mountains・When insulation oxidation separation is performed, deep grooves 24a, 2Jb are formed in the insulation oxidation region when opening holes in the oxide film 9 in the first drawing step.
, 24c are formed, and this groove remains until the F step and At remains in this groove during At etching, causing a short between the electrodes.

On the other hand, in the present invention, since this groove is not formed, no short circuit occurs between the electrodes.

As described above, the present invention contributes to the provision of a high-precision, high-speed, high-density semiconductor device with fewer oxidation steps, less side etching, less variation in current amplification factor, etc.

[Brief explanation of drawings]

, FIGS. 1A to 1F show the oxide film separated by the conventional method.
Figure 2 is a cross-sectional view of the manufacturing process of a pn transistor and a semiconductor device with high resistance; Figure 3A shows the variation of the current amplification factor of the npn transistor formed by the conventional method.
FIG. 2 is a diagram showing variations in current amplification factors of npn transistors formed by the method according to the present invention. 1...Silicon substrate, 2a, 2b...N-type buried region, 3...Epitaxial layer, 109a. 1o9b, 109G...Si3N4 film, 114
・Oxide film, 110...Graft base, 111-
- High resistance contact diffusion region, 115- active base,
116...--Emitter, 117, 118, 119
°120, 12 ot--electrode. Name of agent: Patent attorney Toshio Nakao (1st person)
Figure @ Figure 1 Figure 2 Figure 2

Claims (2)

[Claims] (1) On one conductivity type substrate, the first conductivity type substrate is placed on the other conductivity type substrate. forming a second island region, forming an oxidation-resistant film on the substrate and on the first regions of the first and second island regions, and diffusing the first and second island regions using the oxidation-resistant film as a mask; One conductivity type second. a step of forming a third region; a step of ion-implanting a fourth region of one conductivity type under the oxidation-resistant film in the second island region so as to be electrically connected to the third region using a mask layer; , a step of removing the surface-first oxide film on the first island region except for a desired region, and selectively oxidizing the oxidation-resistant film in the desired region using the oxidation-resistant film as a mask; forming an active base by ion implantation using the oxide film as a mask; A method for manufacturing a semiconductor device including at least the step of forming a fifth region of one conductivity type to serve as an emitter, and a sixth region of the other conductivity type to serve as an emitter. (2) First. Claim 1, characterized in that it includes a step of isolating the side surfaces of the second island region with an insulator.
A method for manufacturing a semiconductor device according to section 1.