JPS62287635A - 半導体素子結線用細線 - Google Patents

半導体素子結線用細線

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Publication number
JPS62287635A
JPS62287635A JP61132566A JP13256686A JPS62287635A JP S62287635 A JPS62287635 A JP S62287635A JP 61132566 A JP61132566 A JP 61132566A JP 13256686 A JP13256686 A JP 13256686A JP S62287635 A JPS62287635 A JP S62287635A
Authority
JP
Japan
Prior art keywords
copper
wire
semiconductor element
fine wire
ball
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61132566A
Other languages
English (en)
Inventor
Yoichi Yorita
寄田 洋一
Masaaki Shimotomai
下斗米 将昭
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
OPTIC DAIICHI DENKO CO Ltd
Mitsubishi Electric Corp
Original Assignee
OPTIC DAIICHI DENKO CO Ltd
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by OPTIC DAIICHI DENKO CO Ltd, Mitsubishi Electric Corp filed Critical OPTIC DAIICHI DENKO CO Ltd
Priority to JP61132566A priority Critical patent/JPS62287635A/ja
Publication of JPS62287635A publication Critical patent/JPS62287635A/ja
Pending legal-status Critical Current

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147Copper (Cu) as principal constituent
    • HELECTRICITY
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    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78Apparatus for connecting with wire connectors
    • H01L2224/7825Means for applying energy, e.g. heating means
    • H01L2224/783Means for applying energy, e.g. heating means by means of pressure
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    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852Applying energy for connecting
    • H01L2224/85201Compression bonding
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    • H01L2924/012055N purity grades, i.e. 99.999%
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    • H01L2924/102Material of the semiconductor or solid state bodies
    • H01L2924/1025Semiconducting materials
    • H01L2924/10251Elemental semiconductors, i.e. Group IV
    • H01L2924/10253Silicon [Si]

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 3、発明の詳細な説明 (発明の利用分野) 本発明は、半導体素子上の電極と外部リードとの結線に
用いる半導体素子結線用細線に関する。
(従来技術) ICやLSI等の半導体素子において、例えば第2図に
示すようにSi半導体チフプlの電極2と外部リードフ
レーム3とを結線用細線4で電気接続するようになって
いるが、この接続は作I性に優れたボールボンディング
法が主に用いられている。本方法は第1図に示すように
このボンディング法に用いられるキャピラリ5の先端部
に結線用細線4を露出させて、その先端部を電気アーク
あるいは水素アークにより加熱させてボール6を形成し
、これを第2図に示すように半導体チップ1の電極2に
熱圧着により接続し、次に弧を描くように細線4を延ば
し、外部リードフレーム3に細線4の一部を超音波圧接
し、切断するようにしたものである。
従ってこの種結線用細線4としては、高導電性を維持で
きること、上述のように半導体素子の電極への圧着に用
いるキャピラリ5との通過時に細粉がキャピラリに付着
して細粉詰まりを起こさせないようにすること、高導電
性を維持できること、上記電極に充分に均一に圧接する
よう安定したボール6に形成されること、ボール6の電
極への接着強度が高いこと、結線用細線4が上記電極2
と外部リードフレーム3と接続されたとき弧を描くよう
、■ちループ状につながれること(このループ線が第2
図で一点鎖線で示すように寝すぎるとボール6の根元で
断線されやすい)、などが要求される。
ところで従来は、半導体素子結線用細線として、銅の物
理的特性を利用し、これにBe、 Sn、 Zn、 A
g、 Zr、 Cr、 Fe等を0.1〜2重量%添加
した銅合金が用いられているが、これをボールボンディ
ング法にて使用した場合次のような欠点があった。
まずSi素子上に銅合金ボールを熱圧着する際、銅合金
ポールの硬さが必要以上に大きいため、素子電極面にク
ラックを生じる。
銅合金ポールの硬さを小さくするために、熱圧着温度あ
るいはキャピラリ温度を上げるとループ線が寝すぎて良
好なループ形成性をもたすことが不充分になり断線の原
因となる恐れがある。
また銅合金のほとんどを占める銅の細粉がキャピラリを
通過する際に多く発生し、キャピラリの銅粉詰まりを起
こし結線作業上支障をきたす事態がある。
(発明が解決しようする問題点) 本発明の目的は銅の物理的特性を失うことなく、これを
最大限に生かし、かつボールポンディングに通した硬さ
で、その作業性に優れた半導体素子結線用細線を提供し
ようとするものである。
(問題点を解決するための手段) 上記目的を達成するために本発明は、純度99.999
%以上のCuを素材料として、これにCoを10〜11
00pp含有させた銅合金細線からなる構成を採用する
ものである。
なおまたその実施態様として前記銅合金細線は0.01
〜0.1鰭φに形成されてなるものである。
(作用) 銅の純度を99.999重量%以上としたのは、結線用
細線の変形挙動を金線の場合に可能な限り近づけ、圧着
時にSi半導体素子を損傷することなく充分安定であり
、高導電性と信頼性に優れた接続を得るためで、99.
999重量%未満では、まれにSi半導体素子にクラッ
クを生じさせやすいことがわかっている。
またこの高純度の銅にCoを含有させたのはCoは他の
全屈元素に比べて格段に銅との親和性が高いためで、こ
れによって銅系の外部リードフレームとの接合性が非常
に良くなる。
またCoの含有量を10〜1100ppとしたのは、1
0ppm未満ではワイヤ(細線)の強化度が不充分であ
り、また100pp−以上では銅合金のボールが硬くし
て半導体素子を損傷することになり、いずれも本発明の
効果を期待することができないからである。
(実施例) 以下、この発明の実施例に係る半導体素子結線用細線1
〜3と比較例の同細線4〜6および他の比較例の同細線
7についてシリコン素子のクランク不良率、細線の硬度
、銅粉の発生率、ボール形成性、ループ形成性を測定し
た。下記表1がそれである。
なおこの発明に係る実施例階1〜Ih3は次のようにし
て製造されたものである。即ちゾーンメルト法により製
造された99.999%のCuを素材料として、これを
真空熔解を行い、これにCOを表1に示すように10〜
looppmの範囲内で添加し、これを充分に混合熔解
させた後、1511φの棒形状に急冷鋳造し、次にこの
棒材を皮剥し、焼鈍と50〜60%の伸線加工を繰返し
25μφの銅合金細線に仕上げ、これをArガス雰囲気
中で電気アークによりボールを形成し、シリコン素子上
のAI電極およびリン■銅系外部リードフレームとの接
続を行った。さらに第3図に示すようにこの銅合金細線
4をボンダー用セラミック製キャピラリ5に挿通させて
から該細線を2000 m長さ巻取機7に巻取り、これ
によってキャピラリでの銅粉発生量を目視で調査した。
また比較例の階4〜階6に示すものは、上記と同一の製
造工程でCoの添加量を変えたものまたは添加しないも
のである。
以下余白 表=1 (効 果) 本発明によれば、表2から明らかなように99.999
%以上の純度の非常に高い銅を採用するためボールの変
形抵抗が小さく (金に近く)シリコン素子のti傷が
なく、また微量のCo添加により銅との親和性の非常に
高いため銅系の外部リードフレームとの接合性が格段に
よく、また高温強度が向上し、ループの形成性が良好で
あり、耐摩耗性が向上するためキャピラリ挿通時の銅粉
の発生がほとんどなくその銅粉詰まりはほとんど発生せ
ず、これらの相乗作用によってボンディング条件範囲が
広くなり安定したボンディング作業を行うことができる
【図面の簡単な説明】
第1図は本発明の一実施例における半導体素子結線用細
線をキャピラリに挿通させて、その先端部に形成される
ボールの状態を示す説明図、第2は同極線で半導体素子
に接続された状態を示す説明図、第3図は同細線のキャ
ピラリ挿通時の同粉の発生率を調べるための実験方法を
示す図である。 同     弁理士 久保幸雄 第  1 図 第2図 第3図

Claims (1)

  1. 【特許請求の範囲】 1、純度99.999重量%以上のCuを素材料として
    、これにCoを10〜100ppm含有させた銅合金細
    線からなる半導体素子結線用細線。 2、前記銅合金細線は0.01〜0.1mmφに形成さ
    れてなる特許請求の範囲第1項記載の半導体素子結線用
    細線。
JP61132566A 1986-06-06 1986-06-06 半導体素子結線用細線 Pending JPS62287635A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61132566A JPS62287635A (ja) 1986-06-06 1986-06-06 半導体素子結線用細線

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61132566A JPS62287635A (ja) 1986-06-06 1986-06-06 半導体素子結線用細線

Publications (1)

Publication Number Publication Date
JPS62287635A true JPS62287635A (ja) 1987-12-14

Family

ID=15084298

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61132566A Pending JPS62287635A (ja) 1986-06-06 1986-06-06 半導体素子結線用細線

Country Status (1)

Country Link
JP (1) JPS62287635A (ja)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6199645A (ja) * 1984-10-20 1986-05-17 Tanaka Denshi Kogyo Kk 半導体素子のボンデイング用銅線

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6199645A (ja) * 1984-10-20 1986-05-17 Tanaka Denshi Kogyo Kk 半導体素子のボンデイング用銅線

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