JPS62272719A - Interruption address generating circuit - Google Patents

Abstract

PURPOSE:To attain the miniaturization of a circuit by connecting source of plural transistors (TRs) whose gates are connected in common to the highest order input signal line to drains of the TRs in common so as to decrease the occupied area of the titled circuit. CONSTITUTION:A source of TRs receiving a signal from the lowest order input signal line 3 or 6 is connected to grounding potential and its drain is connected to a source of a TR receiving a signal of the higher input signal line 2 or 5. Drains of the TRs receiving the signal from the input signal line 2 or 5 are connected in common to sources of plural TRs receiving a signal of the highest order input signal line 1 or 4 in common. The drain of each TR corresponding to the highest order input signal line 1 or 4 is connected to plural address signal lines individually or opened. The circuitry of the constitution above copes with the case of plural input signals and the increased address length.

Description

3. Detailed Description of the Invention Field of Industrial Application The present invention relates to an address generation circuit for internal and external interrupts of, for example, a microcomputer.

2. Description of the Related Art Conventionally, this type of interrupt address generation circuit has had a configuration as shown in FIG. In Figure 3, 1 to 6 are input signal lines of weighted codes, and the source of the transistor corresponding to the highest input signal line 1 is connected to the drain of the transistor corresponding to the next input signal line 2. Furthermore, the source of the transistor corresponding to the next input signal line 2 is connected to the drain of the transistor corresponding to the lowest input signal line 3. The source of the transistor corresponding to the lowest input signal line 3 is at ground potential or the other potential of the power supply VS
Connected to S. The drain of the transistor corresponding to the highest input signal line 1 is connected to the address signal or is in an open state. Transistor circuits having such a configuration were arranged in parallel according to the number of address signal lines 7 to 10 (number of bits).

Problems to be Solved by the Invention In such a conventional configuration, as the address length increases, the number of arrays increases, and as the number of input signal lines increases, the number of transistors becomes enormous. There is a problem in that the area of the circuit occupied by the transistor increases.

The present invention solves these problems and provides a semiconductor integrated circuit that reduces the area occupied by the circuit and is no different from conventional circuits.

Means for Solving the Problem In order to solve this problem, the present invention provides that each drain is arranged in such a manner that it can be individually coupled to a plurality of address signal lines, and each gate is connected to the highest input signal line. a plurality of transistors commonly coupled to a line, and a single transistor whose sources are commonly connected to a drain and whose gates are coupled to successively higher input signal lines, An interrupt address generation circuit is provided in which the source of the single transistor is connected to the ground potential or the other potential of the power supply, either directly or through transistors sequentially coupled to lower input signal lines.

Effect: With this configuration, the number of transistors corresponding to input signals other than the most significant one can be satisfied with one, regardless of the address length. This makes it possible to reduce the circuit area occupied by a considerable number of transistor elements.

Embodiment FIG. 1 shows an interrupt address generation circuit according to an embodiment of the present invention. In FIG. 1, 11 is a precharge circuit for interrupt address signal lines 10-7. 1-6
indicates an interrupt input signal line. Bottom input signal line 3
The source of the transistor to which the signal of 6 or 6 is input is connected to the ground potential or the other potential vSS of the power supply, and the drain is connected to the source of the transistor to which the signal of the upper input signal line 2 or 5 is input. The drains of the transistors that receive the signal on the input signal line 2 or 5 are commonly connected to the sources of the plurality of transistors that receive the signal on the highest input signal line 1 or 4 as a common input. The drain of each transistor corresponding to the highest input signal line 1 or 4 is individually connected to a plurality of address signal lines or is in an open state. The circuit of this configuration is possible even when there are a plurality of input signals and a plurality of address signals, that is, when the address length increases.

The operation of this circuit will be explained below.

All the signal lines 7 to 10 of the address signals Ao-A3 are connected to the respective precharge circuits 11 before the interrupt is applied.
It is precharged by. When each input signal line 1 to 6 becomes high level at the same time, an interrupt address is generated. At this time, the highest input signal line 1 or 4
The drain of the transistor corresponding to the transistor becomes low level, the address signal to which the drain is connected becomes low level, and the unconnected address signal becomes high level because it holds a precharge. For example, when all the human power signal lines become high level at the same time, the address signals A3 to Ao, that is, (A3A2AIAO) are (1,
OOO).

FIG. 2 shows a timing chart of each signal.

Effects of the Invention According to the circuit of the present invention, only one transistor is required for input signals other than the highest input signal, so even if the address length increases and the number of address signals increases, the highest input signal The transistors corresponding to the signals only increase in response to the increase in address signals, and the other transistors can be removed, which has the effect of reducing the area occupied by the circuit. Furthermore, for input signals other than the highest order, the number of transistors that use the input signal as a gate input is reduced to one, so that an effect of improving the operating speed can also be obtained.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram of an embodiment of the present invention, FIG. 2 is a timing chart of the circuit of the embodiment, and FIG. 3 is a circuit diagram of a conventional example. 1~6...Interrupt input signal line, 7~10...
...Address signal line, 11...Address signal line precharge circuit. Figure 1 7 Figure 3 Figure 2 10 As----1-]-9A2-U-- AO

Claims (1)

[Claims] A plurality of transistors each having a drain arranged in a state that can be individually coupled to a plurality of address signal lines, and each gate having a common coupling to the highest input signal line, and a common source of each of the plurality of transistors. and a single transistor whose drain is connected to the input signal line and whose gate is coupled to a sequentially lower input signal line, and the source of the single transistor is coupled directly or sequentially to a lower input signal line. An interrupt address generation circuit configured to be connected to ground potential or the other potential of a power supply via a transistor.