JP2737689B2 - Semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is related to semiconductor devices. 2. Description of the Related Art Conventional one-chip microcomputers are provided with input / output as shown in MCS ^R -48 shown in Chapters 2 to 4 of the 1983 Microcontroller Handbook of Intel Corporation. As a means, a circuit commonly used in many application fields, such as a parallel input / output port and a timer, is fixedly provided. In each application, the missing circuits were added to the outside and connected to the microcomputer via the input / output boat. [0003] In Japanese Patent Application Laid-Open No. 57-124463, a CPU is used as a core, has an I / O port, and random logic is configured by a master slice around the CPU. However, in the above-mentioned prior art, when the input / output function of the one-chip microcomputer is insufficient, or when the RAM or ROM
In the case where the device is extended to the outside, the number of circuits to be added to the outside increases, the number of necessary IC chips also increases, and miniaturization and cost reduction of the device have been prevented. Therefore, the present invention solves such a problem, and the purpose thereof is to:
On a single board, a one-chip microcomputer organically coupled with a microcomputer and having peripheral circuits with optimal functions for each of various applications is created by changing a few masks, The point is to supply it cheaply. According to Japanese Patent Application Laid-Open No. 57-124463, a signal cannot be output from a random logic section. [0006] A semiconductor device according to the present invention comprises:
In a semiconductor device in which a microcomputer section and a gate array section having a plurality of basic logic cells capable of forming a desired logic are integrated on a single chip, the semiconductor device is connected to the microcomputer section from outside the chip. An input / output circuit for inputting a signal of the microcomputer or outputting a signal from the microcomputer section to the outside of the chip, wherein the gate array section has a first input section for inputting a signal output from the microcomputer section. an input terminal of the previous entry
The signal output from the output circuit to the outside of the chip is
According to have a second input terminal for inputting to the configuration of [0007] [act invention, wherein, the circuit required for each of the applications made using a GA unit, writes the circuit By making an IC using an aluminum wiring mask,
With the CPU as a core, a semiconductor device having a peripheral circuit function optimal for each application can be provided. In addition, Micro
Signal from the computer section through the input / output circuit.
Can be output to the
The equivalent function of the computer and its peripheral circuits
Into a single chip by configuring
The same circuit as the original peripheral circuit
It can be configured as a part. FIG. 1 is a layout diagram of a chip according to an embodiment of the present invention. In the figure, 1 is a silicon substrate, 2 is a RAM,
Reference numeral 3 denotes a ROM, reference numeral 4 denotes a CPU unit, and reference numeral 5 denotes an input / output port, which is an 8-bit parallel input / output port. When the RAM and ROM are externally extended, they serve as bus terminals for connecting them. Reference numeral 6 denotes an internal data bus connecting these. Reference numeral 7 denotes a GA unit. The parts other than 7 are microcomputer parts.
8 in the GA section are input / output cells, each having a pad 8 '.
The cells 9 arranged in the horizontal direction are basic cells. Then, the area between them becomes the wiring area. The GA section in this embodiment will be described in more detail. FIG. 2A is a structural diagram of a basic cell. FIG. 2B shows an equivalent circuit thereof. In this embodiment, C
It has a MOS structure. Reference numeral 16 denotes a boundary between the N well (upper side) and the P well (lower side). 17 is polysilicon, 18 is polysilicon-aluminum contact, 19 is P-channel diffusion, 20 is P-channel diffusion and aluminum contact, 2
Reference numerals 1 and 22 denote N-channel diffusion and contacts thereof, 23 denotes a high-voltage-side power supply aluminum, and 24 denotes a low-voltage-side power supply aluminum. 18 ', 22', 23 ', 24' in the equivalent circuit diagram correspond to 18, 20, 22, 23, 24 in the structural diagram.
Reference numeral 25 denotes three P-channel MOS transistors, and reference numeral 26 denotes three N-channel MOS transistors. MOS transistors of one or more basic cells are connected by aluminum, and a minimum unit price having a specific logic function called a cell is created. 3-input NAND as cell example
3A and 3B are a structural diagram and an equivalent circuit diagram, respectively. In the figure, a thick black line 27 indicates an aluminum wiring for forming a cell. Cells include inverters, buffers, NANDs,
There are a cell latch for interface including NOR and Schmitt trigger, a flip-flop, and the like, which are registered as a library. At the time of design, a cell having a necessary function is designated from this library, and connection between cells is performed. The connection of the transistors and the connection between the cells are formed by aluminum wiring. The input / output cell is a part for inputting / outputting signals between the GA unit and the outside of the chip, and FIG. 4 shows an equivalent circuit diagram thereof.
In the figure, reference numeral 28 is connected to the outside of the chip by bonding a gold wire or the like with a pad. 29 is a P-channel MOS transistor. 30 is an N-channel MOS transistor. Reference numeral 31 denotes a P-channel MOS transistor for a pull-up resistor having an on-resistance of about 50 KΩ, and reference numeral 32 denotes a switch for determining whether the pull-up resistor is used or not. 3
3 is an input protection resistor. 34 to 36 are connection terminals with the GA unit. The following input / output specifications can be selected by processing the connection terminals 34 to 36 and opening and closing the 32 switches. Input specifications: T depends on the selection of the interface cell connected to the presence / absence of pull-up 31
TL level input, CMOS level input, and Schmitt trigger input can be selected. Output specifications: Complementary, P-channel open drain, N-channel open drain, and 3-state output can be selected. Next, the connection between the CPU unit and the GA unit will be described. As shown in FIG. 1, an internal timing signal (bar S1, bar S2, bar S3) is sent from the CPU unit to the GA unit.
S4, S2X, S3X) 10, a reset signal (RST) 11, an instruction decode output signal (MOVGA, MOVAG, SELGX, SELG) generated by the instruction.
Y, IRO, IR1) 12 are connected around the GA section so that an interrupt signal (INTRPT) 13 can be connected from the GA section to the CPU section. or,
Input terminal of external timing signal 15, input / output port circuit
5 (DB0, DB1,..., DB7) 14 are input.
Input terminal (second input terminal) and internal bus (U0V to U7
V) The input terminal (first input terminal) for inputting the signal of 6 is also arranged. The circuits in the GA section can be easily connected to many of these signals by aluminum wiring.
This is due to having the parts on the same silicon substrate. By changing one aluminum mask in this way, it is possible to produce a one-chip microcomputer having various input / output terminals and an arbitrary peripheral circuit controlled by various signals of the CPU. Will be possible. Further, the GA section and the CPU section are tightly coupled by the above-mentioned many signals. For example, one instruction MOVG
At A, the data of the register in the CPU can be transferred to the GA. FIGS. 5A and 5B show this timing chart and G
The circuit diagram of the part A is shown. In the figure, 37 is a clock waveform, 38
Is the waveform of the internal timing signal S4, 39 is the instruction MO
The waveform of the signal (MOVGA) output by the VGA,
41 is a waveform of the internal bus. During execution of the MOVGA instruction, the contents of the register are put on the internal bus in synchronization with the bar S4, so that a strobe signal 40 is created from 38 and 39 and read into the flip-flop (43 in (6)).
4 shows an output waveform of the flop 43. M like MOVGA
OVAG, SELGX, and SELGY are also MOVG instructions.
A, SELGX, and a signal output when SELGY is executed. With these instructions, the execution time of the instruction can be faster than the execution time of the input / output instruction for the input / output port. This means that the GA unit can be directly connected to the internal bus, and
This is due to the fact that the signal is propagated inside the device and the delay is small. FIG. 6 is a circuit diagram showing an application example in which ROM, RAM, and input / output ports are externally extended using MCS ^R- 48 of Intel Corporation, which is an example of the prior art. In the figure, reference numeral 44 denotes a one-chip microcomputer, and reference numeral 49 denotes a bus line connecting a ROM 46 extended to the outside and a RAM 47 with input / output. The bus 49 performs address transmission and data transfer in a time-division manner. The ALE 50 is a signal indicating the timing of latching the address on the bus 49. The RAM 47 has an address latch inside, but the ROM 46 does not have an address latch, so an external latch 45 is required. 48 is an input / output port circuit. Although various circuits can be considered for this circuit depending on the application, it is a part that generally requires many components such as ICs. As described above, conventionally, many external parts are required, and as a result, the cost of parts is increased, and moreover, a large area on the printed circuit board is occupied, which prevents the apparatus from being downsized. On the other hand, if the one-chip microcomputer according to the embodiment of the present invention shown in FIG. 1 is used, the above-mentioned disadvantage can be improved. FIG. 7 shows a circuit diagram as an application example. In the figure, reference numeral 54 denotes the one-chip type shown in the embodiment of FIG.
Microcomputer 46 is ROM, 51 is RAM
It is. A data bus 49 connects the ROM and the RAM. Reference numeral 52 denotes an address line which latches the latch 45 in FIG.
The output is made out of the chip by an input / output cell. As described above, the input / output ports DB0
Since the DB 7 can be connected to the GA unit, there is no need to connect the DB 7 outside the IC to connect to the input / output of the address latch in the GA unit, and the input / output cells can be used efficiently. In this manner, the IC for latch, which is required in the application example shown in FIG. 6, is not required. Reference numeral 53 denotes an input / output port circuit. By forming a part of the circuit in the GA section, the number of external components can be reduced or eliminated. Further, since the CPU unit can control the GA unit at high speed by a dedicated command, high-speed input / output processing is also possible. As described above, according to the present invention, a one-chip microcomputer incorporating circuits required for each application can be manufactured by changing a small number of masks. As a result, the variables of the IC section can be deleted, and the cost and size can be reduced. Also, since signals from the microcomputer unit can be output to the gate array unit via the input / output circuit, functions equivalent to those of a microcomputer and its peripheral circuits can be performed by using the peripheral circuit as a gate array unit. In the case of a one-chip configuration, the same circuit as the original peripheral circuit can be configured in the gate array unit.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a layout diagram of an IC chip showing one embodiment of a one-chip microcomputer of the present invention. FIGS. 2A and 2B are a structural diagram and an equivalent circuit diagram showing an embodiment of a basic cell used in a gate array unit constituting a one-chip microcomputer of the present invention. FIGS. 3A and 3B are a structural diagram and an equivalent circuit diagram showing one embodiment of a basic cell used in a gate array unit constituting a one-chip microcomputer of the present invention. FIG. 4 is an equivalent circuit diagram showing one embodiment of an input / output cell used in a gate array unit constituting the one-chip microcomputer of the present invention. FIGS. 5A and 5B are a timing chart and a circuit diagram showing an application example of the embodiment shown in FIG. FIG. 6 is a circuit diagram showing an application example of a conventional one-chip microcomputer. FIG. 7 is a circuit diagram in which the embodiment shown in FIG. 1 is applied to the same application example as FIG. 6; [Description of Signs] 1 silicon substrate 2 RAM 3 ROM 4 CPU unit 5 input / output port circuit 6 internal bus 7 gate array unit 8 input / output cell 9 {Basic cell 44} One-chip microcomputer 45} Address latch 46 {ROM 47} RAM with I / O 48} I / O circuit 51 {RAM 53} I / O circuit 54} Chip microcomputer

Claims (1)

(57) [Claims] In a semiconductor device in which a microcomputer section and a gate array section having a plurality of basic logic cells capable of forming a desired logic are integrated on a single chip, from the outside of the chip to the microcomputer section An input / output circuit for inputting a signal from the microcomputer section or outputting a signal from the microcomputer section to the outside of the chip, wherein the gate array section has a first circuit for inputting a signal output from the microcomputer section. Output terminal and output from the input / output circuit to the outside of the chip
A semiconductor device having a second input terminal for inputting the signal .