KR900008795B1 - Monolithic semi-custom system lsi - Google Patents

Abstract

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Description

Semi-Custom System LSI

1 is a block diagram showing a circuit configuration according to an embodiment of the present invention.

2 is a block diagram showing the arrangement of the embodiment shown in FIG.

3 is a block diagram showing a conventional circuit configuration.

* Explanation of symbols for main parts of the drawings

1 'to 8': Standard LSI logic section A to D: Gate array (block of gate array)

E: Pad Area

[Industrial use]

The present invention provides a monolithic structure comprising a plurality of standard LSI logic portions having logic components and wiring patterns already completed to operate as LSIs of a single article, and gate arrays forming peripheral circuits of these standard LSI logic portions. It relates to a monolithics semi-custom system LSI (LSI).

[Traditional Technology and Problems]

In recent years, the LSI design technology has been simplified and facilitated by using a gate array as a vertex. By using such a technique, a system engineer can easily perform a LSI design that only a semiconductor engineer can conventionally perform. As a result, the system's LSI has been promoted, contributing to making the device light, thin and small.

On the other hand, in recent years, the use of microcomputers and the surrounding LSI family is prevalent, and in this case, the object of LSI is to include miscellaneous circuits called glue circuits other than the microcomputer and the surrounding LSI family. do. This is because gate arrays or standard cells cannot accommodate large circuits such as microcomputers or peripheral LSI family circuits. Therefore, in the case of constituting a hardware logic circuit in the most compact form, it has been difficult to reduce the size of the hardware logic circuit to a "microcomputer + peripheral family chip + gate array or a standard cell", and to achieve further arcing and high integration.

3 is a block diagram showing an example of the configuration of a system according to the conventional LSI technique. In FIG. 3, reference numerals 30 to 69 denote functional blocks each composed of independent logic circuit elements (semiconductor chips).

Here, reference numeral 30 is a CPU, 31A and 50A are oscillators (OSCs), 31B is a clock generation circuit (CG), 32 is a bus control circuit (BUS-CONT), and 33 and 34 are DMA control circuits (DMA-). CONT), 35 and 40, 47, 48 and 54 are latch circuits (LATCH), 36 is timer circuit (TMR), 37 is interrupt control circuit (PIC), 38 and 45 is mask ROM (MROM), 39 is RAM ( RAM), 41 and 46 are dynamic RAMs (D-RAM), and 42 are dynamic RAM control circuits (DRAM-CONT).

Reference numerals 43 and 49 denote a glue circuit composed of a gate array GA, where 43 is a CRT job circuit (GA-CRT), and 49 is a CPU job circuit (GA-CPU). Reference numeral 44 is a CRT control circuit (CRTC), 50B is a PLL circuit (PLL), 51 is a floppy disk control circuit (FDC), 52 is a floppy disk interface circuit (FDD-IF), 53 is a register (REG), 55 is a video driving circuit (VIDEO-OUTPUT), 56 to 60 and 63 are driving circuits (DRV), 61 is a parity generating circuit (PAR-G), 62 and 64, 65, 66 and 67 are driving circuits / receiving circuits ( D / R), 68 are keyboard / speaker interface circuits (KB-SPK-SW), 69 are numerical data processors, PJ1 and PJ2, and PJ4 to PJ11 are pin-junction portions of the connectors. However, in the above-described circuit elements, symbols (such as 8088) shown in parentheses in the drawings indicate types of typical devices.

As described above, since each of the functional circuits 30 to 69 is composed of independent logic circuit elements (semiconductor chips), it has a certain degree of freedom in circuit design while miniaturizing or simplifying system hardware. There was a flaw in the difficulty.

[Purpose of invention]

Accordingly, the present invention has been invented in view of the above-described circumstances, and the microcomputer and its peripheral circuits are more highly integrated, thereby simplifying system configuration, miniaturization, and low cost, and enabling a system engineer to fully exhibit circuit design technology. The aim is to provide a monolithic semi-custom system LSI that can easily realize any functional circuit configuration.

[Configuration of Invention]

In order to achieve the above object, the present invention has a plurality of standard LSI logic parts having already completed logic structure and wiring pattern functioning as LSI of a single article, and design criteria according to the same process conditions as those standard LSI logic parts. A mask pattern portion having at least one block of gate array for constituting a peripheral circuit of the standard LSI logic portion, and a wiring area for arbitrarily connecting each terminal of each standard LSI logic portion and each terminal of the gate array; Each arranged to have a minimum size; An input / output buffer gate array for an external connection interface is provided to surround each of the above standard LSI logic parts and a gate array, and a lead terminal connection bonding pad portion is provided to surround the gate for the input / output buffer. Make the element common hardware as a master; By interconnecting each of the components in a single-layer to multi-layered pattern wiring to implement a highly integrated monolithic semi-order system LSI.

[Action]

When the system is configured using the semi-custom system LSI according to the present invention having the above-described configuration, the system configuration can be simplified and downsized, and the price can be lowered. Also, the system engineer can fully exhibit the circuit design technology. It is possible to easily configure a system having any function circuit configuration.

EXAMPLE

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

1 and 2 are for explaining one embodiment of the present invention, where FIG. 1 is a circuit block diagram and FIG. 2 is a circuit arrangement diagram (top view).

In Fig. 1, the portion enclosed by a dotted line is an internal hardware block that is the subject of LSI in the present invention, which includes a microcomputer peripheral LSI, a bus control block, an interface logic, an address latch, a data driving circuit / receiving circuit, and the like. It is composed.

The microcomputer peripheral LSI includes a clock generation circuit (CG; corresponds to 8284) (1), a bus control circuit (BUS CONT; corresponds to 8288) (2), and a DMA control circuit (DMA; corresponds to 8237) (3). ), Timer circuit (TMR; equivalent to 8253) (4), interrupt control circuit (PIC; equivalent to 8259) (5), CRT control circuit (CRTC; equivalent to 505S) (6), bidirectional interface circuit (PPI; 8255) 7) and a floppy disk control circuit (FDC; corresponding to 765A) 8 are provided, and as the peripheral circuits, an address latch circuit (LATCH) 9 and an address buffer (ADRS BUF) ( 10), data bus drive circuit / receive circuit (DATA BUF) 11, DMA bus / CPU bus timing controller (DMA READY CPU WAIT) 12, peripheral LSI memory chip select logic (CHIP SEL) 13, DMA Interface section (DMA PAGE REG, GATE, LATCH) (14), FDC interface section (FDC COM REG, FDC INTERFACE) (15), Parity Generation Test Circuit (PG & PC) (16), Keyboard Speaker Interface Circuit (KB SPK) DSW) 17 and the like are provided.

FIG. 2 is an actual LSI plane of the LSI target portion shown in FIG. 1, wherein reference numerals 1 'through 8' correspond to blocks 1 through 8 shown in FIG. It is a standard LSI logic section with already completed logic configuration and wiring patterns. Reference numerals A, B, C, and D denote gate arrays GA, where A denotes a gate array block in which the keyboard speaker interface circuit 17 and the clock divider circuit shown in FIG. The address latch circuit 9, the address buffer 10, the data bus drive circuit / receive circuit 11, the DMA bus / CPU bus timing control section 12, and peripheral LSI memory chip select logic 13 in FIG. And a parity generation inspection circuit 16 or the like is a block of the gate array in which C is combined. C is a block of the gate array in which the DMA interface 14 and the FDC interface 15 are combined in FIG. A block of a gate array that serves as an I / O buffer area for an external interface. Reference numeral E denotes a pad area for external connection.

Here, the standard LSI logic portions 1 'to 8' in FIG. 2 have the same pattern and logic configuration as those already used as the single article LSI, and the performance is also unchanged.

Each of these LSI logic portions 1 'to 8' is standardized by the same design criteria, that is, the length of the gate, the width of the line, the thickness of the gate oxide film, and the like are suitable for the same process parameters. In addition, the portion corresponding to the pad of each conventional LSI and the portion corresponding to the external terminal are small enough to draw the wiring, and the number of existing wiring layers of each of the LSI logic portions 1 'to 8' is The same layer of A1 is used.

The gate array blocks A, B, and C are of different sizes and have the same design criteria as those of the LSI logic portions 1 'to 8'. There are no pads. , C) can be used as the wiring layer for forming a gate or flip-flop to realize a circuit.

The gate array block D is a gate array including the gate array blocks A, B, and C and an I / O buffer portion for interfacing with the LSI logic portions 1 'to 8' or the outside of the LSI.

In the buffer area E, an external connection buffer group is provided. Each of the above functional blocks 1 'to 8' and A to E is arranged as shown in FIG. 2 so that the size of the chip is minimized, and arranged on a single wafer as a common master.

The system engineer using the LSI realizes the glue circuit portion in each of the gate arrays (blocks A to D of the gate arrays) according to the desired system, that is, here, corresponding to the LSI target portion (dotted line) shown in FIG. In addition, the interconnection with the LSI logic portions 1 'to 8' is connected to the A1 wiring region on the first layer (between each LSI logic portion, the first-layer wiring region on the gate array block) and the A1 wiring region on the second layer (the entire chip region). By using the above method, the monolithic LSI of an arbitrary system configuration can be realized at the same level as the conventional printed board design.

As described above, a plurality of LSI blocks and gate arrays (GA) which have already been confirmed to have performance and are subjected to the same design criteria are most appropriately arranged on a single wafer, and these parts are commonly hardwareized as masters. Then, by allowing designers to freely use the A1 wiring layers of the first and second layers, it is possible to provide a semi-custom LSI that can minimize the size of the chip and cope with the differentiation of various systems.

In addition, since only the wiring of A1 is newly generated in the above process, the manufacturing period can be greatly shortened, and the circuit around the LSI can be realized by a gate array, thereby facilitating the reaction to the system.

Incidentally, in the above embodiment, only the gate array is mounted in addition to the standard LSI logic. However, the present invention is not limited thereto, and the gate array and other elements such as a resistance module may be combined.

[Effects of the Invention]

As described above, according to the present invention, a plurality of standard LSI logic parts having already completed logic structures and wiring patterns functioning as single-item LSIs, and design criteria according to the same process conditions as those standard LSI logic parts A mask pattern portion having at least one block of gate array for constituting a peripheral circuit of the standard LSI logic portion, and a wiring area for arbitrarily connecting each terminal of each standard LSI logic portion and each terminal of the gate array; Each arranged so that the size of the chip is minimized; An I / O buffer gate array for an external connection interface is provided to surround each of the above standard LSI logic parts and a gate array, and a lead terminal connection bonding pad portion is provided to surround the I / O buffer gate array. Make the component common hardware as a master; By interconnecting each of the components in a pattern wiring of one layer to a plurality of layers, the microcomputer and its peripheral circuits can be more integrated.

As a result, the system configuration can be simplified and downsized, as well as the price can be realized, and the monolithic semi-custom type system can easily realize any functional circuit configuration by fully utilizing the circuit design technology by the system engineer. LSI can be provided.

Claims (1)

In the monolithic semi-order system LSI, which is composed of several types of macro cells that are wired to correspond to various types of independent LSIs that can form the required system, the already completed logic configuration and wiring pattern The standard LSI logic sections (1 ') have various standard LSI logic sections (1' to 8 ') and design standards adapted to the same process conditions as those standard LSI logic sections (1' to 8 '). Gate arrays (A-C) of at least one block constituting the peripheral circuit of ˜8 '), and each terminal of each of the standard LSI logic portions (1'-8') and each terminal of the gate arrays (A-C). Input and output buffers for the mask pattern portion having a wiring area for arbitrarily connecting each other, and the external connection interface provided to surround each of the standard LSI logic portions 1 'to 8' and the gate arrays A to C. Gate array (D) and the input / output buffer Lead pad connection bonding pads (E), etc., provided to surround the array D, wherein each of the components forms a common hardware configuration as a master, and at least one layer pattern between the components Semi-custom system LSI, characterized in that interconnected by wiring.

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