JPH06101550B2 - Manufacturing method of monolithic semi-custom system LSI - Google Patents

Description

Description: TECHNICAL FIELD OF THE INVENTION The present invention relates to a plurality of types of standard LSI logic units having a completed logic configuration and wiring pattern which function as a single LSI, and peripheral circuits of these standard LSI logic units. The present invention relates to a monolithic semi-custom system LSI having a gate array that constitutes a.

[Technical Background of the Invention and Problems Thereof] In recent years, LSI design technology has been simplified with a gate array as the apex. By using this technique, it became possible for a system engineer to relatively easily perform LSI design, which was conventionally performed only by a semiconductor engineer. As a result, system LSIs have advanced, which has helped to reduce the size, weight, and size of equipment.

Today, the use of microcomputers and their peripheral LSI families has become popular, and at this time, the parts to be integrated into LSIs are miscellaneous circuits called Glue circuits left outside the microcomputers and peripheral LSI families. . This is because the gate array and standard cells cannot accommodate large-scale circuits such as microcomputers and peripheral LSI family circuits. Therefore, at present, when configuring a hardware logic circuit in the most compact form,
[Microcomputer + peripheral family chip + gate array or standard cell] It was only a stop, and it was difficult to achieve further miniaturization and higher integration.

FIG. 3 is a block diagram showing an example of a system configuration according to the conventional LSI technique, in which each of the functional blocks 30 to 69 is constituted by an independent logic circuit element (semiconductor chip). In the figure, 30 is a CPU, 31A and 50A are oscillators (OSC), 3
1B is a clock generator (CG), 32 is a bus controller (BUS-CONT), and 33 and 34 are DMA controllers (DMA-CON).
T), 35, 40, 47, 48, 54 are latch circuits (LATCH), 36 is a timer circuit (TMR), 37 is an interrupt control circuit (PIC), 38, 45 are mask ROM (MROM), 39 is RAM, 41 and 46 are dynamic RAM
(D-RAM), 42 is a D-RAM controller (DRAM-CONT)
Is. 43 and 49 are Glue circuits each composed of a gate array (GA), 43 is a CRT miscellaneous circuit (GA-CRT),
49 is a CPU miscellaneous circuit (GA-CPU). 44 is a CRT controller (CRTC), 50B is a PLL circuit (PLL), 51 is a floppy disk controller (FDC), 52 is a floppy disk interface circuit (FDD-IF), and 53 is a register (RE
G), 55 are video drivers (VIDEO-OUTPUT), 56, 57, 5
8,59,60,63 are drivers (DRV), 61 is a parity generator (PAR-G), 62,64,65,66,67 are drivers / receivers (D / R), 68 is a keyboard / speaker interface circuit ( KB-SPK-SW), 69 is a numerical data processor, P
J1, PJ2, PJ4 to PJ11 are pin junctions of the connector. It should be noted that the symbols of a plurality of digits in parentheses show typical examples of element types.

As described above, conventionally, each of the functional circuits (30 to 69) is composed of independent logic circuit elements (semiconductor chips), so that there is a certain degree of freedom in the circuit design. On the other hand, downsizing of system hardware,
It had the drawback of being difficult to simplify.

[Object of the Invention] The present invention has been made in view of the above circumstances, and further simplifies the system configuration, reduces the size, and further reduces the cost by further increasing the degree of integration of a microcomputer and its peripheral circuits. It is an object of the present invention to provide a monolithic semi-custom system LSI capable of fully utilizing a circuit design technology by an engineer and easily realizing an arbitrary functional circuit configuration.

SUMMARY OF THE INVENTION The present invention relates to a method for manufacturing a monolithic semi-custom system LSI, and a plurality of standard LSI logic units each having a completed logic configuration and wiring pattern capable of functioning as a single LSI, and these standard LSI logic units. The gate array is designed according to the same design criteria as that of the standard LSI logic unit so that at least one block of gate array for forming the peripheral circuit can be manufactured together on the same semiconductor chip. Except for the wiring steps, the standard LSI logic section is completed so that an LSI having an arbitrary function can be completed only by the step of performing the interconnection for connecting the logic section and the gate array and the pattern wiring of the gate array. , And the gate array is 1
A wafer arranged on a chip is prepared, and the wafer is commonly used as a master for performing the wiring process so that a monolithic semi-custom system LSI can be manufactured.

Due to this difference in manufacturing process, existing standard LSI logic that has already been confirmed to have certain performance can be used as it is, and existing circuit design technology by system engineers can be effectively used. Becomes Further, by using the wafer in which the gate array is formed together with the standard LSI logic as a master, it is possible to design and manufacture a desired LSI in a short period of time only by a process such as a wiring process.

[Embodiment of the Invention] An embodiment of the present invention will be described below with reference to the drawings.

1 and 2 are each for explaining one embodiment of the present invention. FIG. 1 is a circuit block diagram and FIG. 2 is a circuit layout diagram (floor diagram).

In FIG. 1, the part surrounded by the broken line is the LS in the present invention.
This is an internal hardware logic that is subject to I conversion, and is composed of a microcomputer peripheral LSI, bus control logic, interface logic, address latch, data driver / receiver, and the like. As a microcomputer peripheral LSI, a clock generator (CG; 828
4 equivalent) 1, bus controller (BUS CONT; 8288 equivalent), DMA controller (DMA; 8237 equivalent) 3, timer circuit (TMR; 8253 equivalent) 4, interrupt control circuit (PIC; 8259 equivalent) 5, CRT controller (CRTC) ; 46505s) 6, bidirectional interface circuit (PPI; 8255 equivalent) 7, floppy disk controller (FDC; 765A equivalent) 8, etc., and address latch circuit (LA
TCH) 9, address buffer (ADRS BUF), data bus driver / receiver (DATA BUF) 11,11 ..., DMA bus / CP
U-bus timing controller (DMA READY / CPU WAIT) 12,
Peripheral LSI / Memory Chip Select Logic (CHIP SEL)
13, DMA interface block (DMA PAGE REG, GATE, L
ATCH) 14, FDC interface (FDC COM REG, FD
C INTERFAC) 15, parity generation test circuit (PG & PC) 1
6, keyboard / speaker interface circuit (KB / S
PK DSW) 17 etc. will be provided.

FIG. 2 is an actual LSI floor diagram for the part to be integrated into LSI shown in FIG. 1, and 1'to 8'corresponding to blocks 1 to 8 shown in FIG. This is a standard LSI logic unit with a defined logical configuration and wiring pattern. A, B, C, and D are gate arrays (GA), A is a gate array block in which the keyboard / speaker interface circuit 17 and the clock frequency dividing circuit in FIG. 1 are incorporated, and B is the above 1
Address latch circuit 9 and address buffer 1 in the figure
0, data bus driver / receiver 11,11, ..., DMA bus / C
The gate array block in which the PU bus timing control unit 12, the peripheral LSI / memory chip select logic 13, the parity generation inspection circuit 16 and the like are incorporated, C is the DMA interface unit 14 and the FDC interface unit 15 in FIG. The gate array block D to be incorporated is a gate array block serving as an I / O buffer area for an external interface. E is a pad (PAD) area for external connection.

Here, the standard LSI logic units 1'to 8'in FIG. 2 have exactly the same patterns and logical functions as those already used as a single LSI, and their performance is unchanged.
Further, each of these LSI logic units 1'-8 'is standardized by the same design standard. That is, the gate length, line width, gate oxide film thickness and the like can be adapted to the same process parameters. Also, conventional individual LS
The portion corresponding to the pad of I and the portion corresponding to the external terminal are made small here so that the wiring can be drawn out. The number of existing wiring layers in each of the LSI logic sections 1'to 8'is the same, and one layer of Al is used.

The gate array blocks A, B, and C have different scales, have the same design criteria as the LSI logic sections 1'to 8 ', and have no pads. In each of the gate array blocks A, B, and C, one layer or two layers of Al can be used as a wiring layer that configures a gate or a flip-flop to realize a circuit.

The gate array block D is a gate array serving as an I / O buffer unit for interfacing with the gate array blocks A, B and C and the LSI logic units 1'-8 'and the outside of the present LSI.

The pad area E is provided with a pad group for external connection.

The above functional blocks (1 'to 8', A to E) are arranged as shown in FIG. 2 so as to minimize the chip size, and are configured as a common master on a single wafer.

A system engineer who uses the above-mentioned LSI, in accordance with a desired system, that is, the SLI target portion (indicated by a broken line) in FIG. ) Part, and interconnects with the LSI logic parts 1'to 8'are connected to the first-layer Al wiring region (between each LSI logic part and the first wiring region of the gate array block) and the second layer. By using the Al wiring area (entire chip area), a monolithic LSI with an arbitrary system configuration can be realized at the same level as the conventional printed circuit board design.

As described above, a plurality of LSI blocks whose functions have already been confirmed and have the same design standard and a gate array (GA) are optimally arranged on a single wafer, and these parts are used as a master for common hardware. Wear it, and further,
By freeing the two-layered Al wiring layer to the designer, it is possible to provide a semi-custom LSI that can minimize the chip size and accommodate various system differences. In addition, since the only new step in the process is the wiring of Al, the manufacturing period is greatly shortened. Moreover, since the circuits around the LSI are realized by the gate array, system compatibility can be facilitated.

In addition, in the above-described embodiment, only the gate array other than the standard LSI logic is mounted. However, it is also possible to combine the gate array with other elements such as a resistance module. .

[Effects of the Invention] As described in detail above, according to the present invention, a plurality of types of standard LSI logic units having a completed logic configuration and wiring pattern that function as a single LSI, and the same standard LSI logic units It has design criteria adapted to process conditions,
A mask pattern having at least one block of a gate array for forming a peripheral circuit of the standard LSI logic section and a wiring area for arbitrarily connecting each terminal of the standard LSI logic section and each terminal of the gate array. And a gate array for an external connection interface for surrounding the standard LSI logic part and the gate array, and further, the input and output buffers are arranged so as to minimize the chip size. A bonding pad portion for connecting lead terminals is provided so as to surround the gate array for use, each component is made into a common hardware as a master, and each component is interconnected by one-layer or multi-layer pattern wiring. As a result, the microcomputer and its peripheral circuits can be highly integrated. , A monolithic semi-custom system LSI that can realize system simplification, downsizing, and cost reduction, and that can easily realize any functional circuit configuration by fully utilizing the circuit design technology by system engineers. Can be provided.

[Brief description of drawings]

FIG. 1 is a block diagram showing a circuit configuration in an embodiment of the present invention, FIG. 2 is a floor diagram showing an arrangement configuration in the above embodiment, and FIG. 3 is a block diagram showing a conventional circuit configuration. is there. 1'to 8 '... Standard LSI logic part, A to D ... Gate array (gate array block), E ... Pad area.

Claims (4)

[Claims] 1. A method for manufacturing a monolithic semi-custom system LSI, comprising: a plurality of standard LSI logic sections each having a completed logic configuration and wiring pattern capable of functioning as a single LSI; and peripheral circuits of these standard LSI logic sections. The gate array is designed according to the same design criteria as the standard LSI logic unit so that at least one block of gate array for configuration can be manufactured together on the same semiconductor chip. Except for those wiring steps, the standard LSI logic section and the gates are formed so that an LSI having an arbitrary function can be completed only by the steps of performing interconnection for connecting the gate arrays and pattern wiring of the gate array. A wafer in which the array is arranged on one chip is prepared, and the wafer is used as a master for performing the wiring process. Use common Te method of a monolithic semi-custom system LSI being characterized in that to be able to produce a monolithic semi-custom system LSI. 2. The method for manufacturing a monolithic semi-custom system LSI according to claim 1, wherein the line width of the gate array is defined by the same design standard as that of the standard LSI logic section. 3. The monolithic according to claim 1, wherein the gate length of the gate array and the film thickness of the gate oxide film are defined by the same design criteria as the standard LSI logic section. Manufacturing method of semi-custom system LSI. 4. A single-layer or multi-layer wiring is used in a wiring process for making interconnection between the standard LSI logic section and a gate array, and a pattern wiring for the gate array. A method of manufacturing a monolithic semi-custom system LSI according to claim 1.