KR900000563B1 - Semi-custom lsi - Google Patents

Abstract

The integrated circuit comprises a number of different types of standard LSI logic sections, each having a predetermined offthe-shelf logic configuration and wiring pattern. A glue circuit functionally couples the standard LSI logic sections, the glue circuit having a mask design standard suitable for the manufacturing process conditions as the manufacturing process conditions of the standard LSI logic sections. A wiring region selectively connects terminals between the standard LSI logic sections and the glue circuit. A bonding pad section surrounds the standard LSI logic sections and the glue circuit for connecting the terminals to lead wires.

Description

Semi-Custom System LSI

1 is a block diagram showing a circuit configuration according to an embodiment of the present invention.

2 is a plan view showing the arrangement of the embodiment of FIG.

3 is a block diagram showing a conventional circuit configuration.

* Explanation of symbols for main parts of the drawings

1: Clock generating circuit 2: Bus control circuit

3: DMA control circuit 4: timer circuit

5: interrupt control circuit 6: CRT control circuit

7 bidirectional interface circuit 8 floppy disk control circuit

9: address latch circuit 10: address buffer

11: data bus drive circuit / receive circuit

12: DAE bus / CPU bus timing controller

13: Peripheral LSI memory chip selection logic circuit

14: DMA interface unit 15: FDC interface unit

16: Parity generation test circuit 17: Keywood speaker interface circuit

18: mask ROM 30-60: each function circuit

1` to 8`: standard LSI logic part `: mask ROM

A to D: Gate array (gate array block)

E: Pad area

The present invention is used to control various types of standard LSI logic parts having a logic structure and wiring pattern which are completed as a single-piece LSI, peripheral circuits of these standard LSI logic parts, and control of these circuits. The present invention relates to a monolithic semi-custom system LSI (LSI) constructed with a mask rom.

In recent years, the LSI design technology has been simplified by using a gate array as a vertex. By using this technique, a system engineer can relatively easily design an LSI design that was conventionally possible only by a semiconductor engineer. It became. As a result, the LSI of the system has been promoted, contributing to the so-called thin and short miniaturization, which makes the device light, thin and small.

Today, the use of microcomputers or their main LSI families prevails, and the object of LSIization is miscellaneous circuits called glue circuits that are left outside the microcomputers or peripheral LSI families. . This is because gate arrays and standard cells do not accommodate large circuits such as microcomputers or peripheral LSI family circuits. Therefore, it is difficult to achieve further miniaturization and high integration in the case of configuring a hardware logic circuit in the most compact form (microcomputer + main surface family chip + gate array or standard cell).

3 is a block diagram showing a configuration example of a system according to the conventional LSI technique, in which each functional block of 30 to 60 is composed of independent logic circuit elements (semiconductor chips).

In this figure, reference numeral 30 is a CPU, 31A and 50A are oscillators (OSCs), 31B is a clock generation circuit (CG), 32 is a bus control circuit (BUS-CONT), 33 and 34 are DMA control circuits (DMA-CONT), 35 and 40, 47, 48 and 54 are latch circuit (LATCH), 36 is timer circuit (TMR), 37 is interrupt controller (PIC), 38 and 45 is mask ROM (MROM), 39 is RAM ( RAM), 41 and 46 are dynamic RAMs (D-RAM), and 42 are dynamic RAM control circuits (DRAM-CONT).

In the drawing, reference numerals 43 and 49 denote a glue circuit composed of a gate array, respectively, 43 denotes a CRT job circuit (GA-CRT), 49 denotes a CPU job circuit (GA-CPU), and reference numeral 44 denotes a CRT control circuit (CRTC). 50B is a PLL circuit (PLL), 51 is a floppy disk control circuit (FDC), 52 is a floppy disk interface circuit (FDD-IF), 53 is a register (REG), 55 is a video drive circuit (VIDEO-OUTPUT) 56 to 60 and 63 are drive circuits (DRV), 61 are parity generation circuits (PAR-G), 68 are key board and speaker interface circuits (KB-SPK-SW), 69 are numerical data processors, PJ1 and PJ2 And PJ4 to PJ11 are pin joint portions of the connector. In the circuit section, the second symbol in parentheses (such as 8088) indicates the type of a typical device.

As described above, since each of the functional circuits 30 to 60 is composed of independent logic circuit elements (semiconductor chips), there has been some freedom in designing a circuit, but it has a drawback in miniaturizing and simplifying system hardware. there was.

The present invention has been invented in view of the above-described circumstances, and as a result, the microcomputer and its peripheral circuits are more integrated, thereby simplifying and minimizing the system configuration, lowering the manufacturing cost, and exhibiting sufficient circuit design technology as a system engineer. The aim is to provide a monolithic-semi-customized system LSI that makes it possible to easily realize any functional circuit configuration.

First, the present invention having the above object will be briefly described as follows.

The present invention has a variety of standard LSI logic parts having a preliminary logic configuration and wiring pattern that functions as a single product LSI, and design standards that adapt to the same process conditions as those standard LSI logic parts. Any functional circuit for the standard LSI logic portion and the gate array having a gate array of at least one block for designing a negative peripheral circuit, and a design criterion adapted to the same process conditions as the standard LSI logic portion and the gate array. A mask pattern for writing a command or data for operating the circuit board and a wiring area for arbitrarily connecting each terminal of the standard LSI logic unit and each terminal of the gate array; In addition, each of the above standard LSI logic sections and a mask-ROM and gate array surround The bonding pad for the self-connection is installed, and each of these components is configured to be common hardware as a master, and the components are interconnected according to the pattern wiring of one layer or multilayer, and the mask ROM is contacted or It is designed to be programmed by ion implantation to realize a highly integrated monolithic-semi-order system LSI.

By constructing the system using the semi-customized system LSI configured as described above, the system configuration can be simplified, miniaturized, and the price can be lowered. Also, the system engineer can fully demonstrate the circuit design technology and have arbitrary functional circuit configuration. The system can also be easily configured.

Hereinafter, an embodiment of the present invention will be described with reference to the accompanying drawings.

1 and 2 are each for explaining an embodiment of the present invention, wherein FIG. 1 is a circuit block diagram, and FIG. 2 is a circuit arrangement diagram (plan view).

In FIG. 1, the dotted line is the internal hardware logic that is the object of LSI in the present invention, and includes the peripheral LSI of the microcomputer, the bus control logic circuit, the interface logic circuit, the address latch circuit, and the data drive / receive circuit. It is composed. As the microcomputer peripheral LSI, a claw generating circuit (CG: 8284) (1), a bus control circuit (BUS-CONT: 8288) (2), a DMA control circuit (DMA: 8237) (3), Timer circuit (TMR: 8253) (4), Interrupt control circuit (PIC: 8259) (5), CRT control circuit (CRTC: 46505S) (6), Bidirectional interface circuit (PPI: 8255) (7), floppy disk control circuit (FDC: 735A) (8), and the like, and address latch circuit (LATCH) 9 and address buffer (ADRS BUF) 10 as peripheral circuits thereof. , Data bus drive circuit / receive circuit (DATA BUF) (11, 11, ...), DMA bus / CPU bus timing controller (DMA READY / CPU WAIT) 12, peripheral LSI memory chip select logic circuit (CHIP SEL) (13), DAE interface section (DMA PAGE REG, GATE, LATCH) (14), FDC interface section (FDC COM REG, FDC INTERFACE) (15), parity generation check circuit (PG & PC) (16), key board Speaker interface circuit (KB, SPK DSW) (17), micro ROM (MROM) (18), etc. It is.

FIG. 2 is an actual LSI floor diagram of the LSI target portion shown in FIG. 1, wherein reference numerals 1 'to 8' correspond to blocks 1 to 8 shown in FIG. It is a standard LSI logic unit with a complete logic configuration and wiring pattern that functions as an LSI.

In the figure, reference numeral 9 'denotes a micro-ROM (MROM) corresponding to the micro-rom 18 of FIG. 1, and is composed of 8 bits x 8K = 64K bits here.

On the other hand, symbols A, B, C, and D denote gate arrays GA, and reference numeral A denotes a combination of the key board and speaker interface circuit 17 and the clock divider circuit shown in FIG. The gate array block is shown, and reference numeral B denotes the address latch circuit 9, the address buffer 10, the data bus drive circuit / receive circuits 11, 11, ..., DMA bus / CPU in FIG. A block of a gate array in which the bus timing controller 12, the peripheral LSI memory chip select logic circuit 13, the parity generation check circuit 16, and the like are combined is indicated. Reference numeral C denotes the DMA interface 14 and the FDC. The interface unit 15 represents a combined gate array block, and reference numeral D denotes a gate array block serving as an I / O buffer area for an external interface. Reference numeral E denotes a pad area for external connection. Here, the standard LSI logic portions 1 'to 8' in FIG. 2 have the same pattern and logic function as those used in the single-piece LSI, and the performance is also different.

Each of the LSI logic portions 1 'to 8' is standardized by the same design criteria, that is, the gate length, the line width, the gate oxide film thickness, and the like can be adapted to the same processor parameter. In addition, the portion corresponding to the pad of the conventional individual LSI and the portion corresponding to the external terminal are small enough to draw the wiring here.

The number of existing wiring layers of each of the LSI logic portions 1 'to 8' is the same, but one layer of AI is used here. The mask rom 9 'also has the same design criteria as the LSI logic portions 1' through 8 ', and the portion corresponding to the conventional pad is also small enough to draw the wiring.

The data pattern of this mask ROM 9 'is determined depending on contact or ion implantation, but the processing is not defined here.

The gate array blocks A, B, and C have the same design criteria as those of the LSI logic portions 1 'to 8' while varying in size, and thus there is no pad. The gate array blocks A, B, and C can use one or two AIs as wiring layers for forming a gate or flip-flop to realize a circuit.

The gate array block D is an I / O buffer for interfacing the gate array blocks A, B, and C with the LSI logic portions 1 'to 8' and the mask ROM 9 'to the outside of the LSI. Negative gate array.

In the buffer area E, an external connection buffer group is provided.

Each of the above functional blocks 1 'to 9' and A to E is wired as shown in FIG. 2 so that the size of the chip is minimized, and arranged on one wafer as a common master.

The system engineer using the above LSI corresponds to the desired system, i.e., in this case, corresponding to the LSI target portion (dotted line) in FIG. 1, the glue circuit portion is used for each of the gate arrays (gate array blocks A to D). Part) or interconnection between the LSI logic portions 1 'to 8' and the mask ROM 9 'to the first layer AI wiring region (between each LSI logic portion and the first layer wiring region of the gate array block). And the second pattern AI wiring area (the whole chip area), and the data pattern of the mask (9`) is programmed again by using a contact or ion implantation method, thereby making it possible to generate an arbitrary level at the same level of the conventional printed circuit board design. A monolithic LSI with a system configuration can be realized.

As described above, a plurality of LSI blocks, mask ROMs, and gate arrays (GAs), each of which has been confirmed and standardized in the same design, are best disposed on one wafer, and these parts are mastered to form common hardware. It is possible to minimize the size of the chip by allowing designers to freely contact or ion-implant the interconnection or gate array and the AI-layers on the first and second layers for the mask ROM. Will be able to provide.

In addition, the only new process in terms of process is AI wiring, which greatly shortens the manufacturing period and makes it possible to easily cope with the system because the circuit around the LSI is realized by the gate array.

On the other hand, since the mask ROM is built in, it is easy to program the system and test the chip.

According to the present invention as described above, having a variety of standard LSI logic part having a logic configuration and wiring pattern that has been completed in order to function as a single-piece LSI, and design standards that adapt to the same process conditions as these standard LSI logic part The standard LSI logic portion and the gate array have a design criteria adapted to the same process conditions as at least one block of the gate array, each standard LSI logic portion and the gate array for configuring the peripheral circuit of the standard LSI logic portion. A mask pattern portion having a mask ROM for writing an instruction or data for operating an arbitrary function circuit, and a wiring area for arbitrarily connecting the terminals of the respective standard LSI logic sections with the terminals of the mask ROM and respective terminals of the gate array; Each of the standard LSI logic sections and gates is disposed in addition to the smallest chip size. Install the gate array for I / O buffer for external interface to surround the ray, and then install bonding pads for lead terminal connection to surround the gate array for I / O buffer, and make each of these components the master to make common hardware. In addition, by interconnecting each of the components in a single-layer or multi-layered pattern wiring, and by configuring the mask ROM to be programmed by contact or ion implantation, the system configuration can be simplified and downsized, so that the manufacturing cost can be realized at low cost. In addition, it is possible to provide a monolithic-semi-order system LSI that allows a system engineer to fully utilize the circuit design technology to easily form a system having an arbitrary functional circuit configuration.

Claims (1)

In the monolithic semi-order system LSI, which is composed of several kinds of macro cells that are wired to correspond to various kinds of independent LSIs, which can form a predetermined required system, the logic configuration and wiring completed in advance At least one block for constituting a peripheral circuit of the standard LSI logic part having various types of standard LSI logic parts (1` to 8`) having patterns and design criteria adapted to the same process conditions as those standard LSI logic parts; The standard LSI logic portion and the gate array are subjected to design criteria adapted to the same process conditions as the gate arrays A to C, the standard LSI logic portions 1 'to 8', and the gate arrays A to C. A mask ROM 9 'capable of writing an instruction or data for operating the arbitrary function circuit, each terminal of each of the standard LSI logic sections 1` to 8`, a terminal of the mask ROM 9`, and Gate array (A A mask pattern portion having a wiring area for arbitrarily connecting each of the terminals of -C), and provided to surround the standard LSI logic portions 1 'to 8', the mask ROM 9 'and the gate array. An input / output buffer gate array (D) for an external connection interface, and a lead pad connection (E) for connecting lead terminals provided to surround the input / output buffer gate array (D) and the like, and each of the components as a master To form common hardware so that each component is not only interconnected by at least one layer of pattern wiring, but also the mask ROM 9 'can be programmed by contact ion implantation. System LSI.

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