JP3359178B2 - Layout method of semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an ASIC (Application Specific IC) manufactured by a silicon compiler.
) And the like.

[0002]

2. Description of the Related Art A silicon compiler device describes an LSI function in a high-level language (different for each logic design CAD), compiles it, converts it into a language equivalent to a machine language, and creates a mask layout for LSI manufacture. Refers to an apparatus that can obtain data (hereinafter, referred to as mask data). That is, the silicon compiler device inputs a logic circuit described in a high-level language as a circuit diagram. Thus, a silicon compiler netlist is generated using the circuit diagram as a database, and various library parameters (circuit layout and the like) are set. Then, in the order of compilation and creation of mask data, processing from logic circuit to arrangement and wiring is performed to generate mask data. Thus, LSI
Is given, the pattern design of the mask data is automatically performed without manual operation.

[0003]

However, the above-mentioned prior art has the following problems. That is, when the function or logic of the semiconductor integrated circuit is changed, the mask layout data must be recreated. In that case, in the wafer process (pre-process), all the mask data in the device isolation process, the device formation process, the wiring process, and the like have to be recreated. Therefore, the design and manufacturing period of the changed semiconductor integrated circuit is lengthened, and the development cost is increased.

[0004]

According to the present invention, there is provided a semiconductor integrated circuit arrangement / wiring method for arranging and wiring each circuit so as to realize a predetermined function on a substrate. A semiconductor integrated circuit produced by using a silicon compiler device to generate layout data and using the mask layout data has the following features. (1) A necessary area for realizing an initial predetermined function is provided. An unused portion which is formed on the same substrate as the substrate on which the required region is formed, and which comprises one or both of a gate array and a functional cell for realizing a function in which the predetermined function is modified in accordance with the required region With an area.

(2) In (1), in the unused area, a basic gate is arranged in one direction, and a wiring channel for connecting the basic gates with each other and the basic gate with a necessary area is arranged in a direction perpendicular to the basic gate. It consists of an arranged channel type gate array. (3) In (1), the unused area is for arranging function cells for realizing a function of a predetermined unit in one direction and connecting the function cells to each other and the function cell to a necessary area in a direction perpendicular to the array. Are arranged. (4) In (1), the unused area comprises a channelless gate array in which basic gates are laid.

[0006]

[Action]

(1) An initial predetermined function of a semiconductor integrated circuit is realized by a necessary area. The required area consists of functional cells,
It is generated in a building block system by a silicon compiler device. The silicon compiler generates all the mask data up to the wiring process in the wafer process. In this case, an unused area including a gate array or a functional cell is formed in addition to the necessary area. This unused area is not connected to the function cell of the necessary area in the initial function specification. Thereafter, when the function is changed for improvement or the like, the function can be changed only by changing the wiring while keeping the structure of the function cell in the necessary area and the structure of the unused area. As a result, the steps before the wiring step are exactly the same as before the function change, and the same mask data can be used. That is, only the mask data of the wiring process needs to be newly created. Further, when the wafer before the wiring step is already manufactured, the wafer can be used for manufacturing the wafer after the function change.

(2) In (1), the structure of the unused area is a channel type gate array, so that the degree of freedom of wiring is large, and a slight change in function can flexibly cope with various changes of contents. be able to. (3) In (1), when the structure of the unused area is a general-purpose function cell, if the future function change can be predicted to some extent, the unused area with a small area can cope with such function change. Can be. (4) In (1), as a result of using a channelless gate array for the structure of the unused area, the spare gate can be stored in the unused area having a small area.

[0008]

Embodiments of the present invention will be described below in detail with reference to the drawings. (First Embodiment) FIG. 1 is a block diagram of a first embodiment of a layout method of a semiconductor integrated circuit according to the present invention. The illustrated circuit includes an unused area 2 in addition to the necessary area 1. The necessary area 1 is composed of a combination of the function cells 11 to 14 and is created by a building block method. Such a building block method is a kind of one that facilitates design in developing an LSI. This is because the already designed blocks are arranged as the function cells 11 to 14, and between the function cells and between the function cells and the bonding pads 1.
0 is connected by wiring.

The unused area 2 is provided in a free area of the necessary area 1. This unused region 2 is formed of a channel type gate array. That is, as shown in FIG.
1 and 22 are arranged in one direction, and a wiring channel 20 capable of connecting basic gates to each other, or between basic gates and functional cells, and between basic gates and bonding pads is provided in a direction perpendicular to this. The minimum scale of the basic gate is a scale that can implement at least one logic such as AND and OR.

Next, the function change of the above-mentioned circuit will be described. It is assumed that after the LSI having the configuration as shown in FIG. 1 is manufactured, it is necessary to change functions and logic. In this case, the cell structure of the necessary area 1 and the gate array structure of the unused area 2 are not changed, and, for example, only the mutual wiring is changed as shown in FIG. Therefore, in the manufacturing process, only the wiring step is different, and the steps immediately before the wiring step are the same as before the change. Therefore, the mask or reticle can be diverted to the one before the change until immediately before the wiring step.
A mask or reticle for the wiring process is manufactured by creating mask data. The mask data is created by using a silicon compiler or by manually arranging and wiring by modifying a part of the existing data. The procedure for creating the mask data in this case is as follows.

In the wafer process, the device isolation process and the device formation process are exactly the same after the change of the logic circuit. Therefore, the mask data in the element separation step and the element formation step can be used. It is assumed that mask data for the wiring process is newly created to satisfy the following conditions. (1) When there is no function cell 11 to 14 in the necessary area 1 to be deleted, all the function cells 11 to 14 are used including the wiring. (2) When there is a function cell in the necessary area 1 to be deleted, the wiring is cut to delete it. (3) When there is a logic circuit to be added, a logic array of an additional portion is created by a functional cell image by applying a multilayer wiring to a gate array composed of basic gates in the unused area 2. Then, the logic circuit of the additional portion and the functional cell in the necessary area 1 are connected by wiring.

As described above, when a change occurs in a part of the logic circuit, only the mask data in the wiring process need be created, and the following advantages are provided. In other words, if the process up to the device separation process and the device formation process in the wafer process is completed and a wafer for which the wiring process has not been completed is prepared, the changed chip is performed by performing the changed wiring process on the wafer. A mounted wafer can be manufactured. Therefore, since a wafer on which a new chip is mounted can be manufactured only by the wiring process, the manufacturing period can be reduced to about one-fifth as compared with the case where the entire wafer process is performed. Further, the wafer for which the wiring process has not been completed can be effectively used without wasting. Further, since the mask data creation and the mask or reticle fabrication need only be performed in the wiring process, the development cost can be reduced to about a quarter as compared with the case of performing the entire wafer process. Further, by using the channel type gate array, the degree of freedom of wiring is increased by the existence of the wiring channel, and it is possible to change the logic of, for example, several hundred to several thousand logic gate levels.

(Second Embodiment) FIG. 3 is a block diagram of a second embodiment of the arrangement and wiring method of a semiconductor integrated circuit according to the present invention. The illustrated circuit includes an unused area 2a in addition to the necessary area 1.
It has. The necessary area 1 is the same as in the first embodiment described above. The unused area 2a is arranged in units of function cells 21a and 22a that can realize a specific logic. In the initial state, the function cells 21a and 2a in the unused area 2a
2a is not wired, but is wired only in the function cells 21a and 22a. The wiring in the function cells 21a and 22a is not shown. Function cell 21 in unused area 2a
The method of arranging a and 22a is a building block system in which various functional cells are arranged in one direction and the wiring channel 20a is arranged in a direction perpendicular to the functional cells. That is, the unused area 2
The function cell configuration of “a” is the same as that of the required area 1.

The procedure of changing the circuit is the same as that of the first embodiment except that the inside of the function cell is already wired, and the other steps are the same. As shown in FIG. 4, in the second embodiment, when there is an additional portion in the logic circuit in the chip, such an additional portion is created by a function cell in the unused area 2a or a combination of each function cell. In this case, since the wiring has already been provided in the function cell, the number of newly added wirings can be reduced as compared with the first embodiment. Therefore, in the second embodiment, in addition to the effects of the first embodiment, the amount of mask data for wiring can be reduced and the mask cost can be further reduced. In addition, if the function cells that are required relatively frequently are known in advance, they are built in predetermined positions in the unnecessary area, and when necessary, they are connected and used to change the circuit in a short time. There is also an effect that it becomes possible.

(Third Embodiment) FIG. 5 is a block diagram of a third embodiment of the arrangement and wiring method of a semiconductor integrated circuit according to the present invention. The illustrated circuit includes an unused area 2b in addition to the necessary area 1.
It has. The necessary area 1 is the same as in the above-described first and second embodiments. The unused area 2b is composed of a channelless gate array. That is, it is a laid-down gate array which is composed of a gate array as in the first embodiment, but has no wiring channel. The procedure for changing the circuit is basically the same as that of the first embodiment, but the use efficiency of the gate array is low because there is no wiring channel. Note that a multilayer wiring can be used.

In the third embodiment, when it can be assumed that the function and logic of the logic circuit are slightly changed, for example, a logic such as inserting two inverters in order to provide a delay circuit in the signal propagation path is used. In the case of a change, as shown in FIG. 6, it is possible to cope with a circuit change without using a wiring channel. Therefore, the same change function can be realized by a highly integrated channelless gate array as compared with the first embodiment, and the unused area 2b can be reduced. It should be noted that the present invention is not limited to the above-described embodiment, and it is needless to say that various modifications are possible. For example, in the above-described embodiment, the unused areas 2, 2
Although a and 2b are constituted by either a gate array or a functional cell, both may be combined.

[0017]

As described above, according to the arrangement and wiring method of a semiconductor integrated circuit of the present invention, an unused area for responding to a slight change in the function of the circuit is created. The effect is as follows. That is, when a change in the function or logic of the semiconductor integrated circuit occurs, it is not necessary to re-create all the mask layout data, and it is possible to cope with it by re-creating only the mask layout data in the wiring process. Therefore, the manufacturing period can be shortened, and most of the development cost can be saved.

[Brief description of the drawings]

FIG. 1 shows a first example of a layout method of a semiconductor integrated circuit according to the present invention.
It is a block diagram of an example.

FIG. 2 is a diagram illustrating a first arrangement and wiring method of a semiconductor integrated circuit according to the present invention;
It is a block diagram after wiring change in an Example.

FIG. 3 is a diagram illustrating a second example of the layout method of the semiconductor integrated circuit according to the present invention;
It is a block diagram of an example.

FIG. 4 is a diagram illustrating a second example of the layout method of the semiconductor integrated circuit according to the present invention;
It is a block diagram after wiring change in an Example.

FIG. 5 is a diagram illustrating a third example of the layout method of the semiconductor integrated circuit according to the present invention;
It is a block diagram of an example.

FIG. 6 is a diagram illustrating a third example of the layout method of the semiconductor integrated circuit according to the present invention;
It is a block diagram after wiring change in an Example.

[Explanation of symbols]

 1 Required area 2, 2a, 2b Unused area

Claims (4)

(57) [Claims] 1. A silicon compiler device generates mask layout data for arranging and wiring each circuit so as to realize a predetermined function on a substrate, and the semiconductor integrated circuit manufactured using the mask layout data. A required area for realizing an initial predetermined function, and a gate formed on the same substrate as the substrate on which the required area is formed, and for realizing a function obtained by modifying the predetermined function together with the required area An arrangement and wiring method for a semiconductor integrated circuit, comprising: an unused area comprising one or both of an array and a functional cell. 2. The unused area is a channel type in which basic gates are arranged in one direction, and wiring channels for connecting the basic gates to each other and connecting the basic gates to the required area are arranged in a direction perpendicular to the basic gates. 2. The layout method according to claim 1, wherein the layout method comprises a gate array. 3. The unused area for arranging function cells for realizing a function of a predetermined unit in one direction and connecting the function cells to each other and the function cell to the necessary area in a direction perpendicular to the array. 2. The method according to claim 1, wherein wiring channels are arranged. 4. The layout method according to claim 1, wherein said unused area comprises a channelless gate array in which basic gates are laid.