JPS6182443A - Monolithic semicuston system lsi - Google Patents

Abstract

PURPOSE:To simplify a system configuration and to reduce the size by mutually connecting by one layer or multilayer pattern wirings between constituents, and programming a mask ROM in contact, thereby integrating a microcomputer and its peripheral circuit. CONSTITUTION:A monolithic LSI of an arbitrary system configuration is formed in the same level as the conventional printed board design by forming glue circuit corresponding to an LSI object in gate array portions, connecting LSI logics 1'-8' and a mask ROM9' by using the first layer aluminum wiring region and the second layer aluminum wiring region, and further programming the data pattern of the ROM9' by contacts or ion implantation. Since newly generated step is only aluminum wirings, the manufacturing period can be largely reduced. Thus, the system configuration can be simplified, reduced in size and cost.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a plurality of types of standard LSI logic sections having already completed logic configurations and wiring patterns that function as a single LSI, and a gate array constituting its peripheral circuit. The present invention relates to a monolithic semi-custom system LSI comprising: and a mask ROM used for controlling these circuits.

[Technical background of the invention and its problems 1 In recent years, LSI design technology has focused on gate arrays.
Simplification is progressing with ray) at the top. By using this technique, system engineers can now relatively easily carry out LSI design, which was previously done only by semiconductor engineers. As a result, systems have become increasingly integrated into LSIs, which has helped make devices lighter, thinner, and smaller.

Today, the use of microcomputers and their peripheral LSI families has become popular, and at this time, the parts targeted for LSI conversion are miscellaneous circuits called glue circuits that have been left outside of microcomputers and peripheral LSIs of 77 mm. . This is because gate arrays and standard cells cannot accommodate large-scale circuits such as microcomputers and peripheral LSI 77mm circuits. Therefore,
Currently, when configuring a hardware logic circuit in the most compact form, it is limited to a 7mm chip + gate array or standard cell (microcomputer peripherals), and it is difficult to achieve further miniaturization and higher integration. there were.

FIG. 3 is a block diagram showing an example of a system configuration using the conventional LSI technique, in which each of 30 to 69 functional blocks is composed of independent logic circuit elements (semiconductor chips). In the figure, 30 is the CPU, 31A, soA
is an oscillator (O20), 31B is a clock generator (CG
), 32 is a bus controller (Bus-CONT),
33.34 is the DMA controller (DMA-CONT)
), 35.40.47.48.54 is the latch circuit (L
ATCH), 36 is a timer circuit (TMR), 37 is an interrupt control circuit (PIC), 38°454; tv mask OM
(MROM), 39 is a RAM, 41.degree. 46 is a dynamic RAM (D-RAM), and 42 is a D-RAM controller (DRAM-CONT). 43.49
are each composed of a gate array (GA)
tle circuit, and 43 is a CRT9 circuit (GA-CR
T>, 49 is a CPU miscellaneous circuit (GA-CPU). 4
4 is CRT controller (CRTC), 50B is PLL
circuit (PLL), 51 is a floppy disk controller (FCC), 52 is a floppy disk interface circuit (FDD-IF), and 53 is a register (REG).
), 55 is the video 'r'5 driver (V IDEO-OUT
PUT), 56°57, 58.59.60.63 is the driver (DRV), 61 is the parity generator (PA
62.64° 65, 66, 67 are driver/receivers (D/R), 68 are keyboard/speaker interface circuits (KB-8PK-8W), 69
are numerical data processors, PJI, PJ2, PJ4
~PJ11 is a pin junction of the connector. Note that the multi-digit symbol in parentheses indicates an example of a typical element format.

In this way, conventionally, each of the above functional circuits (30 to 69)
Since each of the circuits is composed of independent logic circuit elements (semiconductor chips), it has a certain degree of freedom in circuit design, but has the disadvantage that it is difficult to downsize and simplify the system hardware. Ta.

[Object of the Invention] The present invention has been made in view of the above-mentioned circumstances, and it is an object of the present invention to increase the integration of a microcomputer and its peripheral circuits, thereby simplifying the system configuration, downsizing it, and lowering its cost. It is an object of the present invention to provide a monolithic semi-custom system LSI that allows engineers to fully utilize their circuit design techniques and easily realizes arbitrary functional circuit configurations.

[Summary of the Invention] The present invention provides a plurality of types of standard LSI logic parts having already completed logic configurations and wiring patterns that function as a single LSI, and design standards adapted to the same process conditions as these standard LSI logic parts. and at least one block of gate array for forming a peripheral circuit of the standard LSI logic section, and a design standard adapted to the same process conditions as the standard LSI logic section and the gate array, and the standard LSI logic section and A mask ROM in which commands or data for operating arbitrary functional circuits of the gate array are written, and a wiring area for arbitrarily connecting each terminal of each standard LSI logic section and each terminal of the gate array. mask pattern portions having the same characteristics as those shown in FIG. , each of these components is configured to form common hardware as a mask, and each of the components is interconnected by one-layer to multi-layer pattern wiring, and the mask ROM is programmed by contact or ion implantation, etc. As a configuration, a highly integrated monolithic semi-custom system LSI is realized.

By configuring a system using a semi-custom system LSI with such a configuration, the system configuration can be simplified, made smaller, and even lower in price. A system with a functional circuit configuration can be easily constructed.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings.

1 and 2 are for explaining one embodiment of the present invention, respectively. FIG. 1 is a circuit block diagram and FIG. 2 is a circuit layout diagram (floor diagram).

In FIG. 1, the part surrounded by a broken line is L in the present invention.
Internal hardware logic that is subject to SI,
It consists of a microcomputer peripheral LSI, bus control logic, interface logic, address latch, data driver/receiver, etc. As a microcomputer peripheral LSI, a clock generator (C
-G: 8284 equivalent) 1, Bus controller (Bus
C0NT: 8288 equivalent) 2, DMA controller (DMA; 8237 equivalent) 3, timer circuit (
TMR: 8253 equivalent) 4. Interrupt control circuit (PI
C; 8259 equivalent) 5. CRT controller (CRT
C; 46505s equivalent) 6, bidirectional interface circuit (PPI: 8255 equivalent) 7, floppy disk controller (FDC near 65A equivalent) 8, etc., and as peripheral circuits, an address latch circuit (L
ATCH) 9, address buffer (ADR8BUF),
Data bus driver/receiver (DATA BUF>
11゜11..., DMA bus/CPU bus timing control section (DMA READY-CPtJ WAI
T) 12, Peripheral LSI/Memory chip select logic (CHIP 5EL) 13, DMA interface section (DMA PAGE REG, GATE, LAT
CH) 14, FDC interface section (FDCCOM
R'EG, FDCINTERFACE) 15, parity generation check circuit (PG&PC) 1B, keyboard/speaker interface circuit (KB/SPK DSW)
) 17, a mask ROM (MROM) 18, etc. are provided.

FIG. 2 is an actual LSI floor diagram for the part to be converted into LSI shown in FIG. 1 above, and 1' to 8' correspond to blocks 1 to 8 shown in FIG. This is a standard LSI logic section with a logical configuration and wiring pattern.

Reference numeral 9' designates a mask ROM (MROM) corresponding to the mask ROM 18 in FIG.

A, B, C, and D are gate arrays (GA), A is a gate array block in which the keyboard/speaker interface circuit 17 and the clock frequency dividing circuit shown in FIG. Address latch circuit 9, address buffer 10, data bus driver/receiver ii, ii, . . . , DMA bus/CPU bus timing control unit 12, peripheral LSI/memory chip select logic 13, and parity generation check in FIG. C is a gate array block in which the circuit 16 etc. are incorporated, C is a gate array block in which the DMA interface section 14 and FDCDM interface section in FIG. 1 is incorporated, and D is I1 for external interface.
0 buff? This is a gate array block that serves as an area.

E is a pad (PAD) area for external connection.

Here, the standard LSI logic section 1' in FIG.
LSIs 8' to 8' have exactly the same pattern and logic functions as those already used as single LSIs, and their performance remains unchanged. Further, each of these LSI logic sections 1' to 8' is standardized according to the same design standard. That is, the gate length, line width, gate oxide film thickness, etc. can be adapted to the same process parameters. Further, the portions corresponding to pads of each conventional LSI and the portions corresponding to external terminals are made small enough to allow wiring to be drawn out. Furthermore, the number of wiring layers in each of the LSI0979 sections 1' to 8' is the same, and one A4 layer is used.

In addition, the mask ROM 9' is also connected to each of the LSI logic sections 1' to 1'.
It has the same design standards as 8', and the portion corresponding to the conventional pad is also small enough to allow wiring to be drawn out.

The data pattern of this mask ROM 9' is determined by contact or ion implantation, but this process has not yet been performed here.

Further, gate array blocks A, B, and C have different scales, have the same design standards as the LSI logic sections 1' to 8', and have no pads. These gate array blocks A, B, and C are one-layer and two-layer wiring layers that form gates and flip-flops to realize circuits.
can be used.

Gate array block D is a gate array that serves as an I10 buffer section for interfacing with the gate array blocks A, B, and C, LSI logic sections 1' to 8', mask ROM 9', and the outside of this LSI.

Further, pad area E is provided with a group of pads for external connection.

The above functional blocks (1' to 9', A to E) are arranged as shown in Fig. 2 so that the chip size is minimized,
A common mask is formed on one wafer.

A system engineer who uses the above-mentioned LSI configures the GIUe circuit section according to the desired system, that is, the LSI target part in FIG. ), and also,
Interconnection with LSI logic parts 1' to 8' and mask ROM 9' is made to the first layer 2 wiring area (between each LSI logic part, first layer wiring area of gate array block),
By using the second layer A2 wiring area (the entire chip area) and programming the data pattern of the mask ROM 9' using contact or ion implantation, you can configure any system at the same level as conventional printed circuit board design. A monolithic LSI can be realized.

As mentioned above, multiple LSI blocks whose performance has already been confirmed and the same design standard and mask R
The OM and gate array (GA) are optimally arranged on one wafer, and these parts are used as a mask to create common hardware, and for mutual wiring and gate array, one or two layers of A2 wiring, or For mask ROM, by freeing the designer to perform contact or ion implantation, it is possible to minimize the chip size and provide a semi-custom LSI that can accommodate differences in various systems. Further, since only 82 wiring steps are newly generated in the process, the manufacturing period is significantly shortened. Also, L
Since the circuit around the SI is implemented with a gate array, it can be easily adapted to the system.

Furthermore, since it has a built-in mask ROM, programming corresponding to the system or program testing of this chip is easily possible.

[Effects of the Invention] As described in detail above, according to the present invention, a plurality of types of standard LSI logic sections having already completed logic configurations and wiring patterns that function as a single LSI, and these standard LSI logic sections are provided.
At least one block of gate array for configuring the peripheral circuit of the standard LSI logic section, which has a design standard adapted to the same process conditions as the I logic section, and the same process conditions as the standard LSI logic section and the gate array. a mask ROM that has design standards adapted to the standard LSI logic section and gate array and writes commands or data for operating any entertainment circuit thereof;
Each of the standard LSI logic sections, the mask ROM, and the mask pattern section having a wiring area for arbitrarily connecting each terminal of the gate array are arranged so that the chip size is minimized, and each of the standard LSI
A gate array for an input/output buffer for an external connection interface is provided so as to surround the logic section and the gate array, and a bonding pad section for connecting lead terminals is further provided to surround the gate array for the input/output buffer. , each of these components is made into common hardware as a mask, each of the components is interconnected by one-layer to multi-layer pattern wiring, and the mask ROM is programmed by contact or ion implantation. We provide a monolithic semi-custom system LSI that not only simplifies, downsizes, and lowers the price of the system configuration, but also makes it possible to easily build a system with any functional circuit configuration by fully utilizing the circuit design skills of system engineers. can.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the circuit configuration in one embodiment of the present invention, FIG. 2 is a floor diagram showing the arrangement in the above embodiment, and FIG. 3 is a block diagram showing the conventional circuit configuration. be. 1' to 8'...a quasi-Ls10 thick portion, 9'...mask ROM, A-D...gate array (gate array block), E...pad area.

Claims (1)

[Claims] In order to configure peripheral circuits of the standard LSI logic section, having multiple types of standard LSI logic sections having already completed logic configurations and wiring patterns, and design criteria adapted to the same process conditions as these standard LSI logic sections. at least one block of gate arrays of the standard L
A mask RO that has design standards adapted to the same process conditions as the SI logic section and gate array, and can write commands or data to operate any functional circuit in the standard LSI logic section and gate array.
M, a mask pattern section having a wiring area for arbitrarily connecting terminals of each of the standard LSI logic sections, the mask ROM, and the gate array, and each of the standard LSI
A gate array for an input/output buffer for an external connection interface provided surrounding the logic section, mask ROM, and gate array, and a lead terminal connection provided surrounding the gate array for the input/output buffer. a bonding pad portion, each of the components has a common hardware configuration as a master, each of the components is interconnected by at least one layer of pattern wiring, and the mask ROM has a contact or ion bonding pad portion. Monolithic semi-custom system LSI that can be programmed by implantation.