JPH04219045A - Large scale integrated circuit device and emulator for large scale integrated circuited circuit device - Google Patents

Abstract

PURPOSE:To attain miniaturization and high circuit integration and to implement high speed processing by integrating a DSP core section, a core for a central processing unit and a logic circuit to one chip. CONSTITUTION:Minute processing of an LSI component is improved by the improvement of the recent process technology in an LSI and even when a control section of a facsimile equipment and a digital signal processing section of a MODEM are realized by one DSP chip, the program has still a margin. Then a MODEM function 9 is added to conventional control sections 4-8 of the LSI provided to, e.g. the facsimile equipment in a form of DSP + software and they are all integrated in one chip IC. Thus, the effect of a signal delay or noise due to a connection lead is avoided, the arithmetic processing speed is improved and the entire size of the device is made small.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to a large-scale integrated circuit device (hereinafter referred to as LSI) that requires high-speed, high-precision control and can be used, for example, in a facsimile machine.
The present invention relates to an emulator device.

0002

[Background Art and its Problems] Conventionally, LSIs used in facsimile machines, for example, have been known to handle digital signals.
Due to limitations in the processing power and chip size of a processor (hereinafter referred to as DSP), a control section that controls a facsimile machine and a DSP that performs other controls have been configured as separate chips. However, recent improvements in process technology in LSI have led to miniaturization of LSI components and improved DSP performance, and the digital signal processing section of the modem (hereinafter referred to as modem) in the facsimile machine as well as the control section of the facsimile machine have been integrated into a DSP chip. Even if this is achieved, there is still room in the program. Therefore, the present invention provides an LS that is included in a facsimile machine, for example.
The first objective is to provide an LSI in which a modem function is added to the conventional control unit in the form of DSP + software, and all of these functions are integrated into one chip.

[0003] Furthermore, when designing an LSI as described above, a DSP, a program memory for storing a control program for the DSP, etc., a breadboard of the entire LSI chip is assembled and the breadboard is assembled as shown in FIG. DSP processor part 21 excluding the program memory mentioned above
The emulator 101 and the breadboard were connected by a conductive wire. Note that the emulator 101 is configured as follows. Processor part 2 consisting of DSP etc.
1 is connected to an address bus 24 and a data bus 25 for reading and writing data, and a RAM 22 is connected to the address bus 24 and data bus 25. However, since the breadboard and the emulator 101 are connected by a conductive wire, as the calculation speed of the DSP increases, problems such as signal transmission delay and the influence of noise in the conductive wire portion become problems. Furthermore, as mentioned above, since an emulator has been constructed for the conventional processor section 21, the core section of the processor corresponding to the DSP section is common.
When developing multiple types of LSIs with different other components, that is, when the program memory configurations are different, it is necessary to develop breadboards or emulators dedicated to each product, which requires time and effort. There is a problem that it takes a lot of time and the cost required for it is also high.

[0004]In order to solve the above-mentioned problems regarding emulators, the following IC packages have been proposed. As shown in FIG. 6, on the four sides of the IC package 102 in which the LSI chip is molded,
Connection terminals for connecting the IC package 102 and an external device are provided in two protruding rows in upper and lower stages. The connection terminals arranged on the upper side of the diagram are molded L
This is the variation pin 103, which is a connection terminal for connecting to an emulator for controlling the operation of the SI, and the connection terminals arranged at the bottom are connected to other components in order to operate the LSI as a product. This is a product pin 104 which is a connection terminal. By standardizing the arrangement of the variation pins 103 in this way, it is possible to connect the IC package 102 directly to a breadboard without using conductive wires, eliminating the negative influence of conductive wires, and also LS with common core
For an IC package containing I, the development of an emulator main body for testing the operation of the LSI included in the IC package 102 is done only once, thereby saving the effort of developing the emulator.

However, by standardizing the arrangement of the variation pins 103, unnecessary variation pins 103 must be provided in certain types of ICs, which causes the problem of increasing the size of the IC package 102. The present invention has been made to solve these problems, and a second object is to provide an LSI emulator device that is free from signal delays and noise effects and is easy to develop.

[0006]

[Means for Solving the Problems and Their Effects] The present invention provides a DSP core section that realizes a modulation/demodulation function using digital signal information with other devices using a dedicated processor and software, and a signal executed by the DSP core section. Using the processing results,
It is characterized by having a central processing unit core and a logic circuit section on one chip, which realize data encoding and decoding functions or device control functions.

With this configuration, the DSP core section improves the arithmetic processing speed of the device as a whole by executing digital signal processing that the central processing unit core and logic circuit section are not good at. do. Furthermore, the DSP core section encodes and decodes input and output data using software, thereby reducing the hardware that constitutes the encoder/decoder and reducing the overall size of the device. Further, the DSP core section functions to be able to achieve various transmission speeds by changing the program stored in the built-in program memory.

Further, the present invention provides an emulator device for a large-scale integrated circuit device having a built-in processor cell.
The present invention is characterized by comprising a processor emulator and a large-scale programmable logic integrated circuit that stores a program for operating the processor.

[0009] With this configuration, the large-scale programmable logic integrated circuit is provided in the same device as the processor, and there is no need to connect the processor and the programmable logic integrated circuit with conductive wires as in the past, which reduces noise and other noise. Acts to prevent negative effects.

Further, the present invention provides an emulator device for a large-scale integrated circuit device having a built-in processor cell.
A processor emulator, a large-scale programmable logic integrated circuit that stores a program for operating the processor, and a switching unit that connects a control device provided outside the device to either the processor or the programmable logic integrated circuit. It is characterized by:

With this configuration, the operations of the processor and the programmable logic integrated circuit can be controlled by one control device.

0012

DESCRIPTION OF THE PREFERRED EMBODIMENTS An LSI showing an embodiment of the present invention shown in FIGS. 1 and 2 is used, for example, in a facsimile machine. As shown in FIG. 1, a data bus 2 provided within the DSP 1
, the address bus 3 includes a CPU core 4 that performs arithmetic processing on signals composed of 8 to 32 bits;
3, an encoder/decoder 5 that encodes and decodes signals transmitted within the 3, another control logic section 6, a CPU program memory 7 in which programs for CPU operation are stored, and a CPU.
A DSP that realizes the CPU data memory 8 for storing data processed by the CPU, and the program memory and modem functions of the CPU, and is provided with the components shown in FIG.
The core parts 9 are connected to each other.

The DSP core section 9 has an I/O port 1 connected to a data bus 2 and an address bus 3 in the DSP 1.
0, an address bus 11 for transmitting addresses related to the data area, a data bus 12 for transmitting data, an address bus 13 for transmitting addresses related to the program area, a data bus 14 for transmitting data, a data area address bus 11 and a data area data bus a data memory 15 connected to the data area data bus 12; a program memory 16 connected to the program area address bus 13 and the program area data bus 14;
High-speed processing of product-sum calculations for transmitted digital signals.
A calculation unit 17 composed of MPY, ALU, ACC, etc.
A pointer is a register for specifying the address of data supplied to the data memory 15, and an instruction decoder decodes DSP instructions and sends control signals written in the instructions to the data memory 15, calculation unit 17, etc. (in the figure) A clock generator (hereinafter referred to as IDEC) that generates a timing clock used within the DSP core 9 is provided. Incidentally, the DSP core 9 having such a configuration is a general-purpose DSP core 9.
Configure SP by making it into cells. Therefore, once the operation of the DSP has been confirmed as a standalone DSP can be used as a functional cell, D
The LSI can be configured in a state where the operation of the SP core section has been evaluated once, increasing the probability that the LSI will operate normally after completion.

The operation of the present LSI configured in this manner will be explained below. When executing a facsimile function that converts information such as characters written on a document to be transmitted into a digital signal and performs digital signal calculation processing, the CPU core 4 performs general control of signal processing, and signal processing such as encoding and decoding. Signal processing is performed in a CPU program memory 7, a CPU data memory 8, and the like. On the other hand, digital signal processing during transmission and reception with the modem is realized by the DSP core 9, including software.

In this way, the CPU core 4 and the DSP core 9
each runs on a separate program, and the CPU core 4
Since the DSP core 9 processes analog signals and the DSP core 9 processes digital signals, signal processing can be performed at high speed. Furthermore, the functions of the CPU core 4 and DSP core 9 can be easily changed by changing the programs.

Furthermore, although the encoder/decoder in FIG. 1 is formed by hardware, as mentioned above, with the improvement in the processing ability of the DSP, the encoder/decoder can be executed by the software of the DSP. Also, if configured like this,
There is no reduction in arithmetic processing speed, and since there is no need to form an encoder/decoder, the amount of hardware for the entire device can be reduced, contributing to miniaturization and high integration of ICs.

Furthermore, as shown in FIG.
is equipped with a program memory 16 that stores programs for operating the DSP core 9, and by changing the programs stored therein, modem functions of various transmission speeds can be realized with the same hardware. When an integrated circuit becomes as shown in FIG. 1, the internal circuit scale reaches several hundreds of thousands of transistors, and changing the hardware requires extremely large risks and time. Therefore, by providing the program memory 16 as shown in this embodiment, these risks are reduced and several types of integrated circuits can be developed in series.

Next, an emulator device suitable for LSI design will be described below. In FIG. 3, the same components as those shown in FIG. 5 are designated by the same reference numerals. The variation chip section 20 constituting the emulator device according to this embodiment includes a processor section 2 such as a DSP.
1, has a RAM 22 and a large-scale programmable logic array 23, a processor section 21 such as a DSP, and a RA
M22 are both connected to the address bus 24 and data bus 25 for the processor, and are also connected to the processor section 21.
is connected to a large-scale programmable logic array 23, and the programmable logic array 23 is connected to an address bus 26 and a data bus 27 for writing data in the programmable logic array. In addition, devices with multiple elements on one chip (hereinafter referred to as AS
An output terminal 28 corresponding to the external pins of the ASIC is provided to facilitate debugging of a target system using an ASIC. The sides are connected.

In this way, the variation chip part 2
By configuring 0, the large-scale programmable logic array 23, which was conventionally provided on the breadboard side, is provided within the variation chip section 20, and the configuration uses an address bus 26 and a data bus 27 to supply signals. This allows the variation to be easily performed from outside the variation chip portion 20.

Therefore, conventionally, each time the configuration of a programmable logic array differs, the programmable
Although it was necessary to manufacture a breadboard having a logic array, such a labor can be omitted with the emulator having the present variation chip section 20. Furthermore, if the logic is comparable to that which can be realized by programmable logic, it is not limited by the pin arrangement of ASIC products, and can contribute to the degree of freedom in product development and the reduction of chip costs.

[0021] Also, compared to the conventional method of making a breadboard using multiple logic ICs or debugging using an emulator for a single processor, it is more compact and can save on the number and length of wires. Therefore, problems such as the signal transmission delay and noise described above can be eliminated.

In the emulator device having the variation chip portion 20 shown in FIG. 3, a host computer for driving a processor and a programmable logic
Although two host computers are required, including a host computer for configuring the array 23, since the configuration of the programmable logic array 23 can be performed at the start of emulation operation, only one host computer is sufficient. FIG. 4 shows the configuration of an emulator device operated by one host computer in this manner. Note that the same components as in FIG. 3 are designated by the same reference numerals, and their explanations will be omitted.

The variation chip portion 20 has an address bus 2 for the programmable logic array 23.
RAM 22 (referred to as program memory in FIG. 4) is connected to multiplexer 29 via 6 and data bus 27, and is also connected to variation chip section 20.
is connected to a multiplexer 29 via a processor address bus 24 and a data bus 25. The input side of multiplexer 29 is connected to a host computer (not shown) via a bus. The above program memory is RA
M, PROM, etc. may be used. Further, the multiplexer 29 may be configured with a port IC.

Emulator device 3 configured as described above
The operation of 0 will be explained below. First, multiplexer 29
The variation chip part is 20 programmable
It is connected to the logic array 23 side, and the host computer and the programmable logic array 23 are connected. Then, the programmable logic array 23 is configured in the host computer to support emulation operation.

Next, the multiplexer 29 is switched to the RAM 22 side, and the host computer and the processor section 21 of the variation chip section 20 are connected via the RAM 22.
Connect with. Thereafter, the host computer controls predetermined emulation operations on the processor section 21.

[0026] In such an emulator device 30, only one host computer is required, and the device configuration can be simplified.
When 0 is integrated into one chip, it can be incorporated into a circuit board in a host computer, and the device configuration can be further simplified.

Note that the processor section 21 in the variation chip section 20 described above includes a DSP and a CPU.
It can be configured to include one or more of the following.

[0028]

[Effects of the Invention] As detailed above, according to the present invention, D
Since the SP core section, the central processing unit core, and the logic circuit section each operate according to separate programs, each can perform signal processing that they are good at, and can perform high-speed processing. Furthermore, since the DSP core section uses software to perform signal processing that was previously processed by hardware, the amount of hardware in the entire device is reduced, making it possible to downsize and highly integrate the device. Furthermore, since the DSP core section is equipped with a program memory, by changing the program stored in the memory, it is possible to form an integrated circuit compatible with a plurality of types of devices. Furthermore, according to the present invention, since the programmable logic array, which was conventionally provided on the breadboard side, is provided integrally with the variation chip part, it is possible to eliminate the conductor wires that used to connect the emulator device and the breadboard. , can eliminate the effects of signal transmission delay and noise,
In addition, programmable logic can be implemented on the emulator device side.
Since the array configuration can be changed, the emulator device can be easily developed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of an LSI according to the present invention.

FIG. 2 is a block diagram showing an example of the configuration of the DSP core shown in FIG. 1.

FIG. 3 is a block diagram showing the configuration of an variation chip portion used in the LSI emulator device of the present invention.

4 is a block diagram showing the configuration of an emulator device including the variation chip portion shown in FIG. 3. FIG.

FIG. 5 is a block diagram showing the configuration of a conventional emulator device.

FIG. 6 is a perspective view showing an IC chip provided with variation pins.

[Explanation of symbols]

4...CPU core, 9...DSP core, 16...program memory.

Claims (6)

[Claims] Claim 1: A DSP core unit that realizes modulation and demodulation functions based on digital signal information with other devices using a dedicated processor and software, and data encoding, using the signal processing results executed by the DSP core unit. 1. A large-scale integrated circuit device comprising a central processing unit core and a logic circuit unit that realize decoding or device control functions on one chip. 2. The large-scale integrated circuit device according to claim 1, wherein the DSP core section encodes and decodes data using software. 3. The DSP core section has two types of buses for transmitting addresses and data related to the data area and the program area, and a program connected to each of the buses and related to the operation of the DSP core section. 2. The large-scale integrated circuit device according to claim 1, further comprising a memory for storing data, and an arithmetic unit connected to a data-related bus for performing arithmetic processing on digital signals. 4. An emulator device for a large-scale integrated circuit device having a built-in processor cell, characterized by comprising a processor emulator and a large-scale programmable logic integrated circuit that stores a program for operating the processor. Emulator device for large-scale integrated circuit devices. [Claim 5] The emulator device according to claim 4 is one
An emulator device for large-scale integrated circuit devices made into chips. 6. An emulator device for a large-scale integrated circuit device having a built-in processor cell, comprising: a processor emulator; a large-scale programmable logic integrated circuit that stores a program for operating the processor;
An emulator device for a large-scale integrated circuit device, comprising: a switching unit for connecting a control device provided outside the device to either the processor or the programmable logic integrated circuit.