JP2634423B2 - Microcomputer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a microcomputer as an evaluation chip used for software debugging such as emulation and system evaluation, and a microcomputer as an actual chip to be subjected to proxy control by the evaluation chip. For example, for ASIC (application-specific
The present invention relates to a technology that is effective when applied to the maintenance of a software debugging system for various microcomputers deployed in an integrated circuit (IC) system.

(Prior art)

In the development of microcomputer application equipment (hereinafter also simply referred to as target system), a system development tool (system development support device) such as an emulator for system debugging and system evaluation includes a console including the system development device and a target system. And a function as a debugger, that is, a system development support device, while substituting the functions of the microcomputer (target microcomputer) included in the target system.

To perform software debugging of the target system with system development tools, it is basically possible to inform the debugger of the control state while acting on behalf of the target microcomputer, or to change the control state by arbitrarily changing the program flow. An evaluation chip for emulation or the like having such a function is used.

This evaluation chip is required to have at least a control function equivalent to that of the target microcomputer on behalf of the target microcomputer, so that the evaluation chip includes not only the configuration of the central processing unit but also the peripheral functions. The circuit configuration or function is determined for each type.

As described above, as a method of obtaining an evaluation chip whose circuit configuration and function are particularly determined in response to the function of the target microcomputer, a circuit of the target microcomputer as a real chip to be subjected to proxy control is used as a core. A method of newly adding a signal input / output function necessary for emulation or the like and logic for controlling the signal input / output function can be adopted. Such a method of diverting the actual chip reduces the number of development steps of the evaluation chip and also reduces the difference in electrical characteristics between the evaluation chip and the actual chip to some extent.

In addition, from the viewpoint of general applicability to system development tools, in order to standardize system development tools, the evaluation chip package is shared with actual chips that have different external terminal arrangement configurations and different peripheral functions. can do.

Examples of documents describing the emulator include “LSI Handbook” P562 to P563 published by Ohmsha on November 30, 1984.

[Problems to be solved by the invention]

However, the technology of simply forming an evaluation chip by diverting an actual chip is not sufficient in terms of improving the easiness of obtaining an evaluation chip and improving its reliability. Just to make the system fully compatible with system development tools for individual evaluation chips corresponding to various types of microcomputers developed with ASICs or various types of microcomputers with peripheral functions changed around the same central processing unit. Can not get to. In this sense, the present inventor has clarified that the software debugging system of the microcomputer system cannot be easily and reliably arranged to obtain general versatility only with the prior art.

For example, in the case of configuring individual evaluation chips corresponding to various types of microcomputers developed in a variety of types or ASICs in which peripheral functions are changed around the same central processing unit, using actual chips and sharing a package. ,
If you want to use a specific system development tool for multiple types of evaluation chips without changing the hardware of the system development tool and add a debugging program to the general purpose, you need to use a different type of evaluation chip. The emulator can be made to select additional parts of the software program. For this purpose, it is necessary for the emulator to recognize the type of the real chip corresponding to the evaluation chip. As a means for this, the real chip function possessed by the evaluation chip is controlled by the control register and status of the peripheral I / O module. It is possible to adopt a method of identifying by the initial value of the register or the like. However, in such a convenient method, the identification method becomes inconsistent with respect to various changes of peripheral functions, and the identification method of the function corresponding to the actual chip is different from each other, and the procedure for that is shared. Can no longer be
To avoid this, a problem arises in that the range in which the ASIC can be developed is restricted by the I / O module focused on by such an identification method.

Further, when standardizing a system development tool for a group of evaluation chips having a common central processing unit, it is necessary to realize a signal input / output function necessary for emulation and a logic for controlling the signal input / output function. It was clarified that it was necessary to consider the arrangement of the required external terminal groups to be constant when developing the product type or ASIC. Otherwise, a partial hardware change of the system development tool is inevitable for all or some of the evaluation chips to be developed or developed by ASIC.

In addition, a target microcomputer circuit as a real chip to be controlled as a proxy is used as a core, and the input / output function of signals necessary for emulation and the logic for controlling it are added to form an evaluation chip. As a result, the number of circuit components in the system development tool can be reduced accordingly, but a circuit for preventing the floating state of the input terminal when the input terminal according to the logic thus added is interfaced with the system development tool. It is desirable that the elements be incorporated in the evaluation chip in order to reduce the number of circuit components in the system development tool. In that case, it has been found that it is necessary to consider the prevention of the occurrence of leakage current due to the circuit element from the viewpoint of facilitating an electrostatic breakdown test and the like.

Furthermore, as described above, a target microcomputer as a real chip to be controlled as a substitute is used as a core, and a signal input / output function required for emulation and logic for controlling it are newly added. When obtaining various evaluation chips corresponding to product development or ASIC development by the method that performs the above, it is often necessary to output signals that should be originally output to the target system to the emulator side by additional logic due to the nature of proxy control It is in. In such a case, if the wiring load for the source of the signal may be larger than the original wiring load due to the additional logic, the electrical characteristics of such a signal or the propagation of the signal between the evaluation chip and the actual chip. I noticed that there was an inconsistency in the characteristics, which reduced the reliability of the software debug results. Therefore, in the method of obtaining an evaluation chip by diverting an actual chip, it is necessary to consider that when adding logic for emulation, the electrical characteristics must be the same as the actual chip. Was.

Further, in a method of obtaining an evaluation chip by diverting an actual chip and adding an additional logic for emulation thereto, a signal wiring for the additional logic should be included in a circuit of the actual chip in advance. Has found that it is preferable in facilitating the formation of the evaluation chip, but in that case, in order to use the circuit of the real chip only as the real chip, the signal wiring for the additional logic provided in advance, particularly the input wiring Therefore, permanent floating prevention measures are required, and if these measures are individually applied to each signal wiring, the trouble in that case cannot be ignored, and conversely, the reliability will be increased due to the incorrect modification of the logic at multiple locations. There is a risk of lowering. Therefore, when the signal wiring for the additional logic is included in the circuit of the real chip in advance, consideration should be given to minimizing the number of circuit corrections when using the circuit of the real chip only as the real chip. Was found to be necessary.

An object of the present invention is to improve the software debugging environment of a microcomputer system from the viewpoint of the configuration of an actual chip and an evaluation chip. More specifically, the software debugging system of a microcomputer system is easily and reliably provided. It is an object of the present invention to provide a microcomputer as an evaluation chip or an actual chip which can be prepared to obtain general versatility.

The outline of each specific purpose corresponding to each invention is to make a plurality of types of microcomputers, which are developed in varieties or ASICs, suitable for the standardization of system development tools such as emulators, and for real chips. When an evaluation chip is formed by adding logic to a circuit as a core, matching the electrical characteristics of signals common to the actual chip and the evaluation chip, the number of external circuit elements for preventing floating of input terminals on the evaluation chip To reduce the influence of the leakage current of the circuit element during the test of the evaluation chip, and to easily obtain the evaluation chip by diverting the actual chip. When an evaluation chip is formed by using a chip as a core and adding logic to the core, an actual chip incorporating the logic to be added in advance is used. When the circuit of the real chip is used only as a real chip, the reliability is improved by reducing the number of corrections to the circuit of the real chip.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[Means for solving the problem]

The outline of a representative invention among the inventions disclosed in the present application will be briefly described as follows. In other words, an evaluation microcomputer that performs an alternate control of an application system of a target microcomputer by using an emulator has a core block (10) formed in the center of one semiconductor substrate and an outer peripheral edge of the core block. An additional block (11) is formed. The core block includes a central processing unit (16) and a central processing unit which are provided with external interface ports (27a to 27d) of the target microcomputer on a peripheral portion and are connected to the external interface ports via an internal bus. , A plurality of peripheral circuits (19, 29,...). The additional block includes a target port (4a-4d) for interfacing an interface port included in the core block to the target system, and a first evaluation port for interfacing the interface port with the emulator. Ports (5c, 5d)
A second evaluation port (5a, 5d) for interfacing the internal bus with the emulator, and a third evaluation port (5e) for receiving an input signal from the target port and outputting the signal to the emulator. ) And identification information output means (5g) for outputting identification information for specifying the configuration of the core block. The means based on this configuration can be summarized as follows.

First, the logic of the microcomputer as a real chip in the target system is added or changed as desired, and an evaluation chip for software debugging that can control the microcomputer as a real chip while exchanging signals with a debugger, Includes identification information output means for enabling a debugger to identify a proxy control function corresponding to an actual chip, such as an ASIC developed by selecting peripheral functions as desired, with a common structure or control function of the central processing unit. .

Focusing on a core block which can be a microcomputer chip as a real chip to be controlled by proxy, an additional block for enabling this core block to interface with both the target system and the debugger,
When the identification information output means is included, the function and arrangement of the terminals of the debugger-side interface of the additional block can be made constant among a plurality of different core blocks.

In addition, external terminals of monitor signal output means for providing a signal supplied from the target system to the system development support device are arranged so as to be identical to each other among a plurality of objects having different control targets. Can be.

Secondly, regarding the signals commonly output from both the system development support device side interface unit and the target system side interface unit of the additional block, the signal wiring which is output from the core block and reaches the system development support device side interface unit A drive circuit such as an output buffer sufficient to drive the circuit is provided to constitute an evaluation chip.

Thirdly, it is possible to switch between a real chip mode in which the same operation as the microcomputer as the real chip to be controlled is performed and a debug mode according to logic which is added or changed as desired to the microcomputer as the real chip. Operation mode switching logic, and a pull-up or pull-down element operable in response to selection of a debug mode by the operation mode switching logic is used as an input terminal and an input / output terminal of the interface unit on the system development support device side. The evaluation chip is configured to be built in corresponding to the terminal.

Fourth, an evaluation chip is configured by including the operation mode switching logic in a core block. Further, the core block incorporates a fixing means for collectively fixing the operation mode switching logic to the real chip mode in a selection setting format like a master slice, and is used for forming a real chip by the circuit of the core block. To serve.

(Operation)

According to the first means, the system development tool reads the identification information output by the evaluation chip and recognizes the actual chip function held by the evaluation chip. Due to the consistency of the recognition method, hardware and software for the system development tool to recognize the type of the evaluation chip are shared regardless of the actual chip functions possessed by the evaluation chip. As a result, the system development tool can extract the additional debug program corresponding to the identification information from the data table and perform emulation operations, etc. A general-purpose use of the system development tool is improved by partially adding a debugging program to the type of evaluation chip without changing the hardware of the system development tool. In other words, an evaluation chip corresponding to a plurality of types of microcomputers developed in a variety of types or ASICs is suitable for standardization of a system development tool such as an emulator.

At this time, not only the identification information output terminal but also a terminal group constituting a system development support device side interface such as a monitor signal output terminal are arranged so as to be mutually identical among a plurality of terminals having different substitute control targets. When configured, individual evaluation chips corresponding to multiple types of microcomputers deployed in product types or ASICs
It further promotes the sharing of hardware and software of system development tools.

According to the second means, the signal wiring load increased by the additional logic is output to the target system in the real chip and is also output to the emulator side by the additional logic in the evaluation chip by being driven by the dedicated drive circuit. The electrical characteristics between the signals or the propagation characteristics of the signals are matched, thereby improving the reliability of the software debug result.

According to the third means, since the evaluation chip itself has a built-in pull-up or pull-down element, an external circuit element for preventing floating of the input terminal of the evaluation chip is not required on the system development tool side, and the components of the system development tool are not required. A reduction in the number of parts and an improvement in reliability due to a reduction in the probability of assembly failure with respect to the reduced parts are achieved. Further, when the real chip mode is selected, the pull-up or pull-down elements are controlled to be in an off state, and a leak current is prevented from being generated at an input terminal or the like coupled to the elements, whereby a test such as an electrostatic breakdown test is performed. In this case, it is also possible to prevent the leakage current of the circuit element from affecting.

According to the fourth means, when a circuit of an actual chip is used as a core and logic is added to the core to form an evaluation chip, a circuit of the actual chip in which the logic to be added is prepared in advance is prepared. When an actual chip is used to obtain an evaluation chip, it is only necessary to modify the layout so that the debug mode can be set by the operation mode switching signal, thereby reducing the development man-hour of the evaluation chip. Also,
The logic to be added, which is built in the real chip in advance, can be collectively invalidated by the fixing means, so that the circuit of the real chip is used only when the circuit of the real chip is used as the real chip. The number of locations is extremely reduced.

〔Example〕

FIG. 1 is a block diagram generally showing a microcomputer according to an embodiment of the present invention. The microcomputer shown in FIG. 1 is formed on one semiconductor substrate such as silicon by a known semiconductor integrated circuit manufacturing technique.

The microcomputer 1 of the present embodiment is not particularly limited, but as shown in FIG. 2, the logic of the microcomputer as a real chip (not shown) in the desired target system 2 is added and changed as desired, and the microcomputer 1 A microcomputer for software debugging, that is, an evaluation chip capable of acting as a substitute for a target microcomputer as an actual chip while exchanging data. The microcomputer (hereinafter, also simply referred to as an evaluation chip) 1 of this embodiment is mounted on an emulator 2 or a pod (not shown) via an external terminal of a predetermined package such as a dual in-line package or a flat package. The interface unit 4 is connected to a target microcomputer mounting area 7 via an interface cable 6. The emulator-side interface unit 5 of the microcomputer 1 is interfaced with a breakpoint control unit, an emulation control unit, a trace memory unit, a substitute memory unit, a host processor, and the like via an emulation bus (not shown).

According to FIG. 1, the microcomputer 1 of this embodiment
Although not particularly limited, a core block 10 which can be a microcomputer chip as a real chip to be controlled by proxy, and an additional block 11 for enabling the core block 10 to interface with both the target system 2 and the emulator 3 , And is basically configured in such a manner that actual chips are diverted.

In this embodiment, the real chip means a microcomputer as a main product actually mounted on the target system. Core block corresponding to this real chip
Numeral 10 has at least a control function of a real chip due to the nature of proxy control in emulation. Therefore, a common central processing unit can be used to change peripheral functions as desired.
For a plurality of types of different real chips developed by ASIC development or product development, the evaluation chip 1 of the present embodiment is formed including the core block 10 having the function corresponding to each of them.

First, a method of forming the evaluation chip 1 by using the actual chip will be described with reference to FIG.

The core block 10 not only substitutes for a real chip as a target microcomputer, but also informs the control state to the emulator 3 while performing substitution control of the target microcomputer due to the nature of emulation, and executes a program flow for debugging. The function includes a function that can change the control state by arbitrarily changing, that is, a signal input / output function necessary for emulation and a logic for controlling the function. In FIG. 3, such additional logic is conceptually shown as an inverter 13 and a NAND gate 14. Incidentally, such additional logic can be included in the circuit of the actual chip, and the processing in that case will be described later.

The additional block 11 includes a target-side interface unit 4 for exchanging signals with the target system 2 due to the nature of proxy control, and additional logic such as the inverter 13 and the NAND gate 14 and the emulator 3. And an emulator-side interface unit 5 for providing monitor information and the like to the emulator 3 when performing proxy control of the target system 2.

The evaluation chip 1 is configured by forming such a core block 10 and the additional block 11 on one semiconductor substrate.

Next, the whole of the evaluation chip 1 of the present embodiment will be described in detail mainly with reference to FIG.

The core block 10 includes, but is not limited to, a CPU (Central Processing Unit) 16 which is shared when developing an ASIC, a bus controller 17, an interrupt controller 18, a working area and a RAM which is a temporary storage area for data. (Random access memory) 19, ROM (read only memory) 20, which is a program memory, timer 21, serial communication interface controller (hereinafter also simply referred to as SCI) 2
2. An analog-to-digital (hereinafter also simply referred to as AD) converter 23 and a module selector for selecting the timer 21, SCI22, AD converter 23, etc.
24 and the like, which are appropriately coupled to an internal data bus 25 and an internal address bus 26. In addition, core block 10
Peripheral modules such as timer 21 and SCI22 and AD converter 23 included in
Furthermore, if necessary, direct memory access
A new functional module such as a controller is added.

The core block 10 includes various ports 27a to 27d corresponding to ports that the real chip should originally have. These ports 27a to 27d are basically ports used for interface with the target system 2. Although not particularly limited, the port 27a is a port for exchanging data DATA and an address signal ADRS, and the port 27b is a
It is used for exchanging signals with peripheral modules such as CI22, and is used for exchanging transmission data TD and reception data RD in SCI22, for example. Also port 27c above
Is a port for exchanging a bus request signal BREQ and a bus acknowledge signal BACK for bus arbitration, an interrupt signal IRQ, and the like. And the above port
27d is a port for exchanging a read signal RD, a write signal WT, and the like.

The additional block 11 includes various ports as the target system-side interface unit 4 which is actually interfaced with the target system 2 via the ports 27a to 27d.
4a to 4d are formed.

Next, an additional logic for emulation in the core block 10 and a configuration corresponding to the additional logic in the additional block 11 will be described.

In emulation, the state of the internal data bus 25 can be traced,
In some cases, the ROM 20 holds the memory inside the emulator 3 or the memory included in the main target system 2 is replaced with the memory inside the emulator 3. To cope with these, a data bus 30 coupled to the internal data bus 25 is added. In response to this, an additional block 11 includes a data input / output unit for enabling the data bus 30 to interface with the emulator 3. 5a is provided. In response to this, an address output section 5 b branched from the internal address bus 26 is provided in the additional block 11 so that the address signal on the internal address bus 26 can be supplied to the emulator 3. The data input / output through the data input / output unit 5a is shown as ADATA, and the address signal output from the address output unit 5b is
Shown as AADRS.

A control signal output unit 5c for providing various control signals corresponding to the program execution state in the core block 10 to the emulator 3 is provided in the additional block 11. In particular, the control signal output unit 5c is branched and connected to a part of the signal line 31 extending from the bus controller 19 to the port 27d. The signals branched and supplied from the signal line 31 to the control signal output unit 5c are, for example, a read signal RD and a write signal WT. Control signal output section 5c
Is not particularly limited, but the read signal supplied to this
The assertion timing of the RD and the write signal WT is changed and output so that the memory access control timing by the emulator 3 matches the memory access timing inside the core block 10. The read signal and the write signal output from the control signal output unit 5c are illustrated as ADR and AWT.

The additional block 11 is provided with a control signal input unit 5d for receiving a control signal from the emulator 3, and a signal supplied thereto is not particularly limited, but the bus controller 19 and the port 27a are connected via signal lines 32 and 33 and the like. And so on. The signal given to the control signal input unit 5d is not particularly limited, but is a wait signal AWAIT for stopping the operation of the CPU 16, and the like.

The additional block 11 has a terminal information output unit 5e for monitoring terminal information of the core block 10, for example, desired information exchanged with the target system 2 via the ports 4b and 4c.
Is provided. As a signal output from the terminal information output unit 5e, AIRQ and ARD are representatively shown.

The additional block 11 is a debug mode for enabling the core block 10 by enabling the various additional logics, that is, an emulation mode according to the present embodiment, and a target microcomputer as an actual chip with the various additional logics for the core block 10 disabled. And an input section 5f for a mode switching signal AMODE for instructing a real chip mode performing the same operation as the above. The block that receives the mode switching signal AMODE inside the core block 10 is a fixing unit 34 that can permanently fix the operation mode of the core block to the real chip mode.

The additional block 11 is provided with an identification information output unit 5g for enabling the emulator 3 to identify the function or configuration of the core block 10 corresponding to various real chips provided by being expanded into an ASIC. Is not particularly limited, the identification information output unit 5g outputs the device identification code AID ₀ ~AID ₂ of 3 bits.

The blocks indicated by 5a to 5g in FIG. 1 correspond to the emulator-side interface unit 5 in FIG.

The evaluation chip 1 configured as above as a whole is
ASICs are developed and accommodated in a common package among those having different core blocks 10. At this time, the external terminals connected to the emulator-side interface unit 5 of the additional block 11, such as the identification information output unit 5g and the terminal information output unit 5e, have different paper capabilities and arrangement configurations when the ASIC is developed. Among a plurality of different types of evaluation chips 1.

For example, taking the terminal information output unit 5e as an example, assuming that the terminal information to be monitored in the core block 10 in FIG. 4 is the information of the input terminal 40, the terminal information is coupled to the input terminal 40 in the layout of the additional block 11. The signal line is connected to the terminal information output unit 5e. On the other hand, when the terminal information to be monitored in the other core blocks 10 shown in FIG. 5 is the information of the input terminal 41, the signal line coupled to the input terminal 41 in the layout of the additional block 11 is sent to the terminal information output unit 5e. Join. As a result, desired terminal information to be monitored can be obtained for the external terminals allocated to the terminal information output unit 5e irrespective of the configuration of the core block 10. still,
This relationship is not limited to the terminal information output unit 5e but also to the control signal output unit 5c.
The same applies to not only the information of the input terminal but also the output of the internal gate represented by the NOR gate 42 in FIG. 4 or the output of the internal gate represented by the NOR gate 43 in FIG. Can also be given.

The configuration of an output circuit corresponding to one output terminal in the terminal information output section 5e is to configure a complementary MOS inverter composed of an N-channel MOSFET Q1 and a P-channel MOSFET FEYTQ2 as an output buffer as shown in FIG. Can be.

According to the method of arranging the external terminals connected to the emulator-side interface unit 5 of the additional block 11 such as the identification information output unit 5g and the terminal information output unit 5e, each type corresponds to the ASIC development. When the emulator 3 monitors desired information with respect to the evaluation chip 1 including the core block 10, even if the terminals to be monitored in the respective core blocks 10 are located at mutually different positions, the same on the corresponding evaluation chip 1 Emulator 3
The hardware of the signal monitor unit is common to the various evaluation chips 1.

 Next, the identification information output unit 5g will be described in detail.

FIG. 7 is a circuit diagram showing an example of the identification information output unit 5g. This identification information output section 5g is an N-channel type MOSFET.
A required three-bit device identification code AID ₀ is provided by providing three sets of circuits each having a complementary MOS inverter composed of Q3 and a P-channel type MOSFEYTQ4 as an output buffer, and controlling each gate input signal by the number of inverters INV. ~
AID ₂ is formed.

With the provision of the identification information output unit 5g, the emulator 3 can output the device identification code AI output from the evaluation chip 1.
By reading D _{0 to} AID ₂ , the actual chip function of the evaluation chip 1 is recognized. Due to the consistency of the recognition method, hardware and software for the emulator 3 to recognize the type of the evaluation chip are shared irrespective of the actual chip functions of the evaluation chip 1. As a result, the emulator 3 can perform an emulation operation by extracting an additional portion of the debugging program corresponding to the identification information from a data table or the like, and can perform a plurality of types of different types of chips corresponding to different real chips developed as ASICs. By adding a debugging program partially to the evaluation chip without changing the hardware of the emulator 3, general-purpose usability of the emulator can be enhanced. In other words, a product type or ASIC is developed. An evaluation chip corresponding to a plurality of types of microcomputers is suitable for standardization of an emulator.

At this time, the terminal arrangement for the emulator-side interface unit 5 including the identification information output unit 5g is a core block.
Regardless of the ten differences, they are made the same, so that the hardware and software of the system development tool can be further standardized for each evaluation chip corresponding to a plurality of types of microcomputers deployed in ASIC.

In particular, since the identification information output unit 5g is provided in the additional block 11, and can adopt an arrangement independent of the layout configuration of the core block 10, the core area does not increase the chip area of the core block 10 that can be an actual chip. Even if the circuit configuration of the block 10 is different, it becomes easy to always arrange an output terminal therefor at a fixed position on the additional block 11 irrespective of the difference.

Next, measures for preventing electrical mismatch between signals output from the evaluation chip and the actual chip will be described.

In the evaluation chip 1, a signal originally output to the target system 2 is simultaneously supplied to the emulator 3 by the additional logic due to the necessity of emulation. According to this embodiment, the address signal AADRS output from the address output unit 5b branched and coupled to the internal address bus 26 and the read signal ARD output from the control signal output unit 5c branched and coupled to the signal line 31 are used. And a write signal AWT. In the real chip, the address signal ADRS, read signal RD, and write signal WT are
It is only output via a or 27d. In the evaluation chip 1, those signal wires are extended into the additional block 11. In this embodiment, in order to prevent the wiring load capacitance to be driven for the source of these signals from substantially increasing due to such extension of the signal wiring, the address output unit 5b
Drive circuits 50 and 51 such as output buffers are interposed in the vicinity of the branch point of the internal address bus 26 reaching the control signal output unit 5c, respectively. The drive circuits 50 and 51 need only have the ability to drive the signal lines from the branch points of the respective signal lines to the emulator-side interface units 5b and 5c.

FIG. 8 is a circuit diagram showing an example of the drive circuit 51 relating to the read signal ARD. In FIG. 8, reference numeral 53 denotes a driver for generating a read signal RD inside the bus controller 19. The driving circuit 51 includes a buffer gate 54 and a driver 55.
Composed of The driver 53, which is the source of the read signal RD, drives the wiring load capacitance 56 inside the core block together with a plurality of gates included in the port 27d. A driver 55 included in the drive circuit 51 drives a plurality of gates in the control signal output unit 5c and drives a wiring load capacitance 57 inside the additional block.

As is clear from FIG. 8, the driver 53, which is the source of the read signal RD, only needs to drive the inside of the core block 10, and the evaluation chip including the core block 10 and the additional block 11 and the core block The drive load of the driver 53 is substantially the same in any of the real chips composed of only 10. When the driving circuit 51 is not provided as shown in FIG. 9, the driving load of the driver 53 is significantly different between the evaluation chip and the actual chip, and the electrical characteristics of the read signal RD output from the port 27d or The signal propagation characteristics may be different between the evaluation chip and the actual chip. These points are similarly applied to the write signal WT and the address signal ADRS.

Therefore, the signal wiring load increased by the additional logic is output to the target system in the actual chip and is also output to the emulator side by the additional logic in the evaluation chip by being driven by the dedicated drive circuits 50 and 51. The electrical characteristics or signal propagation characteristics are matched, and the reliability of the emulation result is improved.

Next, a floating prevention technique for the input terminal and the input / output terminal of the control signal input unit 5d and the data input / output unit 5a of the emulator-side interface unit 5 will be described.

As shown in FIG. 10, the power supply terminals Vdd, Vs
In addition, the surge absorbing diodes 62 and 63 are coupled between s to take measures against electrostatic destruction, and from the viewpoint of matching with the driving logic of the signal line 61 and preventing malfunction, the pull-up element 64 having a high resistance is used.
Alternatively, a pull-down element (not shown) is coupled. In the present embodiment, the floating state of the external input terminal is prevented with respect to the emulator-side interface unit 5, particularly the control signal input unit 5d connected to the external input terminal and the data input / output unit 5a coupled to the external input terminal. In this case, consideration is given to the possibility of selectively stopping the generation of leak current by the circuit element from the viewpoint of facilitating an electrostatic breakdown test or the like in that case.

For example, FIG. 11 corresponds to one bit in the data input / output unit 5a. The output terminal of a tri-state output buffer 66 is coupled to the data input / output terminal 65 typically shown in FIG. The tristate output buffer 66 is controlled to a high output impedance state when the control signal φ is made low. In this state, the input / output terminal 65 is used for data input. When control signal φ is set to a high level, a signal of a level corresponding to output data Dout is applied to data input / output terminal 65. Between the output terminal of the output buffer 66 and the power supply terminal Vdd, a P-channel type pull-up MOSFET Q5 having a relatively high resistance and high withstand voltage is coupled. The gate electrode of the pull-up MOSFET Q5 is supplied with an inversion level of the mode switching signal AMODE taken in via the input section 5f. The input data supplied to the input / output terminal 65 is supplied to one of the input terminals by the mode switching signal AMOD.
The two-input NOR gate 67 to which the inverted level of E is supplied can be selectively taken in via the other input terminal.

Although the mode switching signal AMODE is not particularly limited, its high level indicates a debug mode in which various additional logics of the evaluation chip 1 are enabled and the core block 10 is operable, that is, an emulation mode. Thus, the real chip mode in which various additional logics for the core block 10 are invalidated and the same operation as the target microcomputer as the real chip is performed is indicated.

FIG. 12 corresponds to one bit in the control signal input unit 5d. The input data supplied to the data input terminal 68 typically shown in FIG. 12 is selected via the other input terminal of the two-input NOR gate 69 to which one input terminal is supplied with the inverted level of the mode switching signal AMODE. It can be taken inside. In the case of FIG. 12, similarly to FIG. 11, a P-channel type pull-up MOSFET Q5 which is switch-controlled at the inversion level of the mode switching signal AMODE is incorporated.

In the data input / output unit 5a and the control signal input unit 5d whose typical configurations are shown in FIGS. 11 and 12, when the mode switching signal AMODE is set to a high level, a pull-up MOSFE
While TQ5 is controlled to be in the ON state, the NOR gate circuit 67,
69 is controlled so that data supplied from the external terminals 66 and 68 can be inverted and transmitted. When the mode switching signal AMODE is inverted to a low level, the pull-up MOSFET Q5 is turned off and the data supplied from the external terminals 65 and 68 are invalidated by the functions of the NOR gate circuits 67 and 69.

The NOR gate circuits 67 and 69 provided at the input first stage are examples of an element that configures an operation mode switching logic for the bit in an additional block.
In response to the low level of ADODE, the input is invalidated, and the internal floating state is blocked so that the through current does not flow. The operation mode switching logic in such an additional block is provided for each bit in the data input / output unit 5a and the control signal input unit 5d,
If necessary, other circuit blocks of the emulator-side interface unit 5 can be provided.

Thus, the pull-up MOSFET Q5 is connected to the evaluation chip itself corresponding to the input terminal interfaced with the emulator 3.
The external circuit element for preventing the floating of the input terminal in the evaluation chip 1 is not required on the emulator 3 side, and the number of parts of the system development tool is reduced, and the probability of assembling connection failure is reduced with respect to the reduced parts. Improved reliability can be achieved.

When the real chip mode is selected, the pull-up MOSFET
Q5 is controlled to be in the off state, preventing the occurrence of leakage current at the input terminals and the like coupled to those elements, thereby preventing the leakage current of the circuit element from affecting the circuit during tests such as electrostatic breakdown tests. Can also be prevented,
This makes it easier to check for an increase in input leak current due to electrostatic breakdown of the input terminal, thereby simplifying such a test and improving reliability.

Next, a case where the operation mode switching logic is built in the core block of the evaluation chip or the actual chip will be described.

Here, first, in a method of diverting an actual chip and adding an additional logic for emulation to obtain an evaluation chip as in the present embodiment, a signal wiring for the additional logic, for example, a core block shown in FIG. Signal line 30 included in 10
Or 32 is preferably included in an actual chip or a core block in advance in order to facilitate the formation of an evaluation chip. In this case, however, a circuit configuration including additional logic for emulation must be implemented in advance. In order to use it only as a loop, permanent floating prevention measures are necessary for the signal wiring for the additional logic, especially for the input wiring.
If this is individually applied to each signal wiring, the trouble in that case cannot be ignored, and the reliability may be reduced due to a defective logic modification / change at a plurality of locations. Therefore, in this embodiment, when the input signal wirings for the additional logic for emulation previously included in the circuit configuration for the core block or the real chip are not used, they are not put into a floating state, and the processing is performed. In order to be able to perform the operation at once, a new operation mode switching logic corresponding to the operation mode switching logic in the emulator-side interface unit 5 described above is included in the circuit configuration for the core block or the actual chip. When the operation mode switching logic is included in the circuit configuration for the core block or the real chip, the operation mode switching logic of the emulator-side interface unit 5 on the additional block side corresponding to this logic can be omitted, but can be used together. Especially in the case of coexistence, there should be no conflict between the two switching logics.

FIG. 13 is a circuit diagram showing an example of the operation mode switching logic included in the core block 10 of the evaluation chip 1. The configuration shown in the figure is an example of the operation mode switching logic 70 inside the core block 12 related to the signal line 32 in FIG. 1 which is one of the additional logics for emulation. This is an example in which the operation mode switching logic 71 also coexists in the control signal input unit 5d in FIG.

When the operation mode switching signal AMODE is set to a low level corresponding to the actual chip mode, the operation mode switching logic 71 in FIG. 13 is independent of the level of the input control signal and the output signal lines 32a, 32a of the control signal input section 5d. 32b is fixed at a high level as a disable level, and the signal line 32c
Is fixed to a low level as a disable level, and the input control signal is invalidated. Operation mode switching signal
When AMODE is set to a high level corresponding to the emulation mode, the output signal lines 32a, 32a,
32b32c is controlled to a level corresponding to the input control signal level, and the input control signal is effectively taken in.

Operation mode switching logic 70 included in core block 10
Has logic that matches the switching logic 71, for example,
The drain electrode is coupled to the signal line 32a and the P-channel type charge MOSFET Q6 is switch-controlled by the operation mode switching signal AMODE non-inversion signal, the operation mode switching signal AMODE non-inversion signal and the output signal line 32b signal. 2
The input NAND gate 72 and the drain electrode are signal lines
An N-channel discharge MOSFET Q7 coupled to 32c and controlled by an inversion signal of the operation mode switching signal AMODE. According to the operation mode switching logic 70, the operation mode switching signal AM
When the ODE is set to the low level, the output signals of the operation mode switching logic 70 are respectively fixed to the disable level defined by the internal logic. When the operation mode switching signal AMODE is controlled to a high level, the control signal supplied to the evaluation chip can be effectively taken into the core block 10.

In FIG. 13, reference numeral 34 denotes fixing means for collectively fixing various operation mode switching logics included in the core block 10 as represented by the operation mode switching logic 70 in FIG. 13 to the real chip mode. The fixing means 34 is not particularly limited, but is constituted by a pull-down resistor connected to the ground terminal Vss of the circuit, and the layout can be modified to be conductive or non-conductive to the operation mode switching signal line 74 by means such as an aluminum master slice. Has become. When the circuit configuration of the core block 10 is used as an evaluation chip as shown in FIG. 13, since the operation mode can be switched by the signal AMODE, the resistor constituting the fixing means 34 has the operation mode switching function. The layout is set to be non-conductive with the signal line 74.

On the other hand, when the circuit configuration of the core block 10 is used as an actual chip, as shown in FIG.
Will be deleted. In this case, in order to invalidate unnecessary inputs in the actual chip so as not to float, it is necessary to modify the layout of the portion so that the resistor constituting the fixing means 34 is electrically connected to the operation mode switching signal line 74. I just need.

In this way, in the circuit of the core block or real chip,
When additional logic such as signal wiring required for emulation is included, a switching logic 70 for switching between the real chip mode and the debug mode and a fixing means 34 capable of fixing the switching logic 70 to the real chip mode at once are provided in advance. When the evaluation chip is formed by using the circuit of the real chip, the debug mode and the real chip mode can be set only by modifying the layout of the fixing means 34 so that the debug mode can be set by the operation mode switching signal AMODE. It is possible to easily obtain an evaluation chip that can be set to be switched, and to reduce the number of development steps of the evaluation chip.

Further, when the circuit of the real chip is used as a real chip, additional logic for unnecessary emulation, particularly input wiring of a control signal for emulation, can be collectively invalidated only by modifying the layout of the fixing means 34. Therefore, when the circuit of the real chip is used only as the real chip, the number of corrections to the circuit of the real chip can be significantly reduced.

Note that the fact that the real chip mode can be selectively set for the evaluation chip also helps to simplify the test of the evaluation chip in addition to the convenience of making the evaluation chip usable as the real chip. That is, since the evaluation chip is configured by adding logic for emulation to the function of the corresponding real chip, the test pattern for the real chip is added to the evaluation chip for the test operation overlapping between the two. Set the mode so that it can be used. This saves time and effort for creating a test pattern for the evaluation chip.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the embodiment and can be variously modified without departing from the gist of the invention.

For example, the configuration of the emulator-side interface unit 5 of the additional block 11 included in the evaluation chip, the core block 10
The functional module configuration, the specific circuit configurations of the drive circuits 50 and 51, the specific circuit configuration of the operation mode switching logic, and the like can be appropriately changed.

Further, in the above embodiments, a plurality of inventions disclosed in this specification are applied to one evaluation chip, but it goes without saying that each invention can be applied independently.

The microcomputer is not limited to a so-called single-chip microcomputer as in the embodiment of the personal computer, but means various data processing devices such as a microprocessor.

In the above description, mainly the case where the invention made by the present inventor is applied to a real chip for an ASIC-developed microcomputer or an evaluation chip for emulation, which is the field of application that has become the background, has been described. The present invention is not limited to this, and can be widely applied to microcomputers and other data processing devices that can be used for various system evaluation tools.

〔The invention's effect〕

The effect obtained by the representative one of the inventions disclosed in the present application will be briefly described as follows.

That is, control is performed by the identification information output function in the evaluation chip, the common terminal configuration in the interface unit with the development support device used for evaluation and development of the target system, and the adoption of monitor signal output means included in the interface unit. For multiple evaluation chips with different functions,
If the hardware and software of the development support device can be shared, and a new real chip is developed and provided by ASIC development or product development, a part of the common software can be used for new software debugging. Only the information needs to be added, and the added information can be recognized by the development support device based on the identification information given from the evaluation chip. As a result, by adding a debugging program partially to a plurality of types of evaluation chips corresponding to different real chips developed in ASICs without changing the hardware of the development support device, the system development can be performed. Increase the general-purpose use of tools,
There is an effect that the software debug environment of the system can be quickly prepared.

In addition, the signal wiring load, which is increased by the additional logic for software debugging on the evaluation chip, is output to the target system in the actual chip by being driven by the dedicated drive circuit, and is output to the development support device by the additional logic in the evaluation chip. The electrical characteristics between the signals or the propagation characteristics of the signals are also matched so that the reliability of the software debug result can be improved.

In addition, since the evaluation chip itself has a built-in pull-up or pull-down element, an external circuit element for preventing floating of the input terminal of the evaluation chip is not required on the development support device side. Therefore, there is an effect that the reliability can be improved by reducing the probability of assembly failure. Further, when the real chip mode is selected, the pull-up or pull-down elements are controlled to be in an off state, and a leak current is prevented from being generated at an input terminal or the like coupled to the elements, whereby a test such as an electrostatic breakdown test is performed. In this case, it is possible to prevent the influence of the leak current of the circuit element, which has the effect of facilitating such a test and improving the reliability of the test.

Then, an operation mode switching logic for enabling a signal input required only in the debug mode to be effective only in the operation mode, including an additional logic such as a signal wiring required for software debugging, in the circuit of the core block or the real chip, and By incorporating a fixing means that can fix the switching logic collectively to the real chip mode, an evaluation chip that can switch and set both the debug mode and the real chip mode can be easily obtained, and the development man-hour of the evaluation chip is reduced. And the time required for preparing the software debug environment can be shortened. Furthermore, when the circuit of the real chip is used as a real chip, unnecessary logic for software debugging, which is unnecessary, especially input wiring can be collectively invalidated only by modifying the layout of the fixing means. When the circuit of the chip is used only as a real chip, the number of corrections to the circuit of the real chip can be significantly reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram generally showing a microcomputer, that is, an evaluation chip according to an embodiment of the present invention, FIG. 2 is an explanatory diagram showing an interface state between the evaluation chip, a target system, and an emulator, and FIG. FIG. 4 is a conceptual diagram showing a method of forming an evaluation chip by diverting chips, FIG. 4 is a conceptual diagram for explaining an external terminal arrangement of the evaluation chip, and FIG. 5 is a schematic diagram of an evaluation chip including a core block different from FIG. FIG. 6 is a conceptual diagram for explaining an external terminal arrangement, FIG. 6 is a circuit diagram illustrating an example of a terminal information output unit in an additional block of an evaluation chip, and FIG. 7 is an example of an identification information output unit in an additional block of an evaluation chip. FIG. 8 is a conceptual diagram showing a driving circuit in a core block of an evaluation chip, FIG. 9 is a conceptual diagram showing a case where there is no driving circuit corresponding to FIG. 8, 10 Figure is an explanatory view showing a general treatment for the input terminals of the LSI, FIG. 11 pulled up in an additional block of evaluation chip
Circuit diagram of data output section including MOSFET, Fig. 12 Pull-up in additional block of evaluation chip
FIG. 13 is a circuit diagram of a control signal input unit including a MOSFET, FIG. 13 is a circuit diagram showing a core block around a control signal input unit including operation mode switching logic and fixing means in an evaluation chip, and FIG. 14 corresponds to FIG. FIG. 3 is a circuit diagram showing a case where the circuit configuration of a core block is used as an actual chip. 1 ... Evaluation chip, 2 ... Target system, 3 ...
Emulator, 4 target interface unit
4a to 4d: port, 5: emulator side interface unit, 5a: data input / output unit, 5b: address output unit,
5c: Control signal output section, 5d: Control signal input section, 5e:
Terminal information output section, 5f… Operation mode switching signal input section, 5g… Identification information output section, AID _{0 to} AID ₂ … Device identification code, AMODE… Operation mode switching signal, 10…
Core block, 11… additional block, 16… CPU, 34…
... Fixing means, 50,51 ... Drive circuit, Q5 ... Pull-up MOS
FET, 70 ... Operation mode switching logic.

 ──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Yuji Ota 1450, Josuihonmachi, Kodaira-shi, Tokyo Inside Musashi Plant, Hitachi, Ltd. (72) Kenichi Aoki 1479, Josuihoncho, Kodaira-shi, Tokyo Hitachi Micro In Computer Engineering Co., Ltd. (72) Inventor Tatsuya Suzuki 1479, Kamizuhoncho, Kodaira City, Tokyo Hitachi Micro Computer Engineering Co., Ltd. (56) References JP-A-62-131362 (JP, A) JP-A Sho 62-224835 (JP, A)

Claims (3)

(57) [Claims] An evaluation microcomputer for performing an application control system of a target microcomputer by proxy using an emulator, wherein a core block is formed in a central portion of one semiconductor substrate, and an outer peripheral edge of the core block is formed. An additional block is formed in the core block, wherein the core block includes an external interface port provided in the target microcomputer on a peripheral portion and is connected to the external interface port via an internal bus, and the central processing unit. A plurality of peripheral circuits for the device, wherein the additional block includes a target port for interfacing an interface port included in the core block to the target system, and an interface for interfacing the interface port to the emulator. A first evaluation port for causing the internal bus to interface with the emulator; and a second evaluation port for receiving an input signal from the target port and outputting the signal to the emulator. 3
And an identification information output means for outputting identification information for specifying the configuration of the core block. 2. The microcomputer according to claim 1, wherein a bus drive circuit is interposed between said internal bus and an input of said second evaluation port. 3. The first and second evaluation ports are provided with circuit elements for selectively pulling up or pulling down an external interface terminal by a control signal. Item 18. The microcomputer according to Item 1.