JPS62272539A - Removing method for resist - Google Patents

Removing method for resist

Info

Publication number
JPS62272539A
JPS62272539A JP11643786A JP11643786A JPS62272539A JP S62272539 A JPS62272539 A JP S62272539A JP 11643786 A JP11643786 A JP 11643786A JP 11643786 A JP11643786 A JP 11643786A JP S62272539 A JPS62272539 A JP S62272539A
Authority
JP
Japan
Prior art keywords
substrate
resist
ashing
plasma
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11643786A
Other languages
Japanese (ja)
Inventor
Hiroshi Fujioka
洋 藤岡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP11643786A priority Critical patent/JPS62272539A/en
Publication of JPS62272539A publication Critical patent/JPS62272539A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To largely reduce a substrate damage at the time of removing a resist having a modified layer by removing by ashing the unmodified resist by diffusing gas containing ozone, and then removing by ashing the resist modified layer by an oxygen plasma. CONSTITUTION:When ashing, a substrate 1 to be processed is placed on a stage 2, and an oxygen (O2) is introduced from a gas inlet 6. This introduced oxygen (O2) is activated by an ozonizer 7, fed to a processing chamber 5, uniformly distributed by a gas dispersing plate 8 to be diffused to the main surface of the substrate 1 heated to the temperature. Unreacted resist layer on the substrate 1 is substantially completely removed by ashing by ozone (O3) in the reaction gas, and only the modified layer remains on the substrate 1. Then, the O3-ashed substrate 1 is plasma-processed, for example, by a sheet type plasma processor. In case of O2-plasma ashing, a plasma is generated between an anode 13 and a cathode 14, and the resist modified layer is completely removed by oxygen ions and radicals excited by the plasma.

Description

【発明の詳細な説明】 3、発明の詳細な説明 〔概 要〕 変質していないレジストをオゾンア・ノシングで除去し
た後、イオン衝撃等による変質レジスト層をプラズマア
ッシングで除去する工程を有するレジスト除去方法。
[Detailed Description of the Invention] 3. Detailed Description of the Invention [Summary] Resist removal comprising a step of removing an unaltered resist by ozone anothing and then removing a resist layer altered by ion bombardment, etc. by plasma ashing. Method.

〔産業上の利用分野〕[Industrial application field]

本発明はレジストの除去方法に係り、イオン注入工程の
特に強いイオン衝撃等により変質層を多量に生じている
レジストを、基板にダメージを与えずに完全に除去する
方法に関する。
The present invention relates to a method for removing resist, and more particularly, to a method for completely removing a resist that has a large amount of deteriorated layer due to particularly strong ion bombardment during an ion implantation process without damaging a substrate.

半導体回路が大規模化され高性能化されるLSIにおい
ては、従来のICに比べて品種数が増加し、且つ一品種
当たりの生産数量の減少は避けがたい(頃向である。
As semiconductor circuits become larger and more sophisticated, the number of types of LSIs increases compared to conventional ICs, and it is inevitable that the production volume per type will decrease.

そのためLSIの製造に当たっては、枚葉処理技術が多
く用いられる。
Therefore, single-wafer processing technology is often used in the manufacture of LSIs.

上記枚葉処理におけるベース領域、ソース・ドレイン領
域等の不純物導入領域の形成には、半導体基板上に形成
したレジスト層をマスクにして該半導体基板面に不純物
のイオンを加速注入するイオン注入技術が用いられる。
To form impurity-introduced regions such as base regions and source/drain regions in the above-mentioned single-wafer processing, an ion implantation technique is used in which impurity ions are acceleratedly implanted into the semiconductor substrate surface using a resist layer formed on the semiconductor substrate as a mask. used.

このイオン注入に際しては、加速された不純物イオンの
照射を受けるレジスト層の表面に、イオンのエネルギー
により変質層が形成されるという現象があり、特に高濃
度にイオン注入がなされた際には、上記変質層が多量に
形成されて該レジスト層の除去が困難になり、該レジス
ト層の除去に際して半導体基板に大きなダメージを与え
て、上記LSI等の製造歩留りを低下せしめるという問
題がある。
During this ion implantation, there is a phenomenon in which a degraded layer is formed due to the energy of the ions on the surface of the resist layer that is irradiated with accelerated impurity ions. There is a problem in that a large amount of the deteriorated layer is formed, making it difficult to remove the resist layer, and when removing the resist layer, the semiconductor substrate is seriously damaged, reducing the manufacturing yield of the above-mentioned LSI and the like.

そこで、基板に大きなダメージを与えずに変質層を有す
るレジスト層を完全に除去できるようなレジスト除去方
法が要望され゛ている。
Therefore, there is a need for a resist removal method that can completely remove a resist layer having an altered layer without causing significant damage to the substrate.

〔従来の技術〕[Conventional technology]

基板にダメージを与えないレジストの除去方法には、硫
酸ボイルその他のウェット処理方法があるが、このウェ
ット処理方法により変質層を多量に生じているレジスト
層を完全に除去することは不可能に近い。
Methods for removing resist that do not damage the substrate include sulfuric acid boiling and other wet processing methods, but it is nearly impossible to completely remove a resist layer that has a large amount of deteriorated layer using this wet processing method. .

そこで、従来変質層を有するレジスト層の除去には酸素
(0□)プラズマ等によるプラズマアッシング方法が用
いられていた。
Therefore, conventionally, a plasma ashing method using oxygen (0□) plasma or the like has been used to remove a resist layer having a deteriorated layer.

しかしこのプラズマアッシング方法は、イオン化された
0□等のイオンの衝撃によってレジストのアッシングを
促進する方法であるので、基板にダメージが及ぼされる
ことは避けがたい。
However, since this plasma ashing method promotes resist ashing by bombardment with ionized ions such as 0□, damage to the substrate is unavoidable.

そのため、高濃度イオン注入のマスクに用いられ多量の
変質層を有するレジスト層を完全に除去しようとして、
プラズマ強度を増大せしめたり、処理時間を大幅に延長
した際には、基板に及ぼされるダメージが大きくなって
、該基板に形成される半導体装置の電気的特性が劣化す
るという問題を生ずる。
Therefore, in an attempt to completely remove the resist layer, which is used as a mask for high-concentration ion implantation and has a large amount of altered layer,
When the plasma intensity is increased or the processing time is significantly extended, the damage to the substrate increases, resulting in a problem that the electrical characteristics of a semiconductor device formed on the substrate deteriorate.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

本発明が解決しようとする問題点は、従来、多量に変質
層を生じていたレジスト層の除去に際して、基板に大き
なダメージが与えられていたことである。
The problem to be solved by the present invention is that conventionally, when removing a resist layer that caused a large amount of deteriorated layer, a large amount of damage was caused to the substrate.

〔問題点を解決するための手段〕[Means for solving problems]

上記問題点は、イオン衝撃により変質層が形成されてい
るレジストを除去するに際して、オゾンを含むガスの吹
きつけにより未変質のレジストをアッシング除去した後
、酸素プラズマによりレジスト変質層をアッシング除去
する工程を有する本発明によるレジスト除去方法により
解決される。
The above-mentioned problem is solved by the process of removing unaltered resist by ashing by blowing ozone-containing gas, and then ashing and removing the deteriorated resist layer by oxygen plasma when removing a resist on which a deteriorated layer has been formed by ion bombardment. This problem is solved by the resist removal method according to the present invention.

〔作 用〕[For production]

即ち本発明の方法は、プラズマを用いないのでダメージ
を発生させないオゾンアッシングにより未変質のレジス
トを完全に除去した後、残留する変質層のみをプラズマ
アッシングにより除去するもので、これにより基板にダ
メージを与えるプラズマ処理の時間を大幅に短縮し、変
質層を有するレジスト除去に際しての基板ダメージを大
幅に減少する。
That is, in the method of the present invention, after the unaltered resist is completely removed by ozone ashing, which does not cause damage because it does not use plasma, only the remaining deteriorated layer is removed by plasma ashing, thereby causing no damage to the substrate. This greatly reduces the time required for plasma treatment, and significantly reduces damage to the substrate when removing a resist having an altered layer.

〔実施例〕〔Example〕

以下本発明を、図を参照し実施例により具体的に説明す
る。
Hereinafter, the present invention will be specifically explained by examples with reference to the drawings.

第1図はオゾンアッシング装置の一例を示す模式側断面
図、第2図はプラズマアッシング装置の一例を示す模式
側断面図である。
FIG. 1 is a schematic side sectional view showing an example of an ozone ashing device, and FIG. 2 is a schematic side sectional view showing an example of a plasma ashing device.

本実施例においては、シリコン(Si)基板上に、マス
クとして1μmの厚さに形成され、加速エネルギー60
KeV 、ドーズit t X1015C1ll−2で
砒素(^S)のイオン注入がなされ、多量の変質層が形
成されているレジスト層を有する被処理基板を用いる。
In this example, a mask is formed with a thickness of 1 μm on a silicon (Si) substrate, and an acceleration energy of 60
A substrate to be processed is used, which has a resist layer in which arsenic (^S) ions are implanted at KeV, dose it t X1015C1ll-2, and a large amount of altered layer is formed.

そして先ず上記被処理基板を、オゾン(03)アッシン
グ装置内に挿入し03アツシング処理を行う。
First, the substrate to be processed is inserted into an ozone (03) ashing device and subjected to the 03 ashing process.

03アツシング装置は、例えば第1図に示すように、被
処理基板lを載置するステージ2を内部に有し、ガス供
給管3を上部に、排気ダクトに接続されるガス放出口4
を下部に有する処理室5と、上記ガス供給管3の先に接
続され、ガス導入口6を有するオゾナイザ7とを持って
構成され、処理室5内の上部にはガス分散板8が配置さ
れ、ステージ2内にはヒータ9が具備せしめられてなっ
ている。
For example, as shown in FIG. 1, the 03 ashing device has a stage 2 on which a substrate to be processed 1 is placed, a gas supply pipe 3 at the top, and a gas discharge port 4 connected to an exhaust duct.
The ozonizer 7 is connected to the tip of the gas supply pipe 3 and has a gas inlet 6. A gas dispersion plate 8 is disposed in the upper part of the processing chamber 5. , a heater 9 is provided inside the stage 2.

アッシング処理に際しては、被処理基板1をステージ2
上に載置し、 200〜300℃に加熱した状態で、ガ
ス導入口6から酸素(0□)ガスを例えば2j?/wi
n程度の流量で導入する。この導入酸素(0□)はオゾ
ナイザ7により活性化されて、オゾン(03)を例えば
5%程度含んだ酸素ガス、即ち(0□+5%0.)反応
ガスとなり、処理室5に導かれ、ガス分散板8によって
均一に分配されて前記温度に加熱された被処理基板1の
主面に吹きつけられる。
During the ashing process, the substrate 1 to be processed is placed on the stage 2.
Placed on top and heated to 200 to 300°C, oxygen (0□) gas is supplied from the gas inlet 6, for example, at 2j? /wi
Introduce at a flow rate of about n. This introduced oxygen (0□) is activated by the ozonizer 7 and becomes an oxygen gas containing, for example, about 5% ozone (03), that is, (0□+5%0.) reaction gas, and is led to the processing chamber 5. The gas is uniformly distributed by the gas distribution plate 8 and blown onto the main surface of the substrate 1 to be processed heated to the above temperature.

そして上記反応ガス中のオゾン(0,)により被処理基
板1上の未反応レジスト層は殆ど完全にアッシング除去
され、該被処理基板1上には変質層のみが残留する。処
理時間は約1分程度である。
The unreacted resist layer on the substrate 1 to be processed is almost completely removed by ashing due to the ozone (0,) in the reaction gas, and only the degraded layer remains on the substrate 1 to be processed. The processing time is about 1 minute.

なおこの処理は常圧で行われる。Note that this treatment is performed at normal pressure.

次いで上記O,アッシングの終わった被処理基板1は、
例えば枚葉式のプラズマ処理装置により0□プラズマ処
理を行い、上記被処理基板1上に残渣とし゛ζ被着して
いる変質層の完全な除去がなされる。
Next, the substrate 1 to be processed after the above O and ashing is
For example, 0□ plasma processing is performed using a single-wafer type plasma processing apparatus, and the altered layer deposited on the substrate 1 to be processed as a residue is completely removed.

枚葉式プラズマ処理装置は例えば第2図に示すように、
上部にガス導入口10を有し、下部に真空排気口11を
有する反応容器12内の、下部にステージとなるアノー
ド13が配設され、該アノード13に対向して上部にカ
ソード14が配設されており、該アノード13とカソー
ド14が、カソード14側にコンデンサ15を介し例え
ば13.56MIIzの高周波電源16に接続されてな
っている。
For example, as shown in Fig. 2, a single wafer plasma processing apparatus
In a reaction vessel 12 having a gas inlet 10 at the upper part and a vacuum exhaust port 11 at the lower part, an anode 13 serving as a stage is disposed at the lower part, and a cathode 14 is disposed at the upper part opposite to the anode 13. The anode 13 and cathode 14 are connected to a high frequency power source 16 of, for example, 13.56 MIIz via a capacitor 15 on the cathode 14 side.

0□プラズマアツシングに際しては、被処理基板1をア
ノード13上に載置し、ガス導入口10から02を所定
流量で導入し、真空排気口11から所定の排気を行って
反応容器12内のガス圧を例えば2 Torr程度に減
圧しながら、アノード13−カソード14間にIKW程
度の高周波電力を印加し、アノード13−カソード14
間にプラズマを発生せしめ、該プラズマにより励起され
た酸素のイオン及びラジカルによって被処理基板1上に
残渣として被着しているレジスト変質層を完全に除去す
る。
0□ For plasma ashing, the substrate to be processed 1 is placed on the anode 13, the gas inlet 02 is introduced at a predetermined flow rate, and the vacuum exhaust port 11 is evacuated at a predetermined rate to drain the inside of the reaction vessel 12. While reducing the gas pressure to, for example, about 2 Torr, high frequency power of about IKW is applied between the anode 13 and the cathode 14.
During this process, plasma is generated, and oxygen ions and radicals excited by the plasma completely remove the altered resist layer deposited as a residue on the substrate 1 to be processed.

該実施例に用いた被処理基板1においては、レジスト変
質層の完全除去に要した時間は約10秒であった・ 以上により変質層を有するレジスト層の除去が完了する
In the substrate 1 to be processed used in this example, the time required to completely remove the deteriorated resist layer was about 10 seconds. With the above steps, the removal of the resist layer having the deteriorated layer was completed.

上記実施例に示したように、本発明の方法においては大
部分を占める未変質レジスト層の除去は基板にダメージ
を与えない03アツシング処理によってなされ、上記0
3アツシング処理後に残留するレジスト変質層のみが0
□プラズマアツシング処理によって除去されて、変質層
を有するレジスト層の完全な除去がなされる。
As shown in the above embodiments, in the method of the present invention, the unaltered resist layer, which accounts for most of it, is removed by the 03 ashes process that does not damage the substrate.
3. Only the resist deteriorated layer remaining after the ashing process is 0.
□The resist layer including the altered layer is completely removed by plasma ashing.

従って、従来2分程度行われていた0□プラズマアツシ
ング処理が、10秒程度に大幅に短縮されるので、該変
質層を有するレジスト層の除去に際しての基板に及ぼさ
れるダメージ量は大幅に減少する。
Therefore, the 0□ plasma ashing process, which conventionally took about 2 minutes, can be significantly shortened to about 10 seconds, and the amount of damage done to the substrate when removing the resist layer with the altered layer is greatly reduced. do.

そしてその結果、上記レジスト除去を終わった被処理基
板1、即ちシリコン(Si)基板における小数キャリア
の寿命で8は従来のレジスト除去方法を用いた場合より
も30%程度向上した。
As a result, the life span of minority carriers on the substrate 1 to be processed after the resist removal, that is, a silicon (Si) substrate, was improved by about 30% to 8 compared to when the conventional resist removal method was used.

なお本発明の方法は上記実施例に示した枚葉処理に限ら
ず、環状炉形式の反応容器を用いるハツチ処理にも勿論
適用される。
Note that the method of the present invention is not limited to the single wafer processing shown in the above embodiments, but is of course applicable to hatch processing using a ring furnace type reaction vessel.

〔発明の効果〕〔Effect of the invention〕

以上説明のように本発明のレジスト除去方法によれば、
イオン注入等により変質層を多量に生じているレジスト
層を、基板に大きなダメージを与えずに完全に除去する
ことができる。
As explained above, according to the resist removal method of the present invention,
A resist layer that has a large amount of altered layers due to ion implantation or the like can be completely removed without causing major damage to the substrate.

従って本発明はLSI等の製造歩留りの向上に有効であ
る。
Therefore, the present invention is effective in improving the manufacturing yield of LSIs and the like.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はオゾンアッシング装置の一例を示す模式側断面
図、 第2図はプラズマアッシング装置の一例を示す模式側断
面図である。 図において、 1は被処理基板、   2はステージ、3はガス供給管
、   4はガス放出口、5ば処理室、     6は
ガス導入口、7はオゾナイザ、   8はガス分散板、
9はヒータ、     ioはカス導入口、11は真空
排気口、  12は反応容器、13はアノード、   
 14はカソード、15はコンデンサ、  16は高周
波電源を示す。
FIG. 1 is a schematic side sectional view showing an example of an ozone ashing device, and FIG. 2 is a schematic side sectional view showing an example of a plasma ashing device. In the figure, 1 is a substrate to be processed, 2 is a stage, 3 is a gas supply pipe, 4 is a gas discharge port, 5 is a processing chamber, 6 is a gas inlet, 7 is an ozonizer, 8 is a gas distribution plate,
9 is a heater, io is a waste inlet, 11 is a vacuum exhaust port, 12 is a reaction vessel, 13 is an anode,
14 is a cathode, 15 is a capacitor, and 16 is a high frequency power source.

Claims (1)

【特許請求の範囲】 イオン衝撃により変質層が形成されているレジストを除
去するに際して、 オゾンを含むガスの吹きつけにより未変質のレジストを
アッシング除去した後、 酸素プラズマによりレジスト変質層をアッシング除去す
る工程を有することを特徴とするレジスト除去方法。
[Claims] When removing a resist in which an altered layer has been formed by ion bombardment, the unaltered resist is removed by ashing by blowing gas containing ozone, and then the altered resist layer is removed by ashing by oxygen plasma. A resist removal method comprising the steps of:
JP11643786A 1986-05-20 1986-05-20 Removing method for resist Pending JPS62272539A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11643786A JPS62272539A (en) 1986-05-20 1986-05-20 Removing method for resist

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11643786A JPS62272539A (en) 1986-05-20 1986-05-20 Removing method for resist

Publications (1)

Publication Number Publication Date
JPS62272539A true JPS62272539A (en) 1987-11-26

Family

ID=14687084

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11643786A Pending JPS62272539A (en) 1986-05-20 1986-05-20 Removing method for resist

Country Status (1)

Country Link
JP (1) JPS62272539A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01248607A (en) * 1988-03-30 1989-10-04 Matsushita Electric Ind Co Ltd Film capacitor and method and apparatus for manufacturing the same
JPH02134805A (en) * 1988-11-16 1990-05-23 Matsushita Electric Ind Co Ltd Film capacitor and manufacture of the same
JPH0334511A (en) * 1989-06-30 1991-02-14 Matsushita Electric Ind Co Ltd Manufacture of film capacitor
JPH0362911A (en) * 1989-07-31 1991-03-19 Matsushita Electric Ind Co Ltd Metallized film capacitor and manufacture thereof
US5310703A (en) * 1987-12-01 1994-05-10 U.S. Philips Corporation Method of manufacturing a semiconductor device, in which photoresist on a silicon oxide layer on a semiconductor substrate is stripped using an oxygen plasma afterglow and a biased substrate
JP2010056332A (en) * 2008-08-28 2010-03-11 Iwatani Internatl Corp Apparatus and method for processing semiconductor

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5310703A (en) * 1987-12-01 1994-05-10 U.S. Philips Corporation Method of manufacturing a semiconductor device, in which photoresist on a silicon oxide layer on a semiconductor substrate is stripped using an oxygen plasma afterglow and a biased substrate
JPH01248607A (en) * 1988-03-30 1989-10-04 Matsushita Electric Ind Co Ltd Film capacitor and method and apparatus for manufacturing the same
JPH02134805A (en) * 1988-11-16 1990-05-23 Matsushita Electric Ind Co Ltd Film capacitor and manufacture of the same
JPH0334511A (en) * 1989-06-30 1991-02-14 Matsushita Electric Ind Co Ltd Manufacture of film capacitor
JPH0362911A (en) * 1989-07-31 1991-03-19 Matsushita Electric Ind Co Ltd Metallized film capacitor and manufacture thereof
JP2010056332A (en) * 2008-08-28 2010-03-11 Iwatani Internatl Corp Apparatus and method for processing semiconductor

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