JPH08306670A - Plasma ashing device - Google Patents

Abstract

PURPOSE: To provide a new plasma ashing device which can completely peel a photoresist layer and moreover prevent the photoresist layer from being contaminated with Na. CONSTITUTION: This plasma ashing device is provided with a chamber 12, a cylindrical part 14, which extends upward from the top of the chamber, an RF power supply 16 of an output of 1000W and a wafer stage 18, which is provided under the bottom of the chamber and has a wafer stage 20, which is placed with a wafer W, on its upper surface. The height of the chamber is low compared with that of the chamber of a prior art plasma ashing device. An RF voltage applying electrode plate 26 and a ground electrode 28 are provided on the cylindrical wall of the part 14 in opposition to each other. The plate 26 extends downward in a short length from the upper part of the part 14 in the longitudinal direction and the length of the plate 26 is shorter than that of an electrode provided in a prior art down flow-system device. A plurality of ground lines are connected with the rear of the wafer stage 20 in such a way that the connection positions of the ground lines with the rear become an even distribution.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma ashing apparatus, and more particularly, to ashing a wafer having a photoresist layer into which P or As is ion-implanted at a high dose or a photoresist layer subjected to dry etching, to prevent Na contamination. The present invention relates to a plasma ashing device having a novel structure capable of preventing the generation of the photoresist layer and surely removing the photoresist layer.

[0002]

2. Description of the Related Art A plasma ashing process is a process for removing a photoresist used for patterning in a dry state by using a plasma ashing device in order to minimize damage to a wafer due to the ashing process. Typical examples of the conventional plasma ashing apparatus are a parallel plate type plasma ashing apparatus as shown in FIG. 2 in the RIE mode and an RF downflow plasma ashing apparatus as shown in FIG. 3 in the downflow mode.

[0003]

By the way, when an attempt is made to remove the photoresist hardened layer by only one ashing process, if an RIE mode plasma ashing device is used, the ashing is mainly O ₂ ions, and the photoresist hardening is performed. The layers can be stripped off satisfactorily, but can lead to Na contamination and damage to the wafer in the areas patterned by the photoresist. Also, RI
When an attempt is made to remove the photoresist hardened layer by using an RF downflow plasma ashing device in a downflow mode instead of the E mode plasma ashing device, ashing mainly consisting of O ₂ radicals occurs and Na
Contamination can be prevented, but since ashing is performed in a state where the wafer temperature is relatively high, a popping phenomenon may occur in the photoresist film, making it difficult to completely remove the photoresist, resulting in a photoresist residue.

There is also a method of removing the photoresist hardened layer by dividing the ashing treatment into two or more times. In that case, the first
In the second ashing process, the plasma ashing device of RIE mode or RF bias mode is used to perform half ashing mainly with O ₂ ions, and in the second and subsequent ashing processes, the remaining photoresist is used by using the plasma ashing device of downflow mode. Is generally peeled off. However, even in this case, in the first ashing process (half ashing), since the ashing is mainly performed with O ₂ ions, the peeling of the photoresist is almost complete,
Although Na contamination in the region of the photoresist layer is also prevented, the region without the photoresist layer or the edge region of the resist pattern is exposed to O ₂ ions, so Na contamination or damage occurs.

Na contamination is caused by Na contained in the photoresist.
Although but believed to result to penetrate the oxide film and the like, O in ₂ ion main ashing, O by ₂ ions undergo oxidation film or the like is damaged, and since the Na enters in association with the O ₂ ions Moreover, Na contamination is considered to be significant. Due to Na contamination, V _TH fluctuates and device stability is impaired. The above problems are particularly remarkable in the ashing of the photoresist layer in which P or As is ion-implanted at a high dose or the photoresist layer in which dry etching is performed.

In view of the above problems, the object of the present invention is to
It is an object of the present invention to provide a plasma ashing device having a novel structure in which the photoresist layer is completely peeled off and Na contamination can be prevented.

[0007]

In developing the improved plasma ashing apparatus, the inventor of the present invention found out the following in the course of research through various experiments. 1) When the photoresist hardened layer is peeled off, unless the ashing is performed at a temperature lower than the post-baking temperature of the photoresist, a popping phenomenon occurs, and there is a high possibility that a photoresist residue will be generated even after an acid treatment such as sulfuric acid / hydrogen peroxide mixture. For that purpose, it is necessary to perform ashing at a low temperature. 2) Even if an attempt is made to remove the photoresist hardened layer by ashing mainly composed of O ₂ radicals, the ashing rate is low and low temperature ashing cannot be carried out. Therefore, ashing mainly based on O ₂ ions, which enables low temperature ashing, should be performed. However, ashing mainly composed of O ₂ ions may cause Na contamination. 3) Then, ashing is mainly performed with O ₂ ions to remove the photoresist hardened layer, and then ashing with O ₂ radicals is performed to completely remove the remaining portion of the photoresist so that Na contamination is not generated. Further, at this time, even if high temperature ashing is performed, since the layered photoresist does not exist, the popping phenomenon does not occur.

In order to achieve the above object, based on the above findings, the plasma ashing apparatus according to the present invention is provided with an electrode for mounting a wafer on the bottom, and the distance from the electrode to the top is formed to be relatively short. Further, it has an ashing chamber that is vacuum-sucked to a predetermined pressure and an inlet for the reaction gas in the upper part, and communicates with the top of the chamber in the lower part to allow the introduced reaction gas to flow toward the electrode in the chamber. Thus, a cylindrical portion extending upward from the top of the ashing chamber, an RF power source, and an RF voltage applying electrode plate that is provided along the cylindrical wall of the cylindrical portion and that descends shortly in the longitudinal direction from the upper portion of the cylindrical portion, A pair with a ground electrode that is provided along the cylindrical wall of the cylindrical portion facing the RF voltage applying electrode plate and extends downward from the upper portion of the cylindrical portion in the longitudinal direction longer than the lower end of the RF voltage applying electrode plate. Counter electrodes to be formed, a plurality of ground lines connected to the back surface of the stage facing the electrode surface of the wafer stage on which the electrodes are mounted in an even distribution, and a vacuum exhaust means for vacuuming the reaction gas in the chamber. It is characterized by having.

In the present invention, the materials of the ashing chamber, the cylindrical portion, the electrodes, etc. are the same as those used in the conventional downflow type plasma ashing apparatus. The present invention can be applied to a plasma ashing apparatus regardless of the type of ashing gas used in the ashing process and the type of photoresist to be ashed.

[0010]

In the present invention, the distance from the wafer stage surface to the top of the ashing chamber (the height of the ashing chamber) is relatively shorter than the distance from the wafer stage surface of the conventional downflow type ashing chamber to the top of the ashing chamber. The amount of O ₂ radical reaching the wafer can be increased by, for example, reducing the amount to about ½, thereby increasing the ashing rate. R
The F voltage application electrode plate is shorter than that of the conventional downflow type plasma ashing device, for example, 1 of the conventional length.
1/2, and by increasing the distance between the wafer stage surface and the RF voltage application electrode plate, the amount of O ₂ ions reaching the wafer stage surface can be reduced and the amount of O ₂ radicals can be relatively increased. it can. With the above configuration, the downflow mode and the RF bias mode can be realized simultaneously in the same device, and the RF output is increased, and further, the degree of vacuum and the stage temperature are adjusted so that O ₂ ions and O ₂ ions can be generated.
₂ The quantitative balance of radicals can be adjusted.
This makes it possible to prevent Na contamination and prevent damage. That is, ashing mainly with O ₂ ions is performed in the RF bias mode to remove the photoresist hardened layer, and thereafter ashing mainly with O ₂ radicals is performed in the downflow mode so that Na contamination is not generated and the remaining portion of the photoresist is completely removed. To remove.

Further, the output of the RF power source is at least 700.
By setting W, the O ₂ radical density can be increased and the ashing rate can be increased. As a result, the photoresist after high-dose ion implantation can be surely removed even by ashing at low temperature. Further, in the conventional plasma ashing system in which the ground line is connected only to the central portion of the wafer stage when ashing the photoresist hardened layer after the ion implantation, a potential distribution is generated on the wafer stage surface, and The distribution of O ₂ ions reaching the wafer surface is not uniform. Therefore, the uniformity of ashing is impaired. Further, if the ground line is provided only in the peripheral portion of the wafer stage, the amount of O ₂ ions reaching the wafer surface decreases, and the peeling ability of the hardened photoresist layer decreases. Therefore, in the present invention, not only the central portion of the back surface of the wafer stage but also the ground line is provided so as to have a uniform distribution over the entire back surface so that no potential distribution occurs on the wafer stage surface.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in more detail with reference to the accompanying drawings. FIG. 1 is a schematic diagram showing the configuration of an embodiment of a plasma ashing device according to the present invention. As shown in FIG. 1, the plasma ashing apparatus 10 of the present embodiment (hereinafter simply referred to as apparatus 10) has an ashing chamber 12, a cylindrical portion 14 extending upward from the top of the ashing chamber 12, and an output of 1000 W. An RF power supply 16 and a wafer stage 18 provided at the bottom of the ashing chamber 12 are provided. Wafer stage 1
8 has a wafer stage surface 20 on which the wafer W is placed on its upper surface.

The ashing chamber 12 has a diameter of about 30.
In cm, the distance H (the height of the ashing chamber 12) from the wafer stage surface 20 of the wafer stage 18 to the top 22 is lower than the height H '(see FIG. 3) of the ashing chamber of the conventional plasma ashing apparatus. There is.
For example, the height of the ashing chamber 12 of the apparatus 10 is 1 cm compared to the height of the conventional ashing chamber of 20 cm.
It is about 1/2 at 0 cm. Ashing chamber 12
Is vacuum-sucked by a vacuum suction device (not shown) and maintained at a predetermined pressure.

The cylindrical portion 14 has an inlet 24 for the reaction gas in the upper portion and a top portion 22 of the ashing chamber 12 in the lower portion.
Communicating with the ashing chamber 1
2 extends upward from the top 22 of the ashing chamber 12 so as to flow toward the wafer stage surface 20. The cylindrical wall of the cylindrical portion 14 has RF along the cylindrical wall.
A voltage application electrode plate 26 and a ground electrode 28 are provided so as to face each other. The RF voltage application electrode plate 26 extends from the upper part of the cylindrical portion 14 along the cylindrical wall downward in the longitudinal direction for a short time, and its length L (see FIG. 1) is equivalent to that of a conventional downflow type plasma ashing apparatus. It is 15 cm, which is about ½ of the length of the electrode (see E in FIG. 3) provided. On the other hand, the ground electrode 28 faces the RF voltage application electrode plate 26 and faces the cylindrical portion 1
The RF voltage applying electrode plate 26 is provided along the cylindrical wall of FIG.
Extends downwardly longer than the lower end of.

On the back surface of the wafer stage 20, a plurality of ground lines 30 are connected so that the distribution of connection positions is uniform.

The apparatus 10 of this embodiment was used to evaluate the present invention. Experimental Example 1 High-dose ion implantation (P is 70 KeV, 1 × 10 ¹⁶
/ Cm ² ) A wafer having a photoresist layer was used as a sample, and an ashing process was performed under the following conditions. RF output: 700W Pressure: 100Pa Stage temperature: 80 ° C Reactant gas flow rate: Oxygen gas, 500sccm Ashing time: 220sec When the processed sample wafer was inspected, Na contamination was hardly generated and the photoresist layer was completely peeled off. Was.

Experimental Example 2 Ion implantation was performed at a high dose (P was 70 KeV, 1 × 10 ¹⁶
/ Cm ² ) A wafer having a photoresist layer was used as a sample, and the primary ashing treatment and the secondary ashing treatment were performed under the following conditions. Primary ashing condition RF output: 700W Pressure: 100Pa Stage temperature: 80 ° C Reaction gas flow rate: Oxygen gas, 500sccm Ashing time: 180sec Secondary ashing condition RF output: 400W Pressure: 100Pa Stage temperature: 80 ° C Reaction Gas flow rate: oxygen gas, 500 sccm ashing time: 120 sec

In Experimental Example 2, until the photoresist hardened layer was peeled off, ashing mainly with O ₂ ions was performed with an RF output of 700 W, and thereafter, RF output was lowered to 400 W and ashing mainly with O ₂ radicals was performed. The rest of the photoresist is removed and Na contamination is completely prevented. When the processed sample wafer was inspected, Na contamination was almost completely prevented, and the photoresist layer was also completely peeled off.

[0019]

According to the structure of the present invention, by providing the ashing chamber having a low height and the counter electrode having the ground electrode and the RF voltage applying electrode plate having a short length, P, As, etc. can be increased. When ashing a wafer having a dose-implanted photoresist layer or a dry-etched photoresist layer, a plasma ashing device has been realized which can prevent Na contamination and can almost completely strip the photoresist layer. By using the plasma ashing device according to the present invention, Na contamination and damage are prevented, so that the characteristics of the semiconductor device are stabilized and the product yield of the semiconductor device can be improved.

[Brief description of drawings]

FIG. 1 is a schematic diagram showing a configuration of an embodiment of a plasma ashing device according to the present invention.

FIG. 2 is a schematic diagram showing a configuration of a parallel plate type plasma ashing apparatus of RIE mode.

FIG. 3 is a schematic diagram showing a configuration of an RF downflow plasma ashing device in a downflow mode.

[Explanation of symbols]

 10 Examples of plasma ashing apparatus according to the present invention 12 Ashing chamber 14 Cylindrical part 16 RF power source 18 Wafer stage 20 Wafer stage surface 22 Top part of ashing chamber 24 Reactant gas inlet port 26 RF voltage application electrode plate 28 Ground electrode 30 Ground line

Claims (3)

[Claims] 1. A wafer stage having a wafer stage surface on which a wafer is placed on an upper surface is provided at a bottom portion, a distance from the wafer stage surface to a top portion is formed relatively short, and vacuum suction is performed to a predetermined pressure. It has an ashing chamber and a reaction gas inlet at the top, and communicates with the top of the chamber at the bottom, so that the introduced reaction gas flows upward from the top of the ashing chamber so as to flow toward the wafer stage surface in the chamber. An extending cylindrical portion, an RF power source, an RF voltage applying electrode plate provided along the cylindrical wall of the cylindrical portion, and extending shortly in the longitudinal direction downward from the upper portion of the cylindrical portion,
The pair of ground electrodes are provided along the cylindrical wall of the cylindrical portion facing the RF voltage applying electrode plate and extend downward from the upper portion of the cylindrical portion in the longitudinal direction longer than the lower end of the RF voltage applying electrode plate. A plasma ashing device, comprising: a counter electrode which is provided with a counter electrode; 2. The output of the RF power supply is at least 700.
The plasma ashing device according to claim 1, wherein the plasma ashing device is W. 3. The plasma ashing device according to claim 1, wherein a plurality of ground lines are connected to the back surface of the wafer stage facing the wafer stage surface of the wafer stage in a uniform distribution.