JPH01112732A - Ashing or resist - Google Patents
Ashing or resistInfo
- Publication number
- JPH01112732A JPH01112732A JP27130687A JP27130687A JPH01112732A JP H01112732 A JPH01112732 A JP H01112732A JP 27130687 A JP27130687 A JP 27130687A JP 27130687 A JP27130687 A JP 27130687A JP H01112732 A JPH01112732 A JP H01112732A
- Authority
- JP
- Japan
- Prior art keywords
- resist layer
- plasma
- implanted
- substrate
- gas
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004380 ashing Methods 0.000 title claims description 22
- 238000000034 method Methods 0.000 claims abstract description 22
- 239000012535 impurity Substances 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 150000002500 ions Chemical class 0.000 claims abstract description 18
- 230000007935 neutral effect Effects 0.000 claims abstract description 8
- 239000007789 gas Substances 0.000 abstract description 19
- 229910052796 boron Inorganic materials 0.000 abstract description 7
- 229910052785 arsenic Inorganic materials 0.000 abstract description 6
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 6
- 239000000126 substance Substances 0.000 abstract description 6
- 125000004430 oxygen atom Chemical group O* 0.000 abstract description 5
- 125000004435 hydrogen atom Chemical group [H]* 0.000 abstract description 3
- 238000005468 ion implantation Methods 0.000 abstract description 3
- 238000010494 dissociation reaction Methods 0.000 abstract description 2
- 230000005593 dissociations Effects 0.000 abstract description 2
- 239000000470 constituent Substances 0.000 abstract 2
- 239000000203 mixture Substances 0.000 abstract 1
- 230000035515 penetration Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 24
- 238000004519 manufacturing process Methods 0.000 description 7
- 239000004065 semiconductor Substances 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 230000005540 biological transmission Effects 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 3
- 238000001816 cooling Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 2
- 229910001882 dioxygen Inorganic materials 0.000 description 2
- 239000012495 reaction gas Substances 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 101100215641 Aeromonas salmonicida ash3 gene Proteins 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000011247 coating layer Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 239000007790 solid phase Substances 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔概 要〕
半導体装置の製造工程において用いられるダウンフロ一
方式のアッシング方法に関し。DETAILED DESCRIPTION OF THE INVENTION [Summary] This invention relates to a down-flow ashing method used in the manufacturing process of semiconductor devices.
レジスト層に注入された不純物イオンを残すことなくレ
ジスト層をアッシング除去可能とする方法を提供するこ
とを目的とし。The object of the present invention is to provide a method that allows a resist layer to be removed by ashing without leaving impurity ions implanted in the resist layer.
ダウンフロ一方式のアッシング装置におけるプラズマ発
生室に02ガスを主成分としHlを副成分とする混合ガ
スを導入して該混合ガスのプラズマを発生し、被処理基
板に塗布されたレジスト層ならびにレジスト層に注入さ
れた不純物イオンを選択的に除去することから構成され
る。A mixed gas containing 02 gas as a main component and Hl as a subcomponent is introduced into the plasma generation chamber of a down-flow one-type ashing apparatus, and a plasma of the mixed gas is generated to form a resist layer and a resist layer coated on a substrate to be processed. It consists of selectively removing impurity ions implanted into the
本発明は半導体装置の製造工程において用いられるレジ
スト塗布層の除去方法に係り、とくにダウンフロ一方式
のアッシング方法に関する。The present invention relates to a method for removing a resist coating layer used in the manufacturing process of a semiconductor device, and particularly relates to a down-flow one-type ashing method.
半導体装置の微細化にともなって製造工程の乾式化が進
められている。リングラフィ工程においてマスクとして
用いられたレジスト層の除去についても溶剤による湿式
除去に代わって、レジスト層を固相・気相反応で除去す
るアッシングと呼ばれる乾式方法が用いられている。With the miniaturization of semiconductor devices, the manufacturing process is becoming increasingly dry. Regarding the removal of the resist layer used as a mask in the phosphorography process, instead of wet removal using a solvent, a dry method called ashing is used in which the resist layer is removed by solid phase/vapor phase reaction.
乾式除去方法においては、酸素ガスのプラズマを発生し
、このプラズマ中に含まれる原子状の酸素とレジスト層
との反応を利用する。このアッシング方法のうちには、
荷電粒子の衝突による基板の損傷を避けるために、被処
理基板を設置する場所をプラズマを発生する場所とを分
離し、プラズマ中のイオンあるいは電子等が被処理基板
に到達しないような手段を設けた装置を用いるいわゆる
ダウンフロ一方式の方法がある。In the dry removal method, an oxygen gas plasma is generated and a reaction between atomic oxygen contained in the plasma and the resist layer is utilized. Among this ashing method,
In order to avoid damage to the substrate due to collisions with charged particles, the place where the substrate to be processed is installed is separated from the place where the plasma is generated, and measures are taken to prevent ions, electrons, etc. in the plasma from reaching the substrate to be processed. There is a so-called down-flow one-way method that uses a similar device.
ダウンフロ一方式のレジスト層除去における反応ガスは
一般に酸素ガスを主成分とするが、中性酸素原子(0)
の生成効率を高めるために、少量の副成分ガスを添加す
ることが行われている。このダウンフロ一方式のアッシ
ングにおいては、有機物であるレジスト層は酸素原子と
化学反応を起こし、 COtおよび■20等の揮発性物
質に変えられて除去される。The reactive gas in resist layer removal using the down-flow one-way method generally has oxygen gas as its main component, but neutral oxygen atoms (0)
In order to increase the production efficiency, small amounts of subcomponent gases are added. In this down-flow type ashing, the organic resist layer undergoes a chemical reaction with oxygen atoms, is converted into volatile substances such as COt and 20, and is removed.
一方1通常の半導体装置の製造工程においては。On the other hand, 1. In the normal semiconductor device manufacturing process.
シリコンウェハ等の被処理基板に塗布形成されているレ
ジスト層にも、被処理基板に注入される不純物イオンが
同時に注入される。一般に不純物として注入される硼素
(B) 、 ta (P) 、砒素(八3)等はアッシ
ング工程において不揮発性の酸化物を形成するために、
レジスト層と同時に除去されず。Impurity ions to be implanted into the substrate to be processed are simultaneously implanted into a resist layer coated on the substrate to be processed, such as a silicon wafer. Generally, boron (B), ta (P), arsenic (83), etc., which are implanted as impurities, form nonvolatile oxides in the ashing process.
Not removed at the same time as the resist layer.
レジスト層除去後の被処理基板表面に残る。このような
残留不純物は、以後の熱処理工程において被処理基板に
拡散し、ここに形成されるトランジスタ等の素子特性に
好ましくない影響を与える。It remains on the surface of the substrate to be processed after the resist layer is removed. Such residual impurities diffuse into the substrate to be processed in the subsequent heat treatment process, and have an undesirable effect on the characteristics of devices such as transistors formed therein.
とくに、半導体装置の微細化部ともなって高ドーズ量の
イオン注入が行われる傾向にあり、アッシング後の残留
不純物の影響は大きくなる。In particular, there is a tendency for high-dose ion implantation to be performed as semiconductor devices become smaller, and the influence of residual impurities after ashing increases.
本発明はダウンフロ一方式によるレジストのアッシング
において上記の問題が生じない方法を提供することを目
的とする。An object of the present invention is to provide a method that does not cause the above-mentioned problems in resist ashing using a down-flow method.
上記の目的は、ダウンフロ一方式のレジストアッシング
方法において、処理室にレジスト層が形成された被処理
基板を設置し、プラズマ発生室に0□ガスを主成分とし
H2を副成分とする混合ガスを導入して該混合ガスのプ
ラズマを発生し、該レジスト層ならびに該レジスト層に
注入された不純物イオンを選択的に除去することを特徴
とする9本発明に係るレジストのアッシング方法により
達成される。The above purpose is to install a substrate on which a resist layer is formed in a processing chamber in a down-flow one-type resist ashing method, and to supply a mixed gas containing 0□ gas as a main component and H2 as a subcomponent in a plasma generation chamber. This is achieved by the resist ashing method according to the present invention, which is characterized in that the resist layer and the impurity ions implanted into the resist layer are selectively removed by introducing the mixed gas and generating plasma of the mixed gas.
ダウンフロ一方式のアッシングにおいて、0□ガスに副
成分としてH2を添加することにより、イオン注入工程
においてレジスト層に注入されたB。In the down-flow one-type ashing, B is implanted into the resist layer in the ion implantation process by adding H2 as a subcomponent to the 0□ gas.
P+As等の不純物を揮発性の物質に変えてレジスト層
と同時に除去する。Impurities such as P+As are converted into volatile substances and removed at the same time as the resist layer.
以下本発明の実施例を図面を参照して説明する。 Embodiments of the present invention will be described below with reference to the drawings.
第1図は本発明を実施するために用いられたダウンフロ
一方式のアッシング装置の模式的断面図である。真空容
器1の内部は、シャワーヘッド2によってプラズマ発生
室3と処理室4とに分離されている。プラズマ発生室3
には反応ガスを導入するための導入管5と反応ガスのプ
ラズマを発生させるためのマイクロ波発生源6に接続さ
れたマイクロ波導入管7が設けられている。FIG. 1 is a schematic cross-sectional view of a down-flow type ashing device used to carry out the present invention. The inside of the vacuum container 1 is separated into a plasma generation chamber 3 and a processing chamber 4 by a shower head 2. Plasma generation chamber 3
An introduction pipe 5 for introducing a reaction gas and a microwave introduction pipe 7 connected to a microwave generation source 6 for generating plasma of the reaction gas are provided.
マイクロ波導入管7には2例えば石英ガラス板から成る
マイクロ波透過窓8と、該マイクロ波透過窓8を冷却す
るための水冷フランジ9が取りつけられている。一方、
処理室4には真空容器1内を所定の低圧に保持するため
の排気系に接続された排気管10が設けられており、ま
た、処理室4の底面にはレジスト層が塗布されたシリコ
ンウェハ等の被処理基板11を載置するための温度制御
が可能ナステージ13が設置されている。シャワーへフ
ド2は接地電位に保持されており、また貫通する小孔1
2が多数設けられている。The microwave introduction tube 7 is provided with a microwave transmission window 8 made of, for example, a quartz glass plate, and a water cooling flange 9 for cooling the microwave transmission window 8. on the other hand,
The processing chamber 4 is provided with an exhaust pipe 10 connected to an exhaust system for maintaining the inside of the vacuum container 1 at a predetermined low pressure, and the bottom of the processing chamber 4 is equipped with a silicon wafer coated with a resist layer. A temperature controllable stage 13 is installed on which a substrate 11 to be processed such as the like is placed. The shower head 2 is held at ground potential and has a small hole 1 passing through it.
2 are provided in large numbers.
上記の装置を用いて下記の工程によりアッシングを行う
。Ashing is performed using the above-mentioned apparatus according to the following steps.
■ステージ13上に2例えば1xlO”ないし1x10
″原子/dの比較的高ドーズ量のB、P、As等の不純
物イオンが注入されたレジスト層が形成されているシリ
コンウェハのような被処理基板1を!!置する。■2 such as 1xlO” or 1x10 on stage 13
A substrate 1 to be processed, such as a silicon wafer, is placed on which a resist layer in which impurity ions such as B, P, and As are implanted at a relatively high dose of ``atoms/d'' is formed.
■排気管10を通じて真空容器1の内部を真空に排気し
たのち、al入管5から1〜10%程度のH2を含むO
2+H,系の混合ガスを所定の流量で導入する。■After evacuating the inside of the vacuum container 1 through the exhaust pipe 10, O2 containing about 1 to 10% H
2+H, system mixed gas is introduced at a predetermined flow rate.
この時のプラズマ発生室3内におけるガス圧が約1.0
Torrとなるように制御する。At this time, the gas pressure in the plasma generation chamber 3 is approximately 1.0
Torr.
■マイクロ波発生源6を起動し、マイクロ波透過窓8を
通してプラズマ発生室3内の混合ガスにマイクロ波を照
射し、プラズマを発生させる。なお、マイクロの周波数
およびパワーの一例は、それぞれ、 2.45GHzお
よび1.5KMである。(2) Start up the microwave source 6 and irradiate the mixed gas in the plasma generation chamber 3 with microwaves through the microwave transmission window 8 to generate plasma. Note that examples of the frequency and power of the micro are 2.45 GHz and 1.5 KM, respectively.
上記のようにして発生されたプラズマ中のイオン、電子
はシャワーヘッド2に衝突して電荷を失うために、処理
室4内にはイオンあるいは電子が入らず、被処理基板に
好ましくない損傷を生じない。一方、プラズマ中の中性
の酸素原子(o)、 82分子が解離して生じた中性の
水素原子(H)等は拡散してシャワーヘッド2の小孔1
2を通過し処理室4に入り、被処理基板11に塗布され
ているレジスト層および該レジスト層に注入されている
B、P。The ions and electrons in the plasma generated as described above collide with the shower head 2 and lose their charge, so the ions and electrons do not enter the processing chamber 4, causing undesirable damage to the substrate to be processed. do not have. On the other hand, neutral oxygen atoms (o) in the plasma, neutral hydrogen atoms (H) generated by dissociation of 82 molecules, etc. diffuse into the small hole 1 of the shower head 2.
2 and enters the processing chamber 4, the resist layer coated on the substrate 11 to be processed and the B and P injected into the resist layer.
As等の不純物イオンと反応する。その結果、上記の不
純物イオンはレジスト層と共に揮発性の物質として排気
管10を通じて除去される。Reacts with impurity ions such as As. As a result, the impurity ions mentioned above are removed together with the resist layer as volatile substances through the exhaust pipe 10.
0!ガスにH2を添加するとプラズマ中の中性酸素原子
の量がOtガス単独の場合よりも増加し、レジストのア
ッシングレートが増大することが確かめられている。一
方、上記B、P、As等の不純物イオンが揮発性の物質
に変換されるのは、プラズマ中のH2から生成した中性
の水素原子(H)がこれらの不純物イオンと反応し+
RtHb* PHz+ ASH3等の気体分子を生成す
るためと考えられる。0! It has been confirmed that when H2 is added to the gas, the amount of neutral oxygen atoms in the plasma increases compared to when Ot gas is used alone, and the ashing rate of the resist increases. On the other hand, impurity ions such as B, P, and As are converted into volatile substances when neutral hydrogen atoms (H) generated from H2 in the plasma react with these impurity ions.
This is thought to be due to the generation of gas molecules such as RtHb*PHz+ASH3.
本発明によれば、シリコンウェハのような被処理基板に
形成されたレジスト層のアッシング工程において、該レ
ジスト層に注入されている不純物イオンを同時に除去で
きるので、所望の特性を有する高集積半導体装置を高歩
留りで製造可能とする効果がある。According to the present invention, in the ashing process of a resist layer formed on a substrate to be processed such as a silicon wafer, impurity ions implanted into the resist layer can be removed at the same time, resulting in a highly integrated semiconductor device having desired characteristics. This has the effect of making it possible to manufacture with high yield.
第1図は本発明の実施に用いたダウンフロ一方式のアッ
シング装置の構造を示す模式的断面図である。
図において。
1は真空容器。
2はシャワーヘッド。
3はプラズマ発生室。
4は処理室。
5は導入管。
6はマイクロ波発生源。
7はマイクロ波導入管。
8はマイクロ波透過窓。
9は水冷フランジ。
10は排気管。
11は被処理基板。
12は小孔。
13はステージ
であ邊。FIG. 1 is a schematic cross-sectional view showing the structure of a down-flow type ashing device used in carrying out the present invention. In fig. 1 is a vacuum container. 2 is the shower head. 3 is the plasma generation chamber. 4 is the processing room. 5 is the introduction pipe. 6 is a microwave generation source. 7 is a microwave introduction tube. 8 is a microwave transmission window. 9 is a water cooling flange. 10 is the exhaust pipe. 11 is a substrate to be processed. 12 is a small hole. 13 is by the stage.
Claims (1)
せるプラズマ発生室と、真空に排気され、被処理基板が
設置される処理室と、該プラズマ中の中性種を該プラズ
マ発生室から該処理室に選択的に通過させる手段とを備
えたアッシング装置における該処理室に、不純物イオン
の注入を受けたレジスト層が形成された被処理基板を設
置し、該プラズマ発生室にO_2ガスを主成分としH_
2を副成分とする混合ガスを導入して該混合ガスのプラ
ズマを発生し、該レジスト層ならびに該レジスト層に注
入された不純物イオンを選択的に除去することを特徴と
するレジストのアッシング方法。A plasma generation chamber into which a reactive gas is introduced and generates a plasma of the reactive gas, a processing chamber which is evacuated to vacuum and where a substrate to be processed is installed, and a process chamber in which neutral species in the plasma are removed from the plasma generation chamber to the processing chamber. A substrate to be processed on which a resist layer implanted with impurity ions is formed is installed in the processing chamber of an ashing apparatus equipped with a means for selectively passing through the ashing chamber, and O_2 gas as a main component is placed in the plasma generation chamber. Toshi H_
1. A method for ashing a resist, which method comprises introducing a mixed gas containing 2 as a subcomponent to generate plasma of the mixed gas to selectively remove the resist layer and impurity ions implanted into the resist layer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP27130687A JPH01112732A (en) | 1987-10-27 | 1987-10-27 | Ashing or resist |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP27130687A JPH01112732A (en) | 1987-10-27 | 1987-10-27 | Ashing or resist |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH01112732A true JPH01112732A (en) | 1989-05-01 |
Family
ID=17498209
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP27130687A Pending JPH01112732A (en) | 1987-10-27 | 1987-10-27 | Ashing or resist |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH01112732A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02263436A (en) * | 1989-04-03 | 1990-10-26 | Mitsubishi Electric Corp | Generating method of active chemical species and manufacture of electronic member material |
WO2009085965A1 (en) * | 2007-12-21 | 2009-07-09 | Applied Materials, Inc. | Removal of surface dopants from a substrate |
-
1987
- 1987-10-27 JP JP27130687A patent/JPH01112732A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02263436A (en) * | 1989-04-03 | 1990-10-26 | Mitsubishi Electric Corp | Generating method of active chemical species and manufacture of electronic member material |
WO2009085965A1 (en) * | 2007-12-21 | 2009-07-09 | Applied Materials, Inc. | Removal of surface dopants from a substrate |
US7989329B2 (en) | 2007-12-21 | 2011-08-02 | Applied Materials, Inc. | Removal of surface dopants from a substrate |
JP2012104841A (en) * | 2007-12-21 | 2012-05-31 | Applied Materials Inc | Removal of surface dopant from substrate |
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