JPS62271429A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To improve the accuracy of alignment by a method wherein a mask for forming a source/drain diffused layer is used as a reference, a plurality of alignment patterns are formed in this mask, and subsequent mask patterns are superposed on the alignment patterns. CONSTITUTION:A means is adopted wherein a pattern as show in Fig. b' is superposed on a pattern formed as shown in Fig. a'. Moreover, a different shape is given for each mask alignment as patterns 1-8 of Figs. (a)-(d) so that positions of superposition can be discriminated distinctly according to shapes in a mask alignment process. These patterns 1-8 enables not only the mask alignment according to the outer side of a pattern, but also the mask alignment according to the inner side thereof, thus facilitating an operation for mask alignment and improving the accuracy of alignment.

Description

Detailed Description of the Invention 3. Detailed Description of the Invention [Field of Industrial Application] The present invention relates to the shape of a pattern for mask alignment and means for mask alignment in a semiconductor manufacturing process.

〔the purpose〕

An object of the present invention is to facilitate the mask alignment process in semiconductor manufacturing, reduce the mutual deviation between semiconductor constituent patterns accumulated in each mask alignment process, and improve the precision of manufacturing tools. Concerning an improved semiconductor manufacturing process.

[Prior art]

In general, in the mask matching process, a pattern as shown in Figure 1 is formed on the layer manufactured in the following process, and a pattern as shown in Figure 1 is included in the mask used in the process of forming the next layer. Alignment between each layer is achieved by overlapping patterns.

The shape of the pattern for mask matching in the conventional mask matching machine has the shapes shown in FIG. Mask alignment is performed by superimposing pattern 2 included in the second mask, and pattern 4 included in the third mask is superimposed on pattern 3, which is simultaneously formed on the semiconductor device by the second mask. Perform the mask alignment of the 3rd mask, and then perform the 4th mask alignment in the same manner. Mask alignment for the fifth class mask is being performed. However, when this method is used, all the mask alignment patterns in each mask alignment process have the same shape, so it becomes unclear to determine the mask alignment position in the factory work (comparison and confirmation with internal semiconductor configuration patterns). This results in a decrease in work efficiency.

On the other hand, as a preventive measure, a pattern for mask alignment is formed at the same location as shown in FIG. 3 in order to compensate for the drawbacks mentioned above.
A method is also used in which the pattern 10 included in the second mask is superimposed on the pattern 9 formed by the first mask, and the pattern 11 included in the 1g5 mask is sequentially superimposed on the pattern 10.

However, the mask alignment means simply performs the previous step aK.
Since mask alignment is performed based on the pattern formed by the used mask, errors due to misalignment that occur in each mask alignment as the manufacturing process progresses are accumulated.
The worst value of the cumulative error is (error caused by one mask alignment K) x (total number of masks - 1).

As a specific example, a part of the manufacturing process of a complementary MO8 field effect transistor will be described.

A complementary MO8 field effect transistor generally has a structure as shown in FIG. 4. To obtain the structure shown in FIG. 4, at least an N-channel substrate 13, a P-channel source/drain layer 14, and a An N diffusion layer 15 forming a channel source-drain, a gate insulating layer 16, a contact portion 17 between the diffusion layer and the metal electrode, a metal electrode 18, and an opening 7 on the input/output butt of the surface protection film. Since the N++ diffusion layer usually has a smaller diffusion coefficient than the P diffusion layer, it is assumed that the N++ diffusion layer is formed after the +P diffusion layer, and that each is formed in the above order.

[Problem that the invention seeks to solve]

As mentioned above, during mask alignment in the conventional complementary MO8 field effect transistor manufacturing process, the mask used in any manufacturing process is simply the mask alignment formed by the mask used one step before the process. The previous Fi3 M OS
When manufacturing a field effect transistor, the mask that serves as a reference for mask alignment when forming the P-channel source/drain diffusion faj4 is a mask having a pattern for forming the N-channel substrate 13; The standard for mask alignment when forming the layer 15 is a mask having a pattern for forming the P-channel source/drain diffusion layer 14, and the standard for mask alignment when forming the gate insulating layer 16 is the N-channel source/drain diffusion layer 14. A mask having a pattern forming layer 15. Since mask alignment is subsequently performed in the same manner for all knees using the mask used one step before the process as a reference, errors occurring in each mask alignment can be accumulated.

As an example, if we consider the case where the channel part consisting of the source/drain diffusion layer 14, gate insulating layer 16, and metal electrode 18 is arranged as shown in Figure 5 in terms of pattern design, the conventional mask alignment method ( d If a deviation occurs in one direction during each mask alignment process, the error due to the deviation will accumulate and cause the pattern design to be
As shown in the figure, it is not possible to obtain the considered overlap between the source/drain diffusion layer 14 and the metal electrode 1B, making it difficult to form a channel.

Therefore, in order to improve the semiconductor production yield, it is necessary to design a pattern with a margin in consideration of the cumulative error caused by poor alignment accuracy, which causes a decrease in the degree of integration and even a decrease in productivity. [Means for Solving the Problems] The present invention eliminates such drawbacks, and uses a mask having a pattern for forming a source/drain diffusion layer as a reference mask, and a pattern shape for mask alignment is subsequently formed on the reference mask. A method for manufacturing a semiconductor device, characterized in that a plurality of masks are formed corresponding to the number of masks, and each mask matching pattern included in subsequent masks is overlapped with each of the plurality of pattern shapes to perform mask matching. It provides:

〔Example〕

The present invention uses a pattern for mask alignment having a shape as shown in FIG. 8, and employs means for overlaying a pattern as shown in FIG. 9(A) on the pattern formed as shown in FIG.
By having a different shape for each mask alignment as shown in I (b) l (e), fd), and being able to clearly determine the amount of overlap with that shape in the mask alignment process, It improves the work efficiency of the vaginal process. Also, Figures 8 and 9 (Arashi) I fb), (6) l
The excellent shape of the pattern for mask alignment according to the present invention as shown in (d) allows mask alignment to be performed not only on the outer side of the pattern but also on the inner side, which makes the mask alignment operation easier. becomes easier,
Alignment accuracy also improves.

The shape of another mask matching pattern according to the present invention is in the form of a number as shown in FIG. By numbering the steps in the order of steps, it is easier to identify the alignment position in the mask alignment process, and at the same time, it is also possible to confirm the mask to be used. However, the same result can also be obtained by making the pattern not in the form of numbers but in the form of letters and using letters that indicate the type of mask.

Furthermore, the means for mask alignment according to the present invention in the manufacturing process of complementary MO6 field effect transistors is shown in FIG.
Using the patterns shown in a) to (d) or FIGS. The mask used to form the diffusion layer is aligned based on the pattern included in the mask for shaping the first N-channel substrate, and after the step of forming the N-channel source/drain diffusion layer. , @3 to seventh masks are all performed using the mask alignment pattern formed by the second mask as a reference. Therefore, the errors caused by the alignment operations in the steps 1 to 7 can be accumulated, and as a result, the alignment accuracy in manufacturing the transistor is improved, and there is no need to take an excessive V margin in the design. The degree of freedom in design increases, and the degree of Iff can be improved.

As a specific example, in the arrangement shown in the previous example shown in FIG. 5, when forming the gate insulating layer 16 as shown in FIG. This mask has a pattern for forming the layer 14, and also when forming the gold 11i'Q[18, since the mask having the pattern for forming the source/drain diffusion layer 14'5c is used as a reference, each Even if the maximum deviation occurs in the mask alignment process, the error due to the deviation will not accumulate, and if the design is designed with a margin for the error in the - times of nuclear machining, the desired pattern configuration can be obtained. I can do it.

Adopting the shape of the mask matching pattern according to the present invention,
Furthermore, in the production of complementary type, M O3 field effect transistors, the mask of Sentry 2 should be used as the standard for mask alignment ((this will improve the work efficiency of the mask alignment GK, improve the degree of integration, and further improve productivity). can be improved.

〔effect〕

As described above, the present invention is based on a mask for forming source/drain diffusion layers, a plurality of alignment patterns are formed on this mask, and subsequent mask patterns are arranged to overlap with the alignment patterns. Since patterning can be formed based on the entire source/drain diffusion layer, alignment accuracy is improved and there is no need to take excessive margins in the design, which can prevent errors caused by alignment operations from being accumulated. , the degree of freedom in design increases and the degree of integration can be improved.

[Brief explanation of the drawing]

FIGS. 1(a) and 1(b) show the shapes of conventional mask alignment patterns. FIGS. 2(&) to (c) are examples of conventional mask alignment methods. Figure 3 shows another row of conventional mask alignment methods. FIG. 4 is a diagram showing the breakdown of a general complementary MO3 field effect transistor. FIG. 5 shows a complementary MOS [
An example of a layout diagram of source/drain diffusion layers and gate metal in a channel part of a field effect transistor. Figure 6 shows
t4I,5 that was misaligned due to conventional mask alignment means
Figure 7 shows the channel part 0 in Figure 5 when using the mask matching means according to the present invention. Figure 9 +a) r +b) + (a) l td)F
i. Mask matching method with different shapes according to the present invention 〇@10 Figures (, ), (b). (c) and (d) are mask matching methods having numerical shapes according to the present invention. 1.9...Mask alignment pattern formed by first mask 2.5.10...Mask alignment pattern formed by second mask 4.5.11...Third mask Mask alignment pattern formed by &, 7.12...Mask alignment pattern 8 formed by the fourth mask...Mask alignment pattern 13 formed by the fifth mask...N channel Substrate 14...P+ forming P channel source/drain
Diffusion layer 15...N+ forming N channel source/drain
Diffusion Station 16...Gate? , R layer 17...Joint part 18 between the diffusion layer and metal electrode...Gold a
T-pole 19...Insulating layer or higher

Claims (1)

[Claims] In a method for manufacturing a semiconductor device forming a MOS transistor, a mask having a pattern for forming a source/drain diffusion layer is used as a reference mask, and a plurality of pattern shapes for mask alignment are formed on the reference mask in accordance with the number of subsequent masks. 1. A method of manufacturing a semiconductor device, wherein each mask matching pattern included in a subsequent mask is overlapped with each of the plurality of pattern shapes for mask matching.