JPS62262086A - Switching circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION A. Field of Industrial Application The present invention relates to a switching circuit, and is suitable for use in, for example, a display device using a cathode ray tube having a high resolution and a large screen.

B Summary of the Invention The present invention provides a switching circuit having a plurality of switching transistors connected in parallel with each other, by providing a balance transformer at the base, emitter, and collector of each switching transistor, so that switching losses are approximately equalized in each switching transistor. You can have them share the work.

C Conventional technology Air traffic control monitors, CAD/CAM (co
mputer aided design/coa+p
(Uter aided manufacturing)
A cathode ray tube (CRT) is used as a display device for graphics processing in computer monitors, etc., which has a high resolution and large screen (for example, a resolution of 2000 dots x 2000 dots and a size of 20 inches x 20 inches).
) is considered to be realized as a rask image.

In this way, when trying to realize an ultra-high definition display device using a CRT, the horizontal deflection frequency is, for example, 13
Since the frequency is very high, about 0 (kHz), and the horizontal deflection current needs to be large, for example, about 20 (A), a configuration that operates stably under these conditions as a switching means used in the horizontal deflection circuit is required. need to be applied.

The horizontal deflection circuit 1 of a CRT generally has the configuration shown in FIG. In FIG. 5, the oscillation output obtained at the output terminal of the oscillation circuit 2 by the horizontal synchronizing signal H, . 5 is subjected to a switching operation every horizontal period.

The horizontal deflection voltage V thus obtained at the collector of the horizontal output transistor 5 is sent to the horizontal deflection line 11, and as shown in FIG. in a pulse,
stand up. During this retrace section T□, a resonant current i is caused to flow from the horizontal deflection coil 6 to the resonant capacitor 7 (FIG. 6(A)). Subsequently, during the period T0 during which the damper diode 8 is turned on, a current 1. flows (FIG. 6(A)), and when it returns to O, the horizontal output transistor 5 is turned on for an on period T. An open current IC of H flows (FIG. 6(C)).

At this time, a linearly increasing horizontal deflection current i flows through the horizontal deflection coil 6 (FIG. 6(A)).

In FIG. 5, 9 is a figure 8 capacitor, and 10 is a horizontal output transformer.

By the way, when trying to drive a CRT with an ultra-high definition and large screen as described above using the horizontal deflection circuit shown in FIG.
Since a horizontal deflection frequency of about 130 (kHz) is required, the horizontal period H is 7.7 [μS] and the retrace interval TIE is about 1.6 [μS]. In addition, since the horizontal deflection voltage ve is approximately 1200 (Vp-p), an element with high withstand voltage is required as the horizontal output transistor. The current i required to flow.

A switching element that allows a large current of about tOCAp-p to flow is required.

Conventional power MOS field effect transistors (power MO3F
ET), and it is conceivable to use this to construct a switching circuit 15 as shown in FIG.

In general, a power MOS FET has a high switching speed, and since it is a majority carrier element, there is no minority carrier accumulation effect, so it has good high-speed switching characteristics.

However, when the breakdown voltage between the drain and the source of a power MOS FET is increased, the resistance when turned on increases in proportion to approximately the 2.5th power, so the horizontal deflection voltage V. There is a problem in that it is not possible to obtain a withstand voltage that can be applied to. In reality, the horizontal deflection voltage vc is about 1200 (vp-p), so the switching element has a voltage of 1500 (vp-p).
-P ) degree of withstand voltage is required, but in practical use
(VP-), and in this respect, it is still insufficient to use a power MO5FET as a switching element.

In addition to this, the power MOS FET has a fairly large resistance of about 3 [Ω] when it is turned on, so it is practical to limit the loss when it is turned on, and at the same time improve the horizontal linearity on the screen. , as shown in FIG. 7, a plurality of, for example, six FET elements -1 to M6
There is a problem in that it is unavoidable to apply a configuration in which the switching circuit 15 is connected in columns, and from this point, there is an unavoidable drawback that the number of elements in the switching circuit 15 becomes extremely large.

Conventionally, as a method to solve this problem, as shown in FIG. 8, a plurality of power switching bipolar transistors, for example two switching transistors
and Q2 are connected in parallel.
A method using

Bipolar transistors for power switching are generally driven to the saturation region during on-state operation, so the conductivity modulation effect works to lower the on-state voltage sufficiently, which has the advantage of reducing on-state loss. Motsu.

In addition, in the same way as used in high-frequency transistors, by using miniaturization technology to improve the multi-structure of the base and emitter, it is possible to obtain ultra-high-speed bipolar transistors whose lifetime can be controlled. Therefore, it is possible to obtain an ultrahigh-speed bipolar transistor with a withstand voltage of about 1500 [V] and a current of about 10 (A) when on, and by connecting a plurality of these in parallel, the number of elements can be reduced.

In the case of FIG. 8, switching transistors Q1 and Q2
The collectors of are connected in parallel to the horizontal deflection output line 11, and the emitters are grounded through a pair of windings Cot and C02 of the balance transformer BTO.

The balance transformer BTO winds a pair of coils COI and CO2 of identical specifications except for the opposite polarity to the transistors Q1 and Q2, so that the coils COI and CO2 are coupled with a sufficient degree of coupling, and thus the coils are drawn from the emitters of the transistors Q1 and Q2. It operates to equalize the currents flowing into each other.

That is, as shown in the equivalent circuit of FIG. 9, the sum of base currents i□, 1llffi and collector currents ic+ and ict is drawn from the emitters of switching transistors Ql and Q2, respectively, and flows into coils col and ict of balance transformer BTO, respectively. Flows to C02.

Therefore, when the balance of the currents flowing through COI and CO2 is about to be lost, the coils col and c.

2, the back electromotive force V and V! are respectively expressed by the following formulas. is generated, which is vz=-Vl (3
) to balance each other out.

As a result, the current flowing through the coils CO1 and CO2 is++
ic+ and imx+icz are im++ ic+= i
sz" icz ...... They are corrected to be equal to each other as shown in (4).

However, even if the currents drawn from the emitters of the switching transistors Q1 and Q2 are controlled to be approximately equal to each other in this way, it is not necessarily possible to make the base currents i□ and 10, ic+ and tex equal to each other, and i11+# i*z...
(5) ic+# ict −・
...When (6) occurs, the sharing of the switching loss becomes unbalanced and the switching transistor Q1
and/or may result in damage to Q2.

According to experiments, as shown in FIG. 10, when the switching transistors Q1 and Q2 perform switching operations, the manner in which the collector currents ic+ and tcz change, and the base current i□
It has been found that this results in an unbalanced operating state in which the manner of change of

The present invention has been made in consideration of the above points, and proposes a switching circuit that minimizes the number of switching elements and satisfies the requirements for high-speed switching operation, high withstand voltage, and low resistance for practical purposes. This is what I am trying to do.

E Means for Solving the Problem In order to solve this problem, in the present invention, a plurality of switching transistors QISQ2, Qll to Q13 made of bipolar transistors, and a plurality of switching transistors Ql, Q2, Qll to Q1.3 are provided. Balance transformer BTI- provided at the base and emitter, or the emitter and collector, or the collector and base of
BT3, BT11 to BT21, and a plurality of switching transistors Q1, G2, Q11 to Q by the balance transformers BTI-BT3 and BTII to BT22.
The currents flowing through the circuits 13 are corrected so that they are approximately equal to each other.

The current flowing through the plurality of switching transistors Q1, G2, Qll to Q13, which are F-action bipolar transistors, is as follows.
Balance transformer BTI~BT3, BTII~BT22
Correction control is performed so that they are equal to each other.

As a result, switching transistors Q1, G2, Qll
~ When the current flowing through Q13 is about to lose its balance, the balance transformer BTI ~ BT3
, BTII to BT22 perform correction operations to prevent loss of balance.

In this way, the plurality of switching transistors Q1, G2, Qll to Q13 constituting the switching circuit 15 can maintain a state in which switching losses are shared almost equally, so that the switching transistors Q1, G2, Q
It is possible to prevent the risk of damage to ll to Q13.

(by using fewer bipolar transistors,
A switching circuit 12 capable of switching a large current at high speed can be easily realized.

G example An embodiment of the present invention will be described in detail below with reference to the drawings.

(G1) First Embodiment As shown in FIG. 1 corresponding to FIG. 8, the switching circuit 15 has transistors Q1 and G2, which are two power switching bipolar transistors. The collectors of transistors Ql and G2 are connected to the deflection output line 1
1 and the emitter is connected to balance transformer B.
It is grounded through a pair of windings C1l and C12 of TI.

In the case of this embodiment, the bases of the transistors Q1 and G2 are connected to the switching control transistor QO via the input transistor INT, and a switch signal SW is applied from the amplifier circuit 3 (FIG. 1) to the switching control transistor QO. When ON is activated, the input quadrance INT
Secondary winding ■NTI and INT2 to transistor Q1
By flowing base currents i□ and imz into the transistors Q1 and G2 through the resistors R11 and R12 and the balance transformer BT2, the transistors Q1 and G2 are turned on.

In the above configuration, the balance transformer BTI connected to the emitters of the switching transistors Q1 and G2
are the currents i+++ic+ and im drawn from the emitter in the same manner as described above for equations (1) to (4).
A correction operation is performed so that t+iet are approximately equal to each other.

At the same time, switching transistors Q1 and G2
Similarly, for the base currents i□ and i□ of By doing this, the base current i and imt are corrected to be equal to each other as expressed by the following equation 1 (%(7)).

In this way, the balance transformers BTI and Br3 perform a correction operation so as to simultaneously satisfy the conditions of equations (4) and (7), so that the collector currents ic+ and icz flowing through the switching transistors Ql and G2 become i cl- f cz --(8)
are equal to each other, as in

In this way, all the currents flowing in the collectors of the two switching transistors Ql and G2 connected in parallel with each other, namely the collector currents ic+ and icz, the base currents ii+ and fax flowing into the bases, and the emitter currents i□ drawn from the emitters. +ic+ and i. +
ic! Since the switching transistors Q1 and G2 are equal to each other, the switching transistors Q1 and G2 perform switching operations in a mutually balanced state.

According to the experimental results, as shown in FIG. 2, the collector currents ie+ and i of the switching transistors Ql and G2
We were able to align the changes in cz (Figure 2 (A)
) as well as the base current l□ and imz (Fig. 2 (B))
It was also possible to match the characteristics of the two switching transistors Q1 and G2 with respect to the way in which they change.

Therefore, according to the configuration shown in Fig. 1, two
When the currents flowing through the two switching transistors Q1 and G2 tend to become unbalanced, the switching losses are reduced by correcting the base current and the collector current to be approximately equal by the balance transformers BTI and BT2. will be maintained in such a way that they will be shared equally.

Therefore, by preventing the occurrence of a state in which only one of the transistors is burdened with switching loss, it is possible to realize a switching circuit 15 that performs a stable and large-capacity switching operation as a whole.

(G2) Second Embodiment FIG. 3 shows a second embodiment. In this case, corresponding parts to those in FIG. 1 are denoted by the same reference numerals. The balance transformer BT2 provided in the base circuit is omitted, and instead, a balance transformer BT3 is provided in the collectors of the switching transistors Ql and G2.

If configured as shown in FIG. 3, collector current ic+ flowing into the collectors of switching transistors Q1 and G2
and icz are corrected to be equal to each other by balance transformer BT3, and emitter currents drawn from the emitters are corrected to be equal to each other by balance transformer BTI.

As a result, base currents 11 and imz flowing into the bases of switching transistors Q1 and G2 have the same value.

In this way, the switching transistors Q1 and G2 operate in a state where the currents flowing therein are equal to each other, thereby preventing the switching transistors Q1 and G2 from losing their balance and being damaged.

(G3) Third Embodiment FIG. 4 shows a third embodiment. In this case, the switching circuit 15 has a configuration in which three transistors Qll, G12, and G13 are connected in parallel with each other, and the transistor Q12
A balance transformer BTII is provided at the base of Qll and switching transistors Q12 and G13.
A balance transformer BT12 is provided at the base of the balance transformer BT12. Thus, the base currents im+z and Le+ of the switching transistors Q12 and Qll are corrected to be equal to each other by the balance transformer BTII, and at the same time, the currents i mHz and i□ flowing through the bases of the switching transistors Q12 and G13 are adjusted by the balance transformer BT12.
are corrected so that they are equal to each other.

In addition to this, switching transistors Q12 and Ql
A balance transformer BT21 is provided at the emitter of switching transistors Q12 and G13, and a balance transformer BT22 is provided at the emitters of switching transistors Q12 and G13.
In this way, ic+z '' imtz and ic++ +isz extracted from the emitters of switching transistors Q12 and Qll are corrected to be equal to each other by balance transformer BT21, and at the same time,
Currents drawn from the emitters of switching transistors Q12 and G13 ic+z + imtz and ic
+s+i 113 are corrected to equal values by the balance transformer BT22.

According to the configuration of FIG. 4, the switching transistor Ql
Regarding the base currents of l to Q13, base current i□1 is approximately equal to base current i□2, and base current 1
By correcting IIt so that it becomes approximately equal to the base current i□, the base current i□l,'l! S l□
, are almost equal to each other.

Also, regarding the current drawn from the emitter, ic+□
+i□2 is corrected to be almost equal to ic++ +i□1, and current ic+z + is+z is 1c+
By correcting it so that it is almost equal to s+i□, l ell ” i□l , I C1t +1 m
l! , ic+z +i□, are corrected to substantially equal values.

Thus the three switching transistors Q11, C1
2. Since the currents flowing through C13 are generally equal to each other, the switching loss of the switching circuit 15 can be reduced by reducing the switching loss of these three switching transistors Qll and C1.
2. By operating with C13 equally sharing the load, damage to these switching transistors can be prevented.

(G4) Other embodiments (1) In the embodiment shown in FIG. 1, a case has been described in which balance transformers BTI and Br3 are provided on the emitter side and base side of switching transistors Ql and C2, but instead of this, Even if balance transformers are provided on the emitter side and the collector side, or on the collector side and the base side, the same effect as in the above case can be obtained.

(2) In the case of the embodiment shown in FIG. 3, a case has been described in which a balance transformer is provided on the emitter side and collector side of the switching transistors Ql and C2. Even if a balance transformer is provided on the collector side, the same effect as in the above case can be obtained.

(3) In the first, second, and third embodiments described above, the number of switching transistors connected in parallel is 2.
Although the case has been described in which the number of switching transistors is two or three, the number of switching transistors connected in parallel is not limited to this, and may be two or more.

H Effects of the Invention As described above, according to the present invention, the bases, emitters, and
By providing a balance transformer in at least two places in the collector, when the current flowing through each switching transistor tries to lose its balance, it corrects the current to become equal to each other. Since switching losses can always be shared equally, a switching circuit that can effectively switch a large current with a small number of elements can be easily realized.

[Brief explanation of drawings]

FIG. 1 is a connection diagram showing a first embodiment of a switching circuit according to the present invention, FIG. 2 is a signal waveform diagram showing changes in current, and FIG. 3 is a diagram showing a second embodiment of a switching circuit according to the present invention. 4 is a connection diagram showing a third embodiment of the switching circuit according to the present invention, FIG. 5 is a systematic connection diagram showing a horizontal deflection circuit, and FIG. 6 is a signal waveform showing signals of each part thereof. Figures 7 and 8 are connection diagrams showing conventional switching circuits, Figure 9 is a connection diagram showing an equivalent circuit of Figure 8, and Figure 10 shows changes in current in the switching circuit of Figure 7. It is a signal waveform diagram. 1...Horizontal deflection circuit, 2...Oscillation circuit, 3...Amplification circuit, 4...Drive circuit,
5...Horizontal output transistor, 15...
・Switching circuit, Ql, C2, Qll~Q13...
...Switching transistor, BTOlBTI,
Br3, BT11~BT22...Balance transformer.

Claims (1)

[Scope of Claims] A plurality of switching transistors made of bipolar transistors, and a balance transformer provided at the bases and emitters, or the emitters and collectors, or the collectors and bases of the plurality of switching transistors; A switching circuit that corrects currents flowing through a plurality of switching transistors so that they are approximately equal to each other.