JPH039418Y2 - - Google Patents

Description

[Detailed description of the invention] Industrial application field The invention relates to a signal input circuit, and includes horizontal synchronization signals (hereinafter referred to as HD), vertical synchronization signals (hereinafter referred to as VD
), composite synchronization signal (hereinafter referred to as CSync)
It is used in video equipment such as television monitors that are driven by externally supplied synchronizing signals such as the following.

Prior Art FIG. 1 shows a circuit diagram of an example of a conventional signal input circuit. In the figure, switch _SW1 is connected to terminal P when HD and VD are in the mode simultaneously. HDa entering terminal 1 (A in Figure 2) and VDb entering terminal 2 (B in the same figure) are connected to matching resistors R ₁ , R ₂ , DC component removal capacitors C ₁ , C ₂ ,
Clamping diodes D ₁ , D ₂ , current limiting resistor R ₄ ,
It is supplied to the bases of limiter transistors Q ₁ and Q ₂ via R ₅ , discharge and base bias resistors R ₇ and R ₈ . Transistors Q ₁ and Q ₂ operate as a so-called limiter that outputs a constant level output to the collector regardless of the level of the base input signal, and outputs signal c (C in the figure) and signal d (D in the figure) from their respective collectors. is taken out.

Signals c and d are supplied to exclusive OR gate 4, where they are combined and taken out as CSync e (E in the same figure), and supplied to one input terminal of exclusive OR gate 5 via switch SW ₁ . be done. Since the exclusive OR gate 5 has the voltage +B applied to its other input terminal via the resistor R ₁₃ , it operates as an inverting circuit, and as a result, the negative polarity CSync f (FIG. F) is output from its output terminal.
is taken out.

The same applies when VD is input to terminal 1 and HD is input to terminal 2.

Next, in the mode in which only CSync is input, switch _SW1 is connected to terminal Q. CSync input to terminal ₃ is connected to the base of limiter transistor Q 3 via matching resistor R ₃ , DC component removal capacitor C ₃ , clamping diode D ₃ , current limiting resistor R ₆ , and discharge and base bias resistor R ₉ supplied to CSync from the collector of transistor Q ₃
A signal e (E in the same figure) whose polarity is inverted is extracted,
It is taken out as a negative polarity CSync f (F in the same figure) via the switch SW ₁ and the exclusive OR gate 5.

Problems that the invention aims to solve The conventional circuit with the above configuration requires three input terminals, and also requires switch SW ₁ to switch between a mode in which HD and VD are input simultaneously and a mode in which only CSync is input. Therefore, there were problems such as a large number of parts, the inability to construct a circuit easily and inexpensively, and troublesome operation.

Means for Solving the Problems The present invention solves the above problems by connecting the base of at least one of the two transistors to the power supply via a base bias resistor, thereby reducing the number of input terminals. It is an object of the present invention to provide a signal input circuit which has a simple circuit configuration and does not require any operation by eliminating a changeover switch. Hereinafter, one embodiment will be described with reference to the drawings.

Embodiment FIG. 3 shows a circuit diagram of an embodiment of the signal input circuit according to the present invention, and in the figure, parts having the same functions as those in FIG. 1 are given the same numbers and symbols. In the figure, R ₁₄ and R ₁₅ are discharge and base bias resistances,
They are connected between the bases of transistors Q ₁ and Q ₂ and the power supply +B, respectively. The output terminal of the exclusive OR gate 4 is directly connected to the input terminal of the exclusive OR gate 5, and no switch is provided as in the conventional circuit. Numerals 6 and 7 are synchronization signal input terminals, which can receive any HD, VD, or CSync synchronization signal. The circuit of the present invention has only two synchronizing signal input terminals, terminals 6 and 7.

First, if HD enters terminal 6 and VD enters terminal 7 at the same time, or VD enters terminal 6 and VD enters terminal 7,
The operation when the HDs arrive at the same time is substantially the same as that of the conventional circuit shown in FIG. 1, so a description thereof will be omitted.

Next, terminal 7 has no input, and terminal 6 has CSync.
When the signal e (FIG. 2E) is input, a signal e (FIG. 2E) is taken out from the collector of the transistor _Q1 . At this time,
The transistor _Q2 is turned on because the power supply voltage +B is applied to its base via the resistor _R15 , and its collector is at L level.

The collector output e of the transistor Q ₁ and the collector output L level of the transistor Q ₂ are supplied to the exclusive OR gate 4, and the same signal e as its input is taken out from the exclusive OR gate 4. The signal e is inverted by an exclusive OR gate 5, and a negative polarity CSync f is taken out.

On the contrary, terminal 6 has no input and terminal 7
When CSync comes in, the signal e is taken out from the collector of transistor _Q2 , while the L level is taken out from the collector of transistor _Q1 . Similar to the above case, exclusive or gate 4
A signal e is taken out from the exclusive OR gate 5, and a signal f is taken out from the exclusive OR gate 5.

In this way, the above embodiments are HD, VD,
CSync may be input to either terminal 6 or 7.
Only two input terminals are required, and there is no need for mode switching operations as in conventional circuits.

FIG. 4 shows a circuit diagram of another embodiment of the circuit of the present invention, in which parts having the same functions as those in FIG. 1 are given the same numbers and symbols. In the figure, 8 and 9 are synchronization signal input terminals, and while HD and VD can be input to either terminal, CSync can be input only to terminal 8. The base of transistor Q ₁ is grounded via resistor R ₇ as in the conventional circuit, while the base of transistor Q ₂ is connected to power supply +B via resistor R ₁₅ .

When HD is input to terminal 8 and VD is input to terminal 9 at the same time, or when VD is input to terminal 8 and HD is input to terminal 9 at the same time, the operation is almost the same as the conventional circuit shown in Figure 1. The explanation will be omitted.

On the other hand, terminal 9 has no input, and terminal 8 has CSync.
The operation when the signal enters is the same as the operation explained in connection with the circuit shown in the third figure, so the explanation thereof will be omitted.

Note that, contrary to the circuit shown in Figure 4, the transistor
The base of Q ₁ may be connected to the power supply +B via resistor R ₁₄ , while the base of transistor Q ₂ may be grounded via resistor R ₈ . in this case,
CSync can only be grounded to terminal 9.

Further, since the exclusive OR gate 5 merely operates as an inverting amplifier, an inverter or the like may be used, for example.

Furthermore, although the transistors in the above embodiments are of NPN type, they are not limited to this type, and PNP type transistors are used.
Shape may also be used. In this case as well, both the discharge and base bias resistors are connected to the power supply +B, or one of them is connected to the power supply +B and the other to ground.

Effects As mentioned above, the signal input circuit according to the present invention has two
Because the base of at least one of the transistors is connected to the power supply via the base bias resistor, only two transistors are required as input terminals for three types of input signals, for example, HD, VD, and CSync.
Also, there is a mode where HD and VD come in at the same time.
There is no need for a switch to change between the mode in which only CSync is input, and as a result, the number of parts can be reduced compared to conventional circuits, the circuit can be configured easily and inexpensively, and there is no need for switching operations. It has characteristics.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an example of a conventional circuit, and FIG. 2 is a signal waveform diagram for explaining the operation of the conventional circuit and the circuit of the present invention.
3 and 4 are circuit diagrams of one embodiment and another embodiment of the circuit of the present invention. 4, 5...Exclusive or gate, 6-9
... Synchronous signal input terminal, Q ₁ - Q ₂ ... Transistor, R ₁₄ , R ₁₅ ... Discharge and base bias resistance.

Claims (1)

[Claims for Utility Model Registration] (1) Two grounded-emitter inverting transistor amplifiers whose bases are supplied with input signals respectively input to two input terminals and whose collectors output inverted signals; In a signal input circuit provided with an exclusive OR gate that is supplied with the collector outputs of transistor amplifiers and synthesizes and extracts the collector outputs, the base of at least one of the two transistors is connected to a base bias resistor. A signal input circuit connected to the power supply via the (2) The bases of the two transistors are connected to a power supply via respective base bias resistors, and both of the two input terminals are terminals to which a horizontal synchronization signal and a vertical synchronization signal are simultaneously input, respectively. The signal input circuit according to claim 1, wherein each of the terminals is a terminal to which a composite synchronization signal is input. (3) One of the two transistors has its base connected to ground via a base bias resistor, and the other transistor has its base connected to the power supply via a base bias resistor, All of the input terminals are terminals into which a horizontal synchronization signal and a vertical synchronization signal are respectively input simultaneously, and only the input terminal corresponding to one of the transistors is a terminal into which a composite synchronization signal is input. The signal input circuit according to item 1.