JPS61238180A - Clamping circuit - Google Patents

Abstract

PURPOSE:To obtain a clamping circuit having the high clamping ability with a low power consumption by providing the variable electric current source at the emitter terminal of the transistor included in an impedance converting circuit composed of the emitter follower provided at the input side of the clamping capacitor. CONSTITUTION:A variable electric current source 30 increases an emitter electric current IE of a transistor Q1 during the clamping period T1 based upon a clamping pulse signal P which comes from the external part. As the result, the output impedance of an impedance converting circuit 10, namely, the input impedance of a clamping capacitor C is decreased, and in a moment, charging is executed. For this, the variable electric current source 30 decreases lowly the emitter electric current IE of the transistor Q1 during the non-clamping period T2 based upon a clamping pulse signal CP. Thus, the power consumption during the non-clamping period T2 can be phasedly decreased.

Description

DETAILED DESCRIPTION OF THE INVENTION A. Field of Industrial Application The present invention relates to a clamp circuit, and can be applied, for example, to setting a reference potential of a video signal and reproducing a DC component in a video tape recorder (VTR).

B Summary of the Invention The present invention provides a clamp circuit including an impedance conversion circuit with an emitter-follower configuration on the input side of a clamp capacitor, in which a variable current source is provided to switch the emitter current of a transistor included in the impedance conversion circuit in a clamp period and a non-clamp period. In particular, sufficient lamp performance can be exhibited during the clamp period, and power consumption during the non-clamp period can be reduced.

C. Conventional technology Video signals have a signal format that determines, for example, the brightness of an image based on the magnitude from a predetermined reference level, so the reference level must be fixed.
Also in R, clamp circuits are often used to fix the reference level for each horizontal period. Conventionally, there is a clamp circuit shown in FIG. 2 as such a clamp circuit.

In FIG. 2, an input video signal VDIN is applied to a clamp capacitor C via an impedance conversion circuit 10. This impedance conversion circuit 10 lowers the input impedance of the clamp capacitor C to convert it into a clamp capacitor. It has an emitter-follower configuration in which a transistor Q1 (NPNII) and a resistor R1 are connected in series between a power supply line L1 and a ground 94 and a resistor R1.

Output end of clamp capacitor C and ground 94 52
In between is an NPN transistor Q2 as a switch circuit.
and a constant voltage source E are connected in series. Switching transistor Q2 receives input video signal VDIN (Fig. 3) K
Based on the input video signal VDIN being at a certain level, for example,
It receives a clamp pulse signal CP (FIG. 3@) which periodically rises to the logic rHJ only during a predetermined time T1 during which the sync chip level is maintained, and performs an on/off operation via a gate resistor R2.

Switching transistor Q2 receives clamp pulse signal C
During the clamp period T1 in which the ON operation is performed based on P, the potential at the midpoint A of the connection between the clamp capacitor C and the collector and the collector of the transistor Q2 is the clamp potential E, which is the output voltage of the constant voltage source E. (sync chip level determined by the signal format). At this time, the clamp capacitor C is charged to the clamp potential E0 through a constant voltage source E-) transistor Q2-capacitor C-resistor R1 constant voltage source E.

On the other hand, during the non-clamp period T2 when the switching transistor Q2 is turned off, the clamp capacitor C is charged to the clamp potential EC, so the potential at the connection point on the output side of the ramp capacitor C is The clamp potential E0 is changed as a reference potential in response to the change in the potential at the connection midpoint B on the side in response to the video signal VDIN.

Thus, the connection midpoint AK reference potential E. A fixed K video signal is obtained, which is connected to the power line L1 and ground 94.
NPNu) transistor Q3 connected in series between
It is sent out as an output video signal VDOUT via a buffer circuit formed by the emitter resistor R3.

In addition, even if the clamp capacitor C is discharged during the non-clamp period T2 when the switching transistor Q2 is off, the voltage drop across the capacitor C can be suppressed to within 1 [chi] at the end of the period T2. selected.

D Problems to be Solved by the Invention Incidentally, the clamp period T1 in the clamp pulse signal CP is selected to be a period that takes a constant value such as the sync chip level, so for example, it is 1 to 4 due to the constraint of the horizontal synchronization period. It is a short period of about .5 [μ5 ec]. Therefore, the clamp capacitor C must be charged instantaneously, and therefore the input impedance of the capacitor C, ie, the output impedance of the impedance conversion circuit 10, must be small.

However, in an impedance conversion circuit with an emitter-follower configuration, in a range where the signal source impedance is small to a certain extent, as shown by the curve CUK in FIG.
There is an inversely proportional relationship between the output impedance and the output impedance of 2°. Therefore, in order to charge the clamp capacitor C instantly, the output impedance is reduced and the emitter current is adjusted.

(If you try to increase it, there is a disadvantage that the power consumption by the resistor R1 increases during the non-clamping period T2 when no clamping is performed. Conversely, the output impedance is increased to keep the emitter current 8 small [Let's lower the power consumption. If this is the case, there are five cases where charging during the clamping period T1 becomes insufficient and the clamping ability decreases.

In practice, the emitter current is selected to be 5 CmA) to reduce power consumption. Therefore, the emitter current is insufficient for the required 20 mA in terms of clamping capacity, and the clamp capacitor C cannot be sufficiently charged, which may cause the output video signal VDOUT to become unstable. Ta.

The present invention has been made in consideration of the above points, and it is an object of the present invention to provide a clamp circuit having low power consumption and high clamping ability.

Means for Solving Problem E To solve this problem, the present invention provides a clamp circuit including an impedance conversion circuit 10 having an emitter-follower configuration on the input side of a clamp capacitor C, in which a transistor Q1 included in the impedance conversion circuit 10 is The emitter current of , the clamp period T1 is made large enough to charge the clamp capacitor C instantaneously, and the transistor Q
1 emitter current 1. A variable current source (9) is provided to switch the non-clamp period T2 to be small.

A two-acting variable current source I receives a clamp pulse signal C that comes from the outside.
During the clamp period T1, the emitter current of the transistor Q1 is increased based on P.

As a result, the output impedance of the impedance conversion circuit 10, ie, the input impedance of the clamp capacitor C, decreases, and charging is instantaneously performed.

On the other hand, the variable current source blade uses the clamp pulse signal CP.
Based on this, the emitter current of the transistor Q1 is kept low (suppressed) during the non-clamp period T2.

As a result, the power consumption during the non-clamp period T2 can be significantly reduced compared to the conventional method.

Embodiment 1 Below, parts corresponding to those in FIG.
An embodiment of the invention will now be described in detail with reference to the figures.

In FIG. 1, a transistor Q1 constituting an impedance conversion circuit 10 has an emitter terminal and an earth line L.
It has a variable current source connected between the two. This variable current source 3o includes a resistor R4 connected between the emitter terminal of the transistor Q1 and the earth line L2, a series circuit of a resistor R5 and a switching transistor Q4 connected in parallel to this resistor R4, and a gate resistor of the switching transistor Q4. It consists of R6.

The switching transistor Q4 receives a clamp pulse signal CP shown in FIG. 3 (to) as an on/off control signal,
During the non-clamping period T2 of the clamp pulse signal CP, the transistor Q1 is turned off and the emitter resistance value of the transistor Q1 becomes the value r4 of the resistor R4, and during the clamping period TI of the clamp pulse signal CP, the transistor Q1 is turned on and the emitter resistance of the transistor Q2 is Let the value be the combined resistance value of resistors R4 and R5 "4 r5/(r4 + r5)".

Here, the resistance values r4 and r5 of the resistors R4 and R5 have a combined resistance value as an emitter resistance value during the clamp period T1, and the emitter current decreases.

If K is selected to be 20 (mA), which is practically necessary and sufficient for charging the clamp capacitor C, the resistance value r4 of the resistor R4 as the emitter resistance value during the non-clamping period T2 is determined only by the resistor R4. The emitter current is selected so that it is small enough to suppress power consumption.

In the configuration shown in FIG. 1, the clamp pulse signal CP (
When the switching transistor Q2) rises, the switching transistor Q2
is turned on, and the potential at the middle point of the connection is the clamp potential E from the constant voltage source EK. K is fixed and output via the buffer circuit (9). At this time, the switching transistor Q4 of the variable current source I is also turned on based on the clamp pulse signal CP.

Therefore, the emitter resistance value of transistor Q1 is resistor R4
The combined resistance value of resistor R5 and resistor R5 takes a small value, increases the emitter current, and makes the output impedance 2° (
(Fig. 4) is made sufficiently small to instantly charge the clamp capacitor C.

On the other hand, the clamp pulse signal CP goes low, the off-state transistor Q2 turns OFF, and the potential of the connecting point becomes the clamping potential E of the ramp capacitor C. K
Since it is charged, it changes according to changes in the video signal VDIN using the clamp potential E0 as a reference potential, and this is outputted via the buffer circuit (9). At this time, K is
The switching transistor Q4 of the variable current [30] is also turned off.

Therefore, the emitter resistance value of transistor Q1 is resistor R4
The value r4 becomes larger than the combined resistance value, and the emitter current is reduced. As a result, power consumption during this non-clamp period T2 can be reduced. Incidentally, in practice, the clamp period T1 is 2 [μsec], while the non-clamp period 2 is about 62 (μsec), so by suppressing the power consumption during the non-clamp period T2, the overall circuit Power consumption can be significantly reduced.

Note that during this non-clamp period T2, that is.

When the transistor Q1 is not clamped, a small value of the emitter current is sufficient since the transistor Q1 does not require a strong drive ability for the clamp capacitor C.

In this way, the circuit shown in Figure 1 uses the clamp pulse signal CPK.
Based on this, in the clamp period, the emitter current of the drive transistor Ql of the clamp capacitor C is increased to enhance the clamping ability, and in the non-clamp period, the emitter current is decreased to suppress power consumption. (Thus, according to the circuit shown in FIG. 1, it is possible to improve both the contradictory characteristics of clamping ability and power consumption.

Although the above-described embodiment shows a case in which the clamp circuit is applied to a VTR, the present invention is not limited to this, and can be widely applied to various electronic devices as required.

Further, in the above-described embodiment, the variable current source I is made up of a series circuit of the resistor R5 and the transistor Q4, and a parallel circuit of the resistor R4, but the present invention is not limited to this. The key point is to increase the emitter current of transistor Q1 when clamping, and
Any device that can be switched so as to suppress the emitter current to a small level when not clamped is sufficient.

Furthermore, the above embodiment is an application of the present invention to the pulse clamp circuit shown in FIG.

The present invention can also be applied to other types of gangway circuits, such as a diode ramp circuit in which the output side pressure diode of the clamp capacitor C is connected, and similar effects can be obtained.

Further, in the above embodiment, the period during which the video signal VDIN is at the sync tip level was selected as the clamp period T1, but it may be selected to be the period during which the video signal VDIN is at the pedestal level, and in this case, the constant voltage source E It is necessary to set the level E0 to the pedestal level <-r. This pedestal level is fixed to the clamp potential.

H Effects of the Invention As described above, according to the present invention, a variable current source is provided at the emitter terminal of the transistor included in the impedance conversion circuit having an emitter follower configuration provided on the input side of the clamp capacitor C, and the emitter current is changed during the clamp period. It is possible to obtain a clamp circuit that can sufficiently exhibit lamp performance by increasing the voltage, and can suppress emitter current during the non-clamp period to realize low power consumption.

[Brief explanation of drawings]

Fig. 1 is a connection diagram showing an embodiment of the clamp circuit according to the present invention, Fig. 2 is a connection diagram showing a conventional circuit, Fig. 3 is a signal waveform diagram of each part of the clamp circuit, and Fig. 4 is an impedance conversion circuit diagram. FIG. 3 is a route diagram showing the relationship between emitter current and output impedance. 10--Impedance conversion circuit, Chrysanthemum--variable current source, C--clamp capacitor, E--constant voltage source,
Q1-Q4-) transistor, R2-R6...resistance.

Claims (1)

[Claims] In a clamp circuit including an impedance conversion circuit having an emitter follower configuration on the input side of a clamp capacitor, the emitter current of a transistor included in the impedance conversion circuit is controlled during a clamping period to such an extent that the clamp capacitor can be charged instantaneously. 1. A clamp circuit comprising a variable current source which switches the emitter current of the transistor to a small value during a non-clamp period.