JPS63166366A - Vertical deflection output circuit - Google Patents

Abstract

PURPOSE:To save the power consumption and the blanking period by providing a capacitor resonated to a vertical deflection coil and a diode disconnecting the transistor (TR) of an output circuit while utilizing flyback pulse generated in the blanking period in a vertical deflection output circuit. CONSTITUTION:Since a 2nd TR 2 is turned off and a 1st TR 1 and a TR 3 have a high impedance with respect to a load circuit by means of a diode D1, the flyback pulse voltage is not suppressed by a power supply voltage and kept to a remarkably higher voltage than the power voltage +B1 by the damping operation of a resistor R1 and a coil resistance of a resonance circuit comprising a vertical deflection coil L and a capacitor C1. Thus, in utilizing the high voltage, the power consumption reduction the same degree as a conventional pump up circuit is attained with a very simple circuit constitution.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a vertical deflection output circuit applied to a so-called CRT display device using a cathode ray tube.

[Conventional technology]

Recently, with the progress of information processing technology using microcomputers, CRT display devices have been increasingly used. Since the vertical deflection circuit of a CRT display device handles a low frequency, it is necessary to use a large-capacity capacitor, so there is little merit in integrating it into an IC, and this is a part that remains extremely problematic in terms of cost reduction. In general, a vertical deflection circuit consists of a vertical oscillator circuit that generates a sawtooth voltage, a vertical drive circuit that shapes and amplifies this voltage, and a vertical deflection circuit that further amplifies it and supplies a sawtooth current to the vertical deflection coil. It consists of an output circuit. The development goals of this vertical deflection output circuit have been to improve the linearity of the output sawtooth wave and to reduce power consumption.

For example, for the former improvement, it is possible to omit the output transformer, connect the output transistor in series with the power supply, and directly supply power to the load. In this case, one output terminal is connected to ground, and when input signals of opposite phases are applied to the two complementary output transistors, outputs are alternately supplied to the load from both transistors. A 5EPP (single-ended push-pull) circuit is configured. Various improvements have been made to this 5EPP circuit, such as adopting a drive method that utilizes the positive half cycle and negative half cycle of one human input signal, and consolidating the power supply for driving the output transistor into -. Things are being implemented. That is, a coupling capacitor connected in series with the load has a sufficiently large capacity for the frequency of the input signal, and the coupling capacitor is charged using the current flowing through the load during the first positive half cycle of the input signal. In the next negative half cycle, the discharge voltage of the coupling capacitor is used as a power source.

In addition, to reduce power consumption in the latter case, in order to repeatedly flow a sawtooth wave current through the vertical deflection coil that is the load, a high voltage is applied during the retrace period of the repetition period when forming the necessary voltage waveform. Various pump-up circuits have been proposed in which the power consumption of the vertical deflection output circuit is reduced by applying a low voltage during the scanning period.

[Problems to be Solved by the Invention] However, the pump-up circuit in the conventional vertical deflection output circuit described above requires two high and low power supplies, and moreover, this power supply is not properly connected to the beginning and end of the retrace period. Since a switching circuit for reliable switching is provided, the circuit structure becomes complicated, and even if power consumption is reduced, the cost increases due to the increase in functions.

Therefore, the purpose of the present invention is to absorb the energy of the flyback pulse generated during the retrace period by using a resonant capacitor connected in parallel with the vertical deflection coil, and to improve the output power that conventionally suppresses this flybank pulse voltage. It is an object of the present invention to provide a vertical deflection output circuit capable of maintaining a high pulse voltage during a retrace period and shortening the retrace period by circuitly separating the output transistors of the circuit.

[Means for solving problems]

Therefore, the vertical (orientation output circuit) according to the present invention is configured such that the first transistor and the second transistor are arranged so that the diode conducts alternately during the positive period and the negative period of the sawtooth wave signal of a predetermined period to which the first transistor and the second transistor are applied. The present invention is characterized in that it includes a push-pull circuit connected in series with the diode with the same polarity through the diode, and a load circuit in which a capacitor is connected in parallel between the anode of the diode and the vertical deflection coil.

[Effect]

According to the vertical deflection output circuit according to the present invention, when a sawtooth waveform signal is supplied as an input signal to the bases of a pair of push-pull connected transistors constituting the output circuit, the output terminal of the push-pull circuit For the connected load circuit, a collector current flows through one and the other transistor of the push-pull circuit, respectively, according to the polarity of the input signal during the scan period, and the push-pull action generates a sawtooth wave in the vertical deflection coil of the load circuit during the scan period. Outward current flows. The change in magnetic flux caused by this current deflects the electron beam of the CRT in the vertical direction. The input signal during the retrace period then turns the other transistor of the push-pull circuit off at the beginning of the retrace period, and the inductance of the vertical deflection coil has a sawtooth wave return current reaching several times the supply voltage. A flyback pulse voltage is generated. Therefore, in the present invention, since the other transistor of the push-pull circuit is in an off state and one transistor has a high impedance to the load circuit via the diode, the flybank pulse voltage is suppressed to the power supply voltage. A resonant circuit consisting of a resonant capacitor provided in the load circuit and a vertical deflection coil receives the damping effect of the coil resistance, etc., and can maintain an appropriate high voltage. Therefore, by utilizing this high voltage, it is possible to achieve the same level of power consumption reduction as a conventional pump-up circuit with an extremely simple circuit configuration.

〔Example〕

Next, regarding an embodiment of the vertical deflection output circuit according to the present invention,
A detailed description will be given below with reference to the accompanying drawings.

FIG. 1 is a circuit diagram showing an embodiment of the vertical deflection output circuit according to the present invention, and FIG. 2 is a waveform diagram showing the operating characteristics of the load circuit shown in FIG. 1.

In FIG. 1, an output circuit is constructed by connecting a first transistor TRI and a second transistor TR2 in series between a power supply +81 and the ground, and these transistors TRI and T
A vertical deflection coil L and a coupling capacitor C1 are connected in series between the output terminal Q of R2 and the ground (the coupling capacitor C1 can be omitted if the emitter side of the transistor TR2 is connected to the negative power supply). ),
Furthermore, a resonant capacitor C2 is connected in parallel with this series connection circuit.
is connected. The circuits connected to the output terminals Q of these transistors TRI and TR2 constitute load circuits, respectively. Further, a drive transistor TR4 whose emitter is grounded is provided, and the collector of this transistor TR4 is connected to the base of the first transistor TRI and the transistor TI? The base input signals input to the three bases are output. In addition,
The transistor TR3 is the second transistor TR2.
This is an amplification transistor that is Darlington connected to the

A resistor R1 connected in series with the vertical deflection coil is a feedback resistor of the load circuit, and a transistor T
Negative feedback is provided to the base of R4 to improve the linearity of the amplified sawtooth waveform output and to act as a damping resistance for the resonant circuit constituted by the load circuit. Resistor R2, R
3, R8 and R6 and R11 are transistors TR2, T
Each of RI, TR4, and TR3 is an emitter resistance,
Resistor R7 is the collector resistance of transistor TR3. Further, resistors R4 and R5 and R9 and RIO are bias resistors for transistors TRI and TR4.

Capacitor C3 is a boost trap capacitor that corrects a decrease in collector current due to an increase in emitter voltage of transistor TRI. Capacitor C4 is an input capacitor pulling capacitor. The diode D1 is a diode for isolating the load circuit from other output circuits during the retrace period, which is the key point of the present invention.

Diodes D2 and D3 are bias diodes. Note that an input signal i having a sawtooth waveform as shown in the figure is supplied to the input point P.

Next, the operation of the circuit of this embodiment will be explained.

The transistor TR4 is a transistor of the input circuit, and inputs the input signal i from a sawtooth wave generation circuit (not shown) and amplifies it, and the transistor TR4 inputs the input signal i from the sawtooth wave generation circuit (not shown) and amplifies it.
Transistor TR2 is connected to Darlington 3.
Drives a quasi-push-pull circuit composed of The operation of the load circuit at this time will be explained with reference to the operation waveforms shown in FIG. FIG. 2 shows the waveform of the current flowing through the vertical deflection coil. In this way, the scanning period and blanking period are alternately repeated during the repetition period. However, in the first half of the scanning period, a current flows to the collector of the transistor TR1 [FIG. 2(b)], and in the second half of the scanning period, the current flows to the collector of the transistor TR2 [FIG. 2(C)].
].

During the scanning period and blanking period, a voltage with the waveform shown in FIG. 2 (dl) is applied to the vertical deflection coil L. As shown in FIG. , a drive transistor T is attached to the base of the transistor TRI.
When a positive half cycle of the human power signal is input from the collector of R4, the collector current flows as shown in Figure 2(b),
A half cycle of the sawtooth wave forward current is passed through the vertical deflection coil, and the compling capacitor C1 is charged. The collector current of the second transistor TR2, which is Darlington connected to the transistor TR3, does not flow into the load circuit. Next, in the second half of the scanning period, the negative half cycle of the input signal is input to the base of the first transistor TR1, and the collector current is cut off and does not flow to the load circuit. The discharge current of the compression capacitor C1 flows into the emitter of the transistor TR3 via the resistor R11, and the transistor TR3 allows current to flow to the collector due to the input of the negative half cycle of the input signal, and the output voltage of the transistor TR3 is This transistor TR2 uses the discharge voltage of the pulling capacitor C1 as a power source to flow the collector current to the load circuit as shown in Figure 2(C), and connects it to the vertical deflection coil. Half a cycle of the sawtooth outgoing current will flow in the opposite direction from the previous one. In this manner, a sawtooth wave forward current flows through the vertical deflection coil during a scanning period of 1 ffl, and this current deflects the electron beam of the CRT in the vertical direction. Next, regarding the operation during the retrace period, at the start of the retrace period, the transistor TR3 is turned off because the driving NPN transistor TR4 is turned off, and therefore the second transistor TR2 is also turned off. In the vertical deflection coil, a flybank pulse voltage reaching several times the power supply voltage is generated due to the sawtooth ground-wave return current. Conventionally, this flyback pulse voltage is applied to the first and second transistors TRI of the output circuit,
Since TR2 is saturated by high voltage, the impedance between its collector and emitter is small, and therefore the flybank pulse voltage reaches the power supply voltage 131 at the same time it occurs.
It was impossible to exhibit a high voltage of 10 B1 or higher because of the power supply voltage. Therefore, in the circuit of the present invention, the second transistor TR2 is off -1X, and the first transistor TRI and the transistor TR3 have a high impedance with respect to the load circuit due to the diode D1, so the flybank pulse voltage is Vertical deflection coil [5 and capacitor C1
Due to the damping effect of the coil resistance of the resonant circuit constituted by the resistor R1 and the resistor R1, a voltage significantly higher than the power supply voltage 1B1 can be maintained. Furthermore, the pulse width of the pulse voltage generated from this resonant circuit can be considerably narrowed, and the retrace scanning speed can be increased accordingly. For comparison, in the circuit shown in Fig. 1, the voltage waveform when the diode D1 and capacitor C2 are not provided is as shown by the broken line in Fig. 2 Fdl, which shows that the operating characteristics of the circuit of the present invention are excellent. I hope you understand.

[Effects of the Invention] As is clear from the embodiments described above, according to the present invention,
By utilizing the fly-hack pulse generated during the retrace period in the vertical deflection output circuit, a simple circuit modification of installing a capacitor that resonates with the vertical deflection coil and a diode that isolates the output circuit transistor can eliminate the conventional complicated pump. It is possible to easily achieve the same reduction in power consumption as in the up circuit and shorten the retrace period.

Although the preferred embodiments of the present invention have been described above, it goes without saying that various design changes can be made without departing from the spirit of the present invention.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the vertical deflection output circuit according to the present invention, and FIG. 2 is a waveform diagram showing the operating state of the load circuit shown in FIG. 1. TRI~TR4,, l-rundisk1) 1~D3゜3. Diodes 01 to C4, , Capacitor RI-R11, , Resistor 0. , Vertical deflection coil patent applicant Nippon Chemi-Con Co., Ltd. FIo, 1 FIG 2

Claims (1)

[Claims] (1) The first transistor and the second transistor are connected in series with the diode with the same polarity through a diode so that the first transistor and the second transistor conduct alternately during the positive period and the negative period of a sawtooth wave signal of a predetermined period that is applied. and a load circuit in which a capacitor is connected in parallel between the anode of the diode and the vertical deflection coil.