JPH01243721A - Power mos fet driving circuit - Google Patents

Abstract

PURPOSE:To suppress the gate charging current of each power MOS FET to a prescribed value, and to prevent the deterioration of each power MOS FET due to a surge voltage by laying a common mode choke coil between the gates of the power MOS FET. CONSTITUTION:A common mode choke coil (current transformer) L1 is laid between the gate circuits of power MOS FETs Q1 and Q2. When a gate signal flows through the respective FETs Q1 and Q2, a charging current equivalent to the gates of the respective FETs Q1 and Q2 flows according to the low of equal ampere-turns of a common mode choke coil L1, etc., and the time for the gate voltages of the respective FETs Q1 and Q2 to arrive at a threshold voltage corresponds to each other.

Description

[Detailed Description of the Invention] [Summary] The present invention provides a switching power supply or the like that drives a plurality of power MOSFETs in parallel and/or series.
In order to suppress the generation of surge voltage due to variations in the gate charging current of the OSFET, each power MOSF
A common mode choke coil is inserted between the gate circuits of the ETs to suppress the gate charging current of each power MOSFET to a predetermined value, thereby preventing the power MOSFETs from being degraded or damaged by surge voltage.

[Industrial Application Field] The present invention relates to a power MOSFET drive circuit, and particularly to a power MOSFET drive circuit used in a switching power supply or the like.

[Conventional technology]

Various types of switching power supplies have been proposed, and among these, in switching power supplies with forward converters, if the current capacity is insufficient just by amplifying the output of the drive transformer with a single power MOSFET, , as shown in FIG. 6, a plurality of power MOSFETs QI, Q2 are connected to the output circuit of the drive transformer T1
A method is adopted in which Q3 is interposed in parallel and these are driven simultaneously.

If a single power MOSFET does not have enough breakdown voltage, a method is adopted in which each output of the drive transformer T1 drives the power MOSFETs Q1 and Q2, as shown in FIG.

[Problem to be solved by the invention]

However, in the system shown in FIG.
3 has a positive temperature coefficient for each on-resistance (■ os drain current has a negative temperature coefficient), so in the completely on region, the drain current is balanced, but during transitions, that is, turn-on and turn-off, the wiring inductance, As shown in Fig. 7, the current value (■.-3 drain current) between each element differs greatly due to variations in the resistances R1, R2, R3, etc. due to the wiring. Q2. There was a risk that Q3 would be damaged.

Also, in the case of the method shown in Fig. 8, each FET Q1, Q
The drain-source voltage of each winding N1, N2 . Due to differences in N3 coupling, wiring resistance, wiring inductance variations, etc.
As shown in FIG. 9, an unbalanced surge voltage occurs when the FET is turned off, and there is a possibility that the FETs Q1 and Q2 may be damaged.

The present invention has been made in view of the above-mentioned conventional problems, and an object of the present invention is to provide a power MOSFET drive circuit that can prevent damage to the power MOSFET due to unbalance of the gate charging current of the power MOSFET. It's about doing.

[Means to solve the problem]

In order to achieve the above object, the present invention provides a plurality of powers M
In a switching power supply that parallels and/or drives OS FETs, a common mode choke coil is inserted between the gate circuits of each power MOSFET to connect each power MOSFET.
Power MOS that equalizes the gate charging current of OSFET
This is a configuration of an FET drive circuit.

[For production]

Since the gate current flows through the gate of each power MOSFET via the common mode choke coil, the gate charging current of each power MOSFET is equalized due to the law of equal ampere turns of the common mode choke coil, and the gate charging current is unbalanced. Power MOSFE
It is possible to prevent the T from being damaged.

〔Example〕

FIG. 1 shows the configuration of an embodiment of the present invention.

This embodiment uses a power MOSFET as shown in the figure.
A common mode choke coil (current transformer) Ll is interposed between the gate circuits of QI and Q2, and the other configuration is the same as that in Fig. 6, so the same parts are given the same symbols. Therefore, their explanation will be omitted. Note that the number of turns of the common mode choke coil L1 on the FETQl side is set to N2, and the number of turns of the FETQ2 example is set to N1=N2.

In the above configuration, when a gate signal flows to each FET QI, Q2, each FET follows the law of equal ampere turns of the common mode choke coil L1, as shown in FIG.
As shown by the broken line in FIG. 2, a current of gate charging current 1g+=Igz flows through the gates of ETQI and Q2. Note that when the common mode choke coil Ll is not provided, gate charging currents 1g+ and Igz as shown by solid lines flow through each of the FETs QI and Q2.

In this way, since the same charging current flows through the gates of each FETQI and Q2, the time when the gate voltage of each FETQI and Q2 reaches the threshold voltage coincides, and each FET
The drain-source currents of QI and Q2 are ■. -31-IIl
A current of 3+ flows. Therefore, a surge voltage exceeding the withstand voltage of each FET QI and Q2 is not generated due to an unbalance in the gate charging current, and damage to the FETs QI and Q2 due to an unbalance in the gate charging current can be prevented.

In addition, each output signal of the drive transformer T is connected to a power MO5FET.
QI, Q2. When driving Q3, each FETQI, Q
2, common mode choke coils LL, L2. By interposing L3, the same effect as in the previous embodiment can be obtained (see FIG. 3).

FIG. 4 shows the configuration of yet another embodiment of the present invention.

In this embodiment, a common mode choke coil Ll is inserted between the gate circuits of FETQI and Q2, and the other configuration is the same as that in FIG. 8, so it is the same as or equivalent to that in FIG. Components are given the same reference numerals and their descriptions will be omitted.

In this embodiment, as in the previous embodiment, FETQ1, Q
When a gate signal is applied to FET 2, a gate charging current of 1 g is applied to the gate of each FET QI and Q2, as shown by the broken line in FIG. 5, due to the law of equal ampere turns of the common mode choke coil Ll.

Igz flows. That is, the game of FETQI, Q2
An equal charging current flows through both. Note that the windings N1 and N2 of the common mode choke coil L1 are such that N1=N2.

In this way, in this embodiment as well, each FETQ1, Q2
Since equal charging current flows through the gates of each FETQ
The time for the gate voltages of FETs I and Q2 to reach the threshold voltage becomes equal, and the drain-source voltages of each FET Q1 and Q2 become equal, as shown by the broken lines in FIG.
FETQI.

Surge voltage ■ when Q2 turns off. , by FET
It is possible to prevent QI and Q2 from being damaged.

Note that the configuration of the first Japanese invention can be implemented with a drive circuit such as a step motor.

[Effects of the Invention] As explained above, according to the present invention, each power MOSF
A common mode choke coil is inserted between the gate circuits of the ETs to suppress the gate charging current of each power MOSFET to a predetermined value.
Even if there are variations in wiring resistance, wiring inductance, etc. in the ET gate circuit, each power MOSFET can be driven without being damaged, which has the excellent effect of contributing to improved reliability. It will be done.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing one embodiment of the present invention, and Fig. 2 is a circuit diagram showing an embodiment of the present invention.
3 is a circuit diagram showing another embodiment of the present invention, FIG. 4 is a circuit diagram showing still another embodiment of the present invention, and FIG. 6 is a circuit diagram of a conventional example; FIG. 7 is a waveform diagram for explaining the operation of FIG. 6; FIG. 8 is a circuit diagram of another conventional example. FIG. 9 is a waveform diagram for explaining the operation of FIG. 8. In FIGS. 1, 3, and 4, T, TI are drive transformers, Q1, Q2. Q3 is a power MOSFET, L1, L2.
L3 is a common mode choke coil.

Claims (4)

[Claims] (1) In a power MOSFET drive circuit that drives multiple power MOSFETs (Q1, Q2), each power
Common mode choke coils (L1, L2, L3) are interposed between the gate circuits of the OSFETs to
A power MOSFET drive circuit characterized by equalizing the gate charging current of T. (2) The plurality of power MOSFETs are power MOSFETs that are simultaneously switched in parallel in a switching power supply.
The power MOSFET drive circuit according to claim 1, wherein each of the power MOSFET drive circuits is an SFET. (3) The power MOSFET drive circuit according to claim 1, wherein the plurality of power MOSFETs are power MOSFETs that are switched simultaneously in parallel to drive a step motor. (4) The power MOSFET drive circuit according to claim 1, wherein the plurality of power MOSFETs are power MOSFETs connected in series and switched simultaneously in a switching power supply.