WO1990013178A1

WO1990013178A1 - Gate drive circuit for power transistor

Info

Publication number: WO1990013178A1
Application number: PCT/US1990/001258
Authority: WO
Inventors: Paul E. Nuechterlein
Original assignee: Sundstrand Corporation
Priority date: 1989-04-19
Filing date: 1990-03-06
Publication date: 1990-11-01

Abstract

The problem of reliability in gate drive circuits is resolved with an isolated gate drive circuit (10) for a power transistor (12) gated in response to the presence of a control signal. The drive circuit (10) includes a transformer (18) having a primary winding (22) and a secondary winding (24, 26). A switch (S) is coupled in series with the transformer primary winding (22) and a source (30) of power for receiving the control signal and connecting the power source (30) across the primary winding (22) responsive thereto. A first control switch (Q1) is coupled to the secondary winding (24, 26) and the power transistor (12) for controlling a conducting state of the power transistor (12) responsive to the presence of the control signal. A second control switch (Q2) is coupled to the transformer secondary winding (24, 26) and to the power transistor (12) for controlling a non-conducting state of the power transistor (12) virtually instantly upon removal of the control signal. A rectifier circuit (34) is coupled to the first and second control switches (Q1, Q2) for preventing operation of the first control switch (Q1) if the second control switch (Q2) is unable to control the non-conducting state of the power transistor (12).

Description

GATE DRIVE CIRCUIT FOR POWER TRANSISTOR

Field of the Invention

This invention relates to a transistor drive circuit and more particularly to an improved gate drive circuit for a power transistor.

Background of the Invention

Power transistors are commonly used in electronic power applications, such as in a DC-DC converter. It is therefore required that the power transistor be capable of switching at a high frequency between conducting and non-conducting states, and vice versa. In aerospace applications in particular, for example aircraft power generating systems, reliability of operation is important.

A reliable drive circuit must operate under conditions which present different problems to the designer of such a circuit. .Among these problems are the requirement that the power transistor must be capable of switching both long and short duty cycle wave forms. Secondly, the maximum positive gate to source voltage must be maintained between selected levels whenever the duty cycle is greater than, for example, five percent to prevent excess power transistor heating due to insufficient voltage, without the possibility of damage due to excessive voltage. Thirdly, the gate to source voltage during shutoff periods should be between zero and a select negative voltage level to ensure that the power transistor becomes completely non-conductive. Fourthly, the gate drive circuit should supply dielectric isolation between the power transistor terminals and the source of control signal. As a result, a voltage between a power transistor terminal and the control signal terminal will not cause a corresponding current to flow. Fifthly, the - 2 -

transitions of the gate to source voltage between conducting and non-conducting states must be rapid to reduce switching loss in the power transistor. For example, in high frequency aerospace applications the transition time must be less than 100 nanoseconds. Finally, the gate drive circuit must present a low impedance on the order of, for example, less than 20 ohms, between the source and gate terminals to minimize the susceptibility of the gate drive circuit to noise. The present invention is intended to overcome the problems set forth above in a novel and simple manner.

Summary of the Invention

In accordance with the present invention, a reliable gate drive circuit satisfies each of the requirements discussed above.

Broadly, there is disclosed herein an isolated gate drive circuit for a power transistor gated in response to the presence of a control signal. The drive circuit includes a transformer having a primary winding and a secondary winding. Switching means are coupled in series with the transformer primary winding and a source of power for receiving the control signal and connecting the power source across the primary winding responsive thereto. First control means are coupled to the secondary winding and the power transistor for controlling a conducting state of the power transistor responsive to the presence of the control signal. Second switch control means are coupled to the transformer secondary winding and to the power transistor for controlling a non-conducting state of the power transistor virtually instantly upon removal cf the control signal. Override control means are coupled to the first and second switch control means for preventing operation of the - 3 -

first switch control means if the second switch control means is unable to control the non-conducting state of the power transistor.

It is a feature of the invention that the transformer includes dual secondary windings.

It is another feature of the invention that the first switch control means comprises a transistor.

It is a further feature of the invention that the second switch control means comprises a transistor. It is yet another feature of the invention that the second switch control means comprises a capacitor coupled across the secondary winding.

It is still another feature of the invention that the override control means comprises a rectifier circuit. In another aspect of the invention, an isolated gate drive circuit is provided for a power transistor having gate, source and drain terminals wherein the transistor is controllably gated in response to the presence of a control signal to provide conduction between the source and drain terminals. The drive circuit includes a transformer having a primary winding and first and second secondary windings, wherein the first secondary winding is connected to the power transistor source terminal. Switching means are coupled in series with the transformer primary winding and a source of power for receiving the control signal and connecting the power source across the primary winding responsive thereto. A first switching transistor is operatively coupled between the first secondary winding and the gate terminal of the power transistor for controlling a conducting state of the power transistor responsive to the presence of the control signal. A capacitor is coupled across the second secondary winding. A second switching transistor is operatively coupled to the capacitor and to the power transistor gate terminal for controlling a non-conducting state of the power transistor virtually instantly upon removal of the control signal.

Further, the gate drive circuit may include a rectifier circuit coupled to the first switching transistor and the capacitor for preventing operation of the first switching transistor if the capacitor is not charged sufficiently to control the non-conducting state of the power transistor. It is an additional feature of the invention that the first and second secondary windings are tightly coupled.

It is still a further feature of the invention that the gate drive circuit further comprises means coupled to the power transistor for maintaining the power transistor in the non-conducting state if the control signal is absent for an extended length of time.

In an illustrative embodiment, the gate drive circuit includes a transformer for isolating a source of control signal from the power transistor. The control signal operates a switch connected in series with the primary winding of the transformer and a DC power source. The transformer includes two series connected secondary windings. The first secondary winding is connected through a first diode to the source of a P channel FET, the drain of which is connected to a second diode, which second diode is connected to the gate of the power transistor. The source of the power transistor is connected to the junction of the two secondary windings. A capacitor is series connected with a third diode between this junction and the low side of the second secondary winding. The operation of this portion of the circuit is as follows, when the control signal is present, a current is induced in each of the secondary windings causing the two diodes and the P channel FET to conduct which applies a positive gate to source voltage across the power transistor which is therefor conducting.

To ensure the proper turnoff of the power transistor, the circuit includes a second P channel FET including its drain connected directly to, and its gate through a resistor to, the negative charge side of the capacitor, and its source connected to the gate of the power transistor. Thus, when the control signal is removed, the first P channel FET stops conducting. The reverse voltage from the capacitor causes the second P channel FET to conduct which directly applies the reverse voltage from the capacitor to the gate of the power transistor to render it non-conductive. Rapid turnoff of the power transistor is thereby also accomplished. In order to ensure that the capacitor is sufficiently charged to provide turnoff of the power transistor, a voltage regulator circuit comprising a diode, a zener diode and a capacitor is operatively connected to the first capacitor and the first P channel FET to prevent such first P channel FET from turning on if the charge across the capacitor is not sufficient to ensure adequate turnoff of the power transistor.

Further features and advantages of the invention will readily be apparent from the specification and from the drawings.

Brief Description of the Drawings

Fig. 1 is a generalized block diagram illustrating the coupling of a gate drive circuit between a source of control signal and a power transistor; Fig. 2 is an electrical schematic of a gate drive circuit according to the invention; and - 6 -

Fig. 3 is a series of wave forms illustrating the operation of the circuit of Fig. 2.

Description of the Invention

Referring first to Fig. 1, a gate drive circuit 10 is provided for gating a power transistor 12 in response to the presence of a control signal received from a source 14 of control signal. In the illustrative embodiment, the power transistor 12 comprises a field-effect transistor, or FET, including source, drain and gate terminals, indicated as S, D and G, respectively, as is well known. More specifically, in the illustrative embodiment, the power transistor 12 comprises an N-channel FET which provides a conduction path between the drain and source terminals when a positive gate to source voltage, labelled V_s is applied thereto.

The gate drive circuit of this invention^' is particularly suited for use in connection with a MOSFET in aerospace power generating systems owing to its fast switching speed and reliability. Nevertheless, the gate drive circuit according to the invention could be used in- connection with any semiconductor switching device, as will be apparent to those skilled in the art.

With reference to Fig. 2, an electrical schematic illustrates the gate drive circuit 10 according to the invention. The gate drive circuit 10 includes a primary switching circuit 16, a transformer 18, and a secondary switching circuit 20.

The transformer 18 includes a primary winding 22, first and second secondary windings 24 and 26, respectively, and an electrostatic shield 28. The first and second secondary windings 24 and 26 are tightly coupled so that the voltage produced in each winding is virtually identical, as - 7 -

is well known. The electrostatic shield 28 prevents capacitively induced current from flowing between the primary winding 22 and the secondary windings 24 and 26.

The transformer 18 is a desirable element in the gate drive circuit 10 due to its inherently simplicity and reliability. Specifically, it is capable of handling both power and signal levels. However, the transformer windings cannot be directly connected to the power transistor control terminals because the long-term average voltage across any transformer winding is always zero. This problem makes the transformer incompatible with the above-described second requirement whenever the gate drive circuit 12 must supply both short duty cycle and long duty cycle switching signals. The primary switching circuit 16 includes a source 30 of DC power which comprises a thirteen volt DC source in the illustrated embodiment. The primary winding 22 is coupled in series with a switch S across the power source 30. The switch S can be any known type of switch and is driven by the source of control signal 14. In the illustrated embodiment, the switch S comprises a transistor which is driven by the control signal source 14.

The secondary switching circuit 20 includes a diode Dl connected between the high voltage side of the first secondary winding 24 and the source terminal of a first P-channel FET Ql. The drain terminal of the first P-channel FET Ql is connected through a second diode D2 to the gate terminal of the power transistor 12. The source terminal of the power transistor 12 is connected to a junction 32 between the secondary windings 24 and 26. A resistor Rl is coupled between the source terminal and gate terminal of the FET Ql. A capacitor Cl is connected between the gate terminal of the FET Ql and the - 8 -

junction 32. A second resistor R2 is connected between the gate and source terminals of the power transistor 12.

A second capacitor C2 is coupled to- the junction 32 and via a third diode D3 to the low voltage side of the second secondary winding 26. A rectifier circuit 34, comprising a zener diode Zl oppositely connected in a series with a fourth diode D4, is connected between the gate terminal of the FET Ql and the low side of the second secondary winding 26. Finally, a second P-channel FET Q2 has its gate and source terminals connected across the second diode D2 and its drain terminal connected to the junction between the second capacitor C2 and the third diode

D3. A third riesistor R3 is coupled across the gate and

^" drain tι_erminals of the second P-channel FET Q2. The operation of the gate drive circuit 10 is intended to render conduction of the power transistor 12 responsive to the presence of a control signal from the source 14, and to render the power transistor 12 non-conductive in the absence of a control signal. If a control signal is received from the source

14, then the switch S conducts and the thirteen volts from the DC source 30 is induced in each of the transformer secondary windings 24 and 26. The thirteen volts established across the first secondary winding 24 causes the first diode Dl to conduct resulting in a negative gate to source voltage for the first P-channel FET Ql causing it to conduct. Therefore, the second diode D2 conducts resulting in a positive gate to source voltage for the power transistor 12 so that the power transistor 12 conducts, as is expected.

Simultaneously, thirteen volts is induced across the second secondary winding 26 so that the third diode D3 conducts to charge the second capacitor C2 to a voltage - 9 -

level labelled V2. The exact level of the voltage V2 depends upon the duty cycle and the frequency. Under normal conditions, and assuming the circuit is operating a high frequency, the capacitor voltage V2 will generally be maintained at a level on the order of approximately ten to twelve volts.

As described in greater detail below, the voltage across the second capacitor C2 is utilized to provide turnoff of the power transistor 12. For reliability, it is necessary to ensure that a sufficient voltage be established across the second capacitor C2 to ensure complete turnoff of the power transistor 12. The normal charge level of ten to twelve volts is sufficient to ensure turnoff. Under low duty cycle operation, however, the capacitor C2 may not maintain a sufficient charge level. The rectifier circuit 34 operates in connection with the first capacitor Cl under such conditions to prevent the power transistor 12 from even turning on.

Under normal operating conditions, with the control signal present, full voltage, i.e., on the order of twenty six volts, is induced across both secondary windings

24 and 26, i.e., thirteen volts across each winding 24 and

26. Therefore, if diodes Dl and D2 are each assumed to have a one volt drop, there is a twenty four volt drop across the series-connected first resistor Rl and rectifier circuit 34.

In the illustrated embodiment, the zener diode Zl has a breakdown voltage of twelve volts. Therefore, the zener diode Zl conducts and twelve volts is dissipated across the first resistor Rl. The voltage VI across the first capacitor Cl is approximately zero. This results in the first P-channel FET Ql being turned on.

If the voltage V2 across the second capacitor is insufficient to ensure proper turnoff of the power transistor 12, i.e., less than six volts in the illustrated embodiment, then a voltage Vg2 across the second secondary winding 26 is necessarily less than approximately seven volts. Owing to the tightly coupled relationship between the secondary windings 24 and 26, the voltage Vgi across the first secondary winding 24 is also less than seven volts in such situation. Therefore, the voltage across the first resistor Rl and the zener Zl is less than the combined total voltage, which is less than fourteen volts. Since the voltage drop across the zener diode Zl is twelve volts, the drop across the first resistor Rl is less than two volts.

This voltage drop is insufficient to turn on the first

P-channel FET Ql.

Therefore, the rectifier circuit 34 acts as an override for preventing operation of the first P-channel FET

Ql if the voltage V2 across the second capacitor C2 is insufficient to ensure proper turnoff of the power transistor 12, as discussed below.

Again assuming normal operation, if the power transistor 12 is conducting and the control signal is removed, then the switch S stops conducting. The voltage across the secondary windings 24 and 26 immediately changes to a negative voltage which eventually dampens out to zero voltage. As a result, the first diode Dl no longer conducts, and the first P-channel FET Ql cannot then conduct. This allows the third resistor R3 to apply a reverse voltage, developed by the capacitor C2, to the second diode D2 to cause the second P-channel FET Q2 to conduct. Current through the second P-channel FET Q2 causes the gate to source voltage VQS of the power transistor 12 to quickly change from positive to negative. Rapid turnoff of the power transistor 12 is thus provided. The second resistor R2 is operable to maintain the power transistor 12 off if no voltage is developed across the transformer 18 for long periods of time. Specifically, the second resistor R2 ensures that the power transistor gate voltage VQS remains zero by dissipating any parasitic currents which can be developed by elements (e.g., a gate-to-drain resistor across the power transistor 12, not shown in Figure 2) .

The above described problems to be solved by a gate drive circuit are satisfied with the circuit 10 according to the invention as follows. Long and short duty cycle requirements are supplied owing to the rapid turn-on and turnoff of the power transistor 12. The maximum positive value of V<-g being between 10 and 12 volts is provided by the second capacitor C2 preventing turn-on. The minimum value of VQS being between zero and -10 volts is provided by reverse coupling the capacitor C2 across the power transistor using the second P-channel FET Q2. Dielectric isolation is provided by the transformer 18. Rapid transitions of the power transistor 12 are accomplished as generally discussed above. Low impedance is provided by the first P-channel Ql in the on state, and by the second P-channel FET Q2 in the off state, each of which effectively acts as a short circuit.

Operation of the gate drive circuit 10 is further illustrated with reference to the waveforms of Fig. 3. Specifically, waveforms 3a-3d illustrate operation under normal conditions. Waveform 3a illustrates the control voltage across the switch S for a normal duty cycle. Wave form 3b illustrates the induced voltage in either secondary winding Vgi or Vg2 which is, as discussed above, on the order of thirteen volts when the control signal is present, quickly switches to negative thirty nine volts upon removal of the control signal and then dampens to zero volts. The voltage V-> across the third resistor R3 switches between -11 volts and +12 volts depending upon whether or not the control signal is present or absent, respectively. Resultantly, if the control signal is present, the power transistor gate voltage V<-g is on the order of twelve volts in the presence of a control signal, and in the absence of a control signal is less than or equal to zero volts.

Under extremely low duty cycle conditions, as illustrated in wave forms 3e-3h, which respectively correspond to wave forms 3a-3d, the first P-channel FET Ql remains non-conducting at all times. Specifically, the maximum voltage Vg of the secondary windings 24 and 26 is on the order of six volts in the illustrated example. As discussed above, the first P-channel FET Ql does not conduct under such circumstances. As a result, the voltage V-> remains at all times at the voltage of the voltage V2 across the capacitor C2 which in the illustrated example is on the order of -6 volts, so that the gate voltage V^g of the power transistor 12 is approximately -3 volts.

As will be appreciated, the specific voltage levels are for illustration only and would depend upon the particular circuit utilized and the instantaneous operating conditions. Thus, the invention broadly comprehends a gate drive circuit which is operable to effectively drive the power transistor.

Claims

I Claim;

1. An isolated gate drive circuit for a power transistor gated in response to the presence of a control signal, comprising: 4 a transformer having a primary winding and a secondary winding; δ switching means coupled in series with said transformer primary winding and a source of power for 8 receiving the control signal and connecting the power source across the primary winding responsive thereto; 10 first switch control means coupled to said secondary winding and said power transistor for controlling 12 a conducting state of said power transistor responsive to the presence of the control signal; 14 second switch control means coupled to said transformer secondary and to said power transistor for 16 controlling a nonconducting state of said power transistor virtually instantly upon removal of the control signal; and 18 override control means coupled to said first and second switch control means for preventing operation of said 20 first switch control means if said second switch control means is unable to control the nonconducting state of the 22 power transistor.

2. The gate drive circuit of claim 1 wherein 2 said transformer includes two secondary windings.

3. The gate drive circuit of claim 1 wherein 2 said first switch control means comprises a transistor.

4. The gate drive circuit of claim 1 wherein 2 said second switch control means comprises a transistor.

5. The gate drive circuit of claim 1 wherein said second switch control means comprises a capacitor coupled across said secondary winding.

6. The gate drive circuit of claim 1 wherein said override control means comprises a rectifier circuit.

7. An isolated gate drive circuit for a power transistor having gate, source and drain terminals wherein the transistor is controllably gated in response to the presence of a control signal to provide conduction between the source and drain terminals, comprising: a transformer having a primary winding and first and second secondary windings, wherein said first secondary winding is connected to the power transistor source terminal; switching means coupled in series with said transformer primary winding and a source of power for receiving the control signal and connecting the power source across the primary winding responsive thereto; a first switching transistor operatively coupled between said first secondary winding and the gate terminal of the power transistor for controlling a conducting state of said power transistor responsive to the presence of the control signal; a capacitor coupled across said second secondary winding; and a second switching transistor operatively coupled to said capacitor and to the power transistor gate terminal for controlling a nonconducting state of said power transistor virtually instantly upon removal of the control signal.

8. The gate drive circuit of claim 7 further comprising a rectifier circuit coupled to said first switching transistor and said capacitor for preventing operation of said first switching transistor if said capacitor is not charged sufficiently to control the nonconducting state of the power transistor.

9. The gate drive circuit of claim 7 wherein said first and said second secondary windings are tightly coupled.

10. The gate drive circuit of claim 7 further comprising means coupled to the power transistor for maintaining the power transistor in the non-conducting state if the control signal is absent for an extended length of time.

11. An isolated gate drive circuit for a power transistor having gate, source and drain terminals wherein the transistor is controllably gated in response to the presence of a control signal to provide conduction between the source and drain terminals, comprising: a transformer having a primary winding and first and second secondary windings, wherein said first secondary winding is connected to the power transistor source terminal; switching means coupled in series with said transformer primary winding and a source of power for receiving the control signal and connecting the power source across the primary winding responsive thereto; a first switching means operatively coupled between said first secondary winding and the gate terminal of the power transistor for controlling a conducting state of said power transistor responsive to the presence of the control signal; a capacitor coupled across said second secondary winding; a second switching means operatively coupled to said capacitor and to the power transistor gate terminal for controlling a nonconducting state of said power transistor virtually instantly upon removal of the control signal; and an override control circuit coupled to said first switching means, said transformer secondary windings and said capacitor for preventing operation of said first switching means if said second switching means is unable to control the nonconducting state of the power transistor.