JPS6225212B2 - - Google Patents

Info

Publication number
JPS6225212B2
JPS6225212B2 JP57092810A JP9281082A JPS6225212B2 JP S6225212 B2 JPS6225212 B2 JP S6225212B2 JP 57092810 A JP57092810 A JP 57092810A JP 9281082 A JP9281082 A JP 9281082A JP S6225212 B2 JPS6225212 B2 JP S6225212B2
Authority
JP
Japan
Prior art keywords
flip
flop
scan
circuit
tri
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP57092810A
Other languages
English (en)
Japanese (ja)
Other versions
JPS58208858A (ja
Inventor
Katsuichi Hirowatari
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP57092810A priority Critical patent/JPS58208858A/ja
Publication of JPS58208858A publication Critical patent/JPS58208858A/ja
Publication of JPS6225212B2 publication Critical patent/JPS6225212B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/3185Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318583Design for test
    • G01R31/318586Design for test with partial scan or non-scannable parts

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
JP57092810A 1982-05-31 1982-05-31 スキヤンル−プ回路制御方式 Granted JPS58208858A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57092810A JPS58208858A (ja) 1982-05-31 1982-05-31 スキヤンル−プ回路制御方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57092810A JPS58208858A (ja) 1982-05-31 1982-05-31 スキヤンル−プ回路制御方式

Publications (2)

Publication Number Publication Date
JPS58208858A JPS58208858A (ja) 1983-12-05
JPS6225212B2 true JPS6225212B2 (enrdf_load_html_response) 1987-06-02

Family

ID=14064761

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57092810A Granted JPS58208858A (ja) 1982-05-31 1982-05-31 スキヤンル−プ回路制御方式

Country Status (1)

Country Link
JP (1) JPS58208858A (enrdf_load_html_response)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2643789B2 (ja) * 1993-09-01 1997-08-20 日本電気株式会社 スキャンパス回路

Also Published As

Publication number Publication date
JPS58208858A (ja) 1983-12-05

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