JPS6224875B2 - - Google Patents
Info
- Publication number
- JPS6224875B2 JPS6224875B2 JP57027105A JP2710582A JPS6224875B2 JP S6224875 B2 JPS6224875 B2 JP S6224875B2 JP 57027105 A JP57027105 A JP 57027105A JP 2710582 A JP2710582 A JP 2710582A JP S6224875 B2 JPS6224875 B2 JP S6224875B2
- Authority
- JP
- Japan
- Prior art keywords
- signal
- shot
- potential
- digit line
- data bus
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
Landscapes
- Static Random-Access Memory (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57027105A JPS58146088A (ja) | 1982-02-22 | 1982-02-22 | メモリ回路 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57027105A JPS58146088A (ja) | 1982-02-22 | 1982-02-22 | メモリ回路 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS58146088A JPS58146088A (ja) | 1983-08-31 |
JPS6224875B2 true JPS6224875B2 (enrdf_load_stackoverflow) | 1987-05-30 |
Family
ID=12211799
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP57027105A Granted JPS58146088A (ja) | 1982-02-22 | 1982-02-22 | メモリ回路 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58146088A (enrdf_load_stackoverflow) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01120884U (enrdf_load_stackoverflow) * | 1988-02-09 | 1989-08-16 |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60103586A (ja) * | 1983-11-11 | 1985-06-07 | Nec Corp | スタテイツク型半導体記憶装置 |
JPH0743935B2 (ja) * | 1985-03-25 | 1995-05-15 | 日立超エル・エス・アイ・エンジニアリング株式会社 | スタティック型ram |
JPH0831277B2 (ja) * | 1985-11-07 | 1996-03-27 | 日本電気株式会社 | 論理回路 |
JPS62170091A (ja) * | 1986-01-21 | 1987-07-27 | Nec Corp | 半導体記憶装置 |
US4825416A (en) * | 1986-05-07 | 1989-04-25 | Advanced Micro Devices, Inc. | Integrated electronic memory circuit with internal timing and operable in both latch-based and register-based systems |
JPH01211394A (ja) * | 1988-02-19 | 1989-08-24 | Sony Corp | メモリ装置 |
US4985865A (en) * | 1988-12-21 | 1991-01-15 | Texas Instruments Incorporated | Asymmetrical delay for controlling word line selection |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5619587A (en) * | 1979-07-27 | 1981-02-24 | Nec Corp | Memory circuit |
-
1982
- 1982-02-22 JP JP57027105A patent/JPS58146088A/ja active Granted
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01120884U (enrdf_load_stackoverflow) * | 1988-02-09 | 1989-08-16 |
Also Published As
Publication number | Publication date |
---|---|
JPS58146088A (ja) | 1983-08-31 |
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