JPS62246198A - メモリ・セル用読取回路 - Google Patents

メモリ・セル用読取回路

Info

Publication number
JPS62246198A
JPS62246198A JP62043237A JP4323787A JPS62246198A JP S62246198 A JPS62246198 A JP S62246198A JP 62043237 A JP62043237 A JP 62043237A JP 4323787 A JP4323787 A JP 4323787A JP S62246198 A JPS62246198 A JP S62246198A
Authority
JP
Japan
Prior art keywords
bit line
memory cell
read
address
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62043237A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0524597B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html
Inventor
ケリー・バーンスタイン
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of JPS62246198A publication Critical patent/JPS62246198A/ja
Publication of JPH0524597B2 publication Critical patent/JPH0524597B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Static Random-Access Memory (AREA)
JP62043237A 1986-04-15 1987-02-27 メモリ・セル用読取回路 Granted JPS62246198A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US852465 1986-04-15
US06/852,465 US4742487A (en) 1986-04-15 1986-04-15 Inhibit and transfer circuitry for memory cell being read from multiple ports

Publications (2)

Publication Number Publication Date
JPS62246198A true JPS62246198A (ja) 1987-10-27
JPH0524597B2 JPH0524597B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1993-04-08

Family

ID=25313409

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62043237A Granted JPS62246198A (ja) 1986-04-15 1987-02-27 メモリ・セル用読取回路

Country Status (4)

Country Link
US (1) US4742487A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
EP (1) EP0242539B1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JP (1) JPS62246198A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
DE (1) DE3786478T2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5146572A (en) * 1980-11-17 1992-09-08 International Business Machines Corporation Multiple data format interface
US4811296A (en) * 1987-05-15 1989-03-07 Analog Devices, Inc. Multi-port register file with flow-through of data
JPH01178193A (ja) * 1988-01-07 1989-07-14 Toshiba Corp 半導体記憶装置
US4969125A (en) * 1989-06-23 1990-11-06 International Business Machines Corporation Asynchronous segmented precharge architecture
JPH04257048A (ja) * 1991-02-12 1992-09-11 Mitsubishi Electric Corp デュアルポートメモリ
US5404271A (en) * 1991-07-30 1995-04-04 Kabushiki Kaisha Toshiba Electronic apparatus having a card storing section formed within a body between a support frame and an upper case of the body and having functional elements mounted between the support frame and a lower case of the body
JPH05250872A (ja) * 1992-03-09 1993-09-28 Oki Electric Ind Co Ltd ランダム・アクセス・メモリ
JPH05266654A (ja) * 1992-03-17 1993-10-15 Mitsubishi Electric Corp マルチポートメモリ装置
US5502683A (en) * 1993-04-20 1996-03-26 International Business Machines Corporation Dual ported memory with word line access control
US8397034B1 (en) 2003-06-27 2013-03-12 Cypress Semiconductor Corporation Multi-port arbitration system and method
US7516280B1 (en) 2004-03-30 2009-04-07 Cypress Semiconductor Corporation Pulsed arbitration system and method
US7813213B1 (en) 2005-05-04 2010-10-12 Cypress Semiconductor Corporation Pulsed arbitration system

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4280197A (en) * 1979-12-07 1981-07-21 Ibm Corporation Multiple access store
US4541076A (en) * 1982-05-13 1985-09-10 Storage Technology Corporation Dual port CMOS random access memory
JPS5968889A (ja) * 1982-10-08 1984-04-18 Toshiba Corp 半導体記憶装置
US4535428A (en) * 1983-03-10 1985-08-13 International Business Machines Corporation Multi-port register implementations
US4577292A (en) * 1983-05-31 1986-03-18 International Business Machines Corporation Support circuitry for multi-port systems
US4616347A (en) * 1983-05-31 1986-10-07 International Business Machines Corporation Multi-port system
US4598387A (en) * 1983-09-29 1986-07-01 Advanced Micro Devices, Inc. Capacitive memory signal doubler cell

Also Published As

Publication number Publication date
DE3786478T2 (de) 1994-02-17
US4742487A (en) 1988-05-03
JPH0524597B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1993-04-08
DE3786478D1 (de) 1993-08-19
EP0242539B1 (en) 1993-07-14
EP0242539A3 (en) 1990-05-16
EP0242539A2 (en) 1987-10-28

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